1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <endian.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/ufs.h> 19 #include <lib/mmio.h> 20 21 #define CDB_ADDR_MASK 127 22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK) 23 #define ALIGN_8(x) (((x) + 7) & ~7) 24 25 #define UFS_DESC_SIZE 0x400 26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */ 27 28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */ 29 30 static ufs_params_t ufs_params; 31 static int nutrs; /* Number of UTP Transfer Request Slots */ 32 33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd) 34 { 35 unsigned int data; 36 37 if (base == 0 || cmd == NULL) 38 return -EINVAL; 39 40 data = mmio_read_32(base + HCS); 41 if ((data & HCS_UCRDY) == 0) 42 return -EBUSY; 43 mmio_write_32(base + IS, ~0); 44 mmio_write_32(base + UCMDARG1, cmd->arg1); 45 mmio_write_32(base + UCMDARG2, cmd->arg2); 46 mmio_write_32(base + UCMDARG3, cmd->arg3); 47 mmio_write_32(base + UICCMD, cmd->op); 48 49 do { 50 data = mmio_read_32(base + IS); 51 } while ((data & UFS_INT_UCCS) == 0); 52 mmio_write_32(base + IS, UFS_INT_UCCS); 53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK; 54 } 55 56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val) 57 { 58 uintptr_t base; 59 unsigned int data; 60 int result, retries; 61 uic_cmd_t cmd; 62 63 assert(ufs_params.reg_base != 0); 64 65 if (val == NULL) 66 return -EINVAL; 67 68 base = ufs_params.reg_base; 69 for (retries = 0; retries < 100; retries++) { 70 data = mmio_read_32(base + HCS); 71 if ((data & HCS_UCRDY) != 0) 72 break; 73 mdelay(1); 74 } 75 if (retries >= 100) 76 return -EBUSY; 77 78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 79 cmd.arg2 = 0; 80 cmd.arg3 = 0; 81 cmd.op = DME_GET; 82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 83 result = ufshc_send_uic_cmd(base, &cmd); 84 if (result == 0) 85 break; 86 data = mmio_read_32(base + IS); 87 if (data & UFS_INT_UE) 88 return -EINVAL; 89 } 90 if (retries >= UFS_UIC_COMMAND_RETRIES) 91 return -EIO; 92 93 *val = mmio_read_32(base + UCMDARG3); 94 return 0; 95 } 96 97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val) 98 { 99 uintptr_t base; 100 unsigned int data; 101 int result, retries; 102 uic_cmd_t cmd; 103 104 assert((ufs_params.reg_base != 0)); 105 106 base = ufs_params.reg_base; 107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 108 cmd.arg2 = 0; 109 cmd.arg3 = val; 110 cmd.op = DME_SET; 111 112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 113 result = ufshc_send_uic_cmd(base, &cmd); 114 if (result == 0) 115 break; 116 data = mmio_read_32(base + IS); 117 if (data & UFS_INT_UE) 118 return -EINVAL; 119 } 120 if (retries >= UFS_UIC_COMMAND_RETRIES) 121 return -EIO; 122 123 return 0; 124 } 125 126 static int ufshc_hce_enable(uintptr_t base) 127 { 128 unsigned int data; 129 int retries; 130 131 /* Enable Host Controller */ 132 mmio_write_32(base + HCE, HCE_ENABLE); 133 134 /* Wait until basic initialization sequence completed */ 135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) { 136 data = mmio_read_32(base + HCE); 137 if (data & HCE_ENABLE) { 138 break; 139 } 140 udelay(HCE_ENABLE_TIMEOUT_US); 141 } 142 if (retries >= HCE_ENABLE_INNER_RETRIES) { 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int ufshc_hce_disable(uintptr_t base) 150 { 151 unsigned int data; 152 int timeout; 153 154 /* Disable Host Controller */ 155 mmio_write_32(base + HCE, HCE_DISABLE); 156 timeout = HCE_DISABLE_TIMEOUT_US; 157 do { 158 data = mmio_read_32(base + HCE); 159 if ((data & HCE_ENABLE) == HCE_DISABLE) { 160 break; 161 } 162 udelay(1); 163 } while (--timeout > 0); 164 165 if (timeout <= 0) { 166 return -ETIMEDOUT; 167 } 168 169 return 0; 170 } 171 172 173 static int ufshc_reset(uintptr_t base) 174 { 175 unsigned int data; 176 int retries, result; 177 178 /* disable controller if enabled */ 179 if (mmio_read_32(base + HCE) & HCE_ENABLE) { 180 result = ufshc_hce_disable(base); 181 if (result != 0) { 182 return -EIO; 183 } 184 } 185 186 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) { 187 result = ufshc_hce_enable(base); 188 if (result == 0) { 189 break; 190 } 191 } 192 if (retries >= HCE_ENABLE_OUTER_RETRIES) { 193 return -EIO; 194 } 195 196 /* Enable Interrupts */ 197 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES | 198 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES; 199 mmio_write_32(base + IE, data); 200 201 return 0; 202 } 203 204 static int ufshc_dme_link_startup(uintptr_t base) 205 { 206 uic_cmd_t cmd; 207 208 memset(&cmd, 0, sizeof(cmd)); 209 cmd.op = DME_LINKSTARTUP; 210 return ufshc_send_uic_cmd(base, &cmd); 211 } 212 213 static int ufshc_link_startup(uintptr_t base) 214 { 215 int data, result; 216 int retries; 217 218 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) { 219 result = ufshc_dme_link_startup(base); 220 if (result != 0) { 221 /* Reset controller before trying again */ 222 result = ufshc_reset(base); 223 if (result != 0) { 224 return result; 225 } 226 continue; 227 } 228 assert((mmio_read_32(base + HCS) & HCS_DP) == 0); 229 data = mmio_read_32(base + IS); 230 if (data & UFS_INT_ULSS) 231 mmio_write_32(base + IS, UFS_INT_ULSS); 232 return 0; 233 } 234 return -EIO; 235 } 236 237 /* Check Door Bell register to get an empty slot */ 238 static int get_empty_slot(int *slot) 239 { 240 unsigned int data; 241 int i; 242 243 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 244 for (i = 0; i < nutrs; i++) { 245 if ((data & 1) == 0) 246 break; 247 data = data >> 1; 248 } 249 if (i >= nutrs) 250 return -EBUSY; 251 *slot = i; 252 return 0; 253 } 254 255 static void get_utrd(utp_utrd_t *utrd) 256 { 257 uintptr_t base; 258 int slot = 0, result; 259 utrd_header_t *hd; 260 261 assert(utrd != NULL); 262 result = get_empty_slot(&slot); 263 assert(result == 0); 264 265 /* clear utrd */ 266 memset((void *)utrd, 0, sizeof(utp_utrd_t)); 267 base = ufs_params.desc_base + (slot * sizeof(utrd_header_t)); 268 /* clear the descriptor */ 269 memset((void *)base, 0, UFS_DESC_SIZE); 270 271 utrd->header = base; 272 utrd->task_tag = slot + 1; 273 /* CDB address should be aligned with 128 bytes */ 274 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t)); 275 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t)); 276 utrd->size_upiu = utrd->resp_upiu - utrd->upiu; 277 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t)); 278 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu; 279 280 hd = (utrd_header_t *)utrd->header; 281 hd->ucdba = utrd->upiu & UINT32_MAX; 282 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX; 283 /* Both RUL and RUO is based on DWORD */ 284 hd->rul = utrd->size_resp_upiu >> 2; 285 hd->ruo = utrd->size_upiu >> 2; 286 (void)result; 287 } 288 289 /* 290 * Prepare UTRD, Command UPIU, Response UPIU. 291 */ 292 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, 293 int lba, uintptr_t buf, size_t length) 294 { 295 utrd_header_t *hd; 296 cmd_upiu_t *upiu; 297 prdt_t *prdt; 298 unsigned int ulba; 299 unsigned int lba_cnt; 300 int prdt_size; 301 302 hd = (utrd_header_t *)utrd->header; 303 upiu = (cmd_upiu_t *)utrd->upiu; 304 305 hd->i = 1; 306 hd->ct = CT_UFS_STORAGE; 307 hd->ocs = OCS_MASK; 308 309 upiu->trans_type = CMD_UPIU; 310 upiu->task_tag = utrd->task_tag; 311 upiu->cdb[0] = op; 312 ulba = (unsigned int)lba; 313 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT); 314 switch (op) { 315 case CDBCMD_TEST_UNIT_READY: 316 break; 317 case CDBCMD_READ_CAPACITY_10: 318 hd->dd = DD_OUT; 319 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 320 upiu->lun = lun; 321 break; 322 case CDBCMD_READ_10: 323 hd->dd = DD_OUT; 324 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 325 upiu->lun = lun; 326 upiu->cdb[1] = RW_WITHOUT_CACHE; 327 /* set logical block address */ 328 upiu->cdb[2] = (ulba >> 24) & 0xff; 329 upiu->cdb[3] = (ulba >> 16) & 0xff; 330 upiu->cdb[4] = (ulba >> 8) & 0xff; 331 upiu->cdb[5] = ulba & 0xff; 332 /* set transfer length */ 333 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 334 upiu->cdb[8] = lba_cnt & 0xff; 335 break; 336 case CDBCMD_WRITE_10: 337 hd->dd = DD_IN; 338 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S; 339 upiu->lun = lun; 340 upiu->cdb[1] = RW_WITHOUT_CACHE; 341 /* set logical block address */ 342 upiu->cdb[2] = (ulba >> 24) & 0xff; 343 upiu->cdb[3] = (ulba >> 16) & 0xff; 344 upiu->cdb[4] = (ulba >> 8) & 0xff; 345 upiu->cdb[5] = ulba & 0xff; 346 /* set transfer length */ 347 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 348 upiu->cdb[8] = lba_cnt & 0xff; 349 break; 350 default: 351 assert(0); 352 break; 353 } 354 if (hd->dd == DD_IN) 355 flush_dcache_range(buf, length); 356 else if (hd->dd == DD_OUT) 357 inv_dcache_range(buf, length); 358 if (length) { 359 upiu->exp_data_trans_len = htobe32(length); 360 assert(lba_cnt <= UINT16_MAX); 361 prdt = (prdt_t *)utrd->prdt; 362 363 prdt_size = 0; 364 while (length > 0) { 365 prdt->dba = (unsigned int)(buf & UINT32_MAX); 366 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX); 367 /* prdt->dbc counts from 0 */ 368 if (length > MAX_PRDT_SIZE) { 369 prdt->dbc = MAX_PRDT_SIZE - 1; 370 length = length - MAX_PRDT_SIZE; 371 } else { 372 prdt->dbc = length - 1; 373 length = 0; 374 } 375 buf += MAX_PRDT_SIZE; 376 prdt++; 377 prdt_size += sizeof(prdt_t); 378 } 379 utrd->size_prdt = ALIGN_8(prdt_size); 380 hd->prdtl = utrd->size_prdt >> 2; 381 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2; 382 } 383 384 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 385 return 0; 386 } 387 388 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, 389 uint8_t index, uint8_t sel, 390 uintptr_t buf, size_t length) 391 { 392 utrd_header_t *hd; 393 query_upiu_t *query_upiu; 394 395 396 hd = (utrd_header_t *)utrd->header; 397 query_upiu = (query_upiu_t *)utrd->upiu; 398 399 hd->i = 1; 400 hd->ct = CT_UFS_STORAGE; 401 hd->ocs = OCS_MASK; 402 403 query_upiu->trans_type = QUERY_REQUEST_UPIU; 404 query_upiu->task_tag = utrd->task_tag; 405 query_upiu->ts.desc.opcode = op; 406 query_upiu->ts.desc.idn = idn; 407 query_upiu->ts.desc.index = index; 408 query_upiu->ts.desc.selector = sel; 409 switch (op) { 410 case QUERY_READ_DESC: 411 query_upiu->query_func = QUERY_FUNC_STD_READ; 412 query_upiu->ts.desc.length = htobe16(length); 413 break; 414 case QUERY_WRITE_DESC: 415 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 416 query_upiu->ts.desc.length = htobe16(length); 417 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)), 418 (void *)buf, length); 419 break; 420 case QUERY_READ_ATTR: 421 case QUERY_READ_FLAG: 422 query_upiu->query_func = QUERY_FUNC_STD_READ; 423 break; 424 case QUERY_CLEAR_FLAG: 425 case QUERY_SET_FLAG: 426 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 427 break; 428 case QUERY_WRITE_ATTR: 429 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 430 query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf)); 431 break; 432 default: 433 assert(0); 434 break; 435 } 436 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 437 return 0; 438 } 439 440 static void ufs_prepare_nop_out(utp_utrd_t *utrd) 441 { 442 utrd_header_t *hd; 443 nop_out_upiu_t *nop_out; 444 445 hd = (utrd_header_t *)utrd->header; 446 nop_out = (nop_out_upiu_t *)utrd->upiu; 447 448 hd->i = 1; 449 hd->ct = CT_UFS_STORAGE; 450 hd->ocs = OCS_MASK; 451 452 nop_out->trans_type = 0; 453 nop_out->task_tag = utrd->task_tag; 454 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 455 } 456 457 static void ufs_send_request(int task_tag) 458 { 459 unsigned int data; 460 int slot; 461 462 slot = task_tag - 1; 463 /* clear all interrupts */ 464 mmio_write_32(ufs_params.reg_base + IS, ~0); 465 466 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1); 467 assert(mmio_read_32(ufs_params.reg_base + UTRLRSR) == 1); 468 469 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) | 470 UTRIACR_IATOVAL(0xFF); 471 mmio_write_32(ufs_params.reg_base + UTRIACR, data); 472 /* send request */ 473 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot); 474 } 475 476 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) 477 { 478 utrd_header_t *hd; 479 resp_upiu_t *resp; 480 unsigned int data; 481 int slot; 482 483 hd = (utrd_header_t *)utrd->header; 484 resp = (resp_upiu_t *)utrd->resp_upiu; 485 do { 486 data = mmio_read_32(ufs_params.reg_base + IS); 487 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0) 488 return -EIO; 489 } while ((data & UFS_INT_UTRCS) == 0); 490 slot = utrd->task_tag - 1; 491 492 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 493 assert((data & (1 << slot)) == 0); 494 /* 495 * Invalidate the header after DMA read operation has 496 * completed to avoid cpu referring to the prefetched 497 * data brought in before DMA completion. 498 */ 499 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); 500 assert(hd->ocs == OCS_SUCCESS); 501 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); 502 (void)resp; 503 (void)slot; 504 return 0; 505 } 506 507 static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf, 508 size_t length) 509 { 510 int result; 511 512 get_utrd(utrd); 513 514 result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length); 515 assert(result == 0); 516 ufs_send_request(utrd->task_tag); 517 result = ufs_check_resp(utrd, RESPONSE_UPIU); 518 assert(result == 0); 519 (void)result; 520 } 521 522 #ifdef UFS_RESP_DEBUG 523 static void dump_upiu(utp_utrd_t *utrd) 524 { 525 utrd_header_t *hd; 526 int i; 527 528 hd = (utrd_header_t *)utrd->header; 529 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n", 530 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs, 531 mmio_read_32(ufs_params.reg_base + UTRLDBR)); 532 for (i = 0; i < sizeof(utrd_header_t); i += 4) { 533 INFO("[%lx]:0x%x\n", 534 (uintptr_t)utrd->header + i, 535 *(unsigned int *)((uintptr_t)utrd->header + i)); 536 } 537 538 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) { 539 INFO("cmd[%lx]:0x%x\n", 540 utrd->upiu + i, 541 *(unsigned int *)(utrd->upiu + i)); 542 } 543 for (i = 0; i < sizeof(resp_upiu_t); i += 4) { 544 INFO("resp[%lx]:0x%x\n", 545 utrd->resp_upiu + i, 546 *(unsigned int *)(utrd->resp_upiu + i)); 547 } 548 for (i = 0; i < sizeof(prdt_t); i += 4) { 549 INFO("prdt[%lx]:0x%x\n", 550 utrd->prdt + i, 551 *(unsigned int *)(utrd->prdt + i)); 552 } 553 } 554 #endif 555 556 static void ufs_verify_init(void) 557 { 558 utp_utrd_t utrd; 559 int result; 560 561 get_utrd(&utrd); 562 ufs_prepare_nop_out(&utrd); 563 ufs_send_request(utrd.task_tag); 564 result = ufs_check_resp(&utrd, NOP_IN_UPIU); 565 assert(result == 0); 566 (void)result; 567 } 568 569 static void ufs_verify_ready(void) 570 { 571 utp_utrd_t utrd; 572 ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); 573 } 574 575 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, 576 uintptr_t buf, size_t size) 577 { 578 utp_utrd_t utrd; 579 query_resp_upiu_t *resp; 580 int result; 581 582 switch (op) { 583 case QUERY_READ_FLAG: 584 case QUERY_READ_ATTR: 585 case QUERY_READ_DESC: 586 case QUERY_WRITE_DESC: 587 case QUERY_WRITE_ATTR: 588 assert(((buf & 3) == 0) && (size != 0)); 589 break; 590 default: 591 /* Do nothing in default case */ 592 break; 593 } 594 get_utrd(&utrd); 595 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); 596 ufs_send_request(utrd.task_tag); 597 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU); 598 assert(result == 0); 599 resp = (query_resp_upiu_t *)utrd.resp_upiu; 600 #ifdef UFS_RESP_DEBUG 601 dump_upiu(&utrd); 602 #endif 603 assert(resp->query_resp == QUERY_RESP_SUCCESS); 604 605 switch (op) { 606 case QUERY_READ_FLAG: 607 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value; 608 break; 609 case QUERY_READ_DESC: 610 memcpy((void *)buf, 611 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), 612 size); 613 break; 614 case QUERY_READ_ATTR: 615 *(uint32_t *)buf = htobe32(resp->ts.attr.value); 616 break; 617 default: 618 /* Do nothing in default case */ 619 break; 620 } 621 (void)result; 622 } 623 624 unsigned int ufs_read_attr(int idn) 625 { 626 unsigned int value; 627 628 ufs_query(QUERY_READ_ATTR, idn, 0, 0, 629 (uintptr_t)&value, sizeof(value)); 630 return value; 631 } 632 633 void ufs_write_attr(int idn, unsigned int value) 634 { 635 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0, 636 (uintptr_t)&value, sizeof(value)); 637 } 638 639 unsigned int ufs_read_flag(int idn) 640 { 641 unsigned int value; 642 643 ufs_query(QUERY_READ_FLAG, idn, 0, 0, 644 (uintptr_t)&value, sizeof(value)); 645 return value; 646 } 647 648 void ufs_set_flag(int idn) 649 { 650 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0); 651 } 652 653 void ufs_clear_flag(int idn) 654 { 655 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0); 656 } 657 658 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size) 659 { 660 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size); 661 } 662 663 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size) 664 { 665 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size); 666 } 667 668 static int ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) 669 { 670 utp_utrd_t utrd; 671 resp_upiu_t *resp; 672 sense_data_t *sense; 673 unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; 674 uintptr_t buf; 675 int retries = UFS_READ_CAPACITY_RETRIES; 676 677 assert((ufs_params.reg_base != 0) && 678 (ufs_params.desc_base != 0) && 679 (ufs_params.desc_size >= UFS_DESC_SIZE) && 680 (num != NULL) && (size != NULL)); 681 682 /* align buf address */ 683 buf = (uintptr_t)data; 684 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) & 685 ~(CACHE_WRITEBACK_GRANULE - 1); 686 do { 687 ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, 688 buf, READ_CAPACITY_LENGTH); 689 #ifdef UFS_RESP_DEBUG 690 dump_upiu(&utrd); 691 #endif 692 resp = (resp_upiu_t *)utrd.resp_upiu; 693 sense = &resp->sd.sense; 694 if (!((sense->resp_code == SENSE_DATA_VALID) && 695 (sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && 696 (sense->asc == 0x29) && (sense->ascq == 0))) { 697 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); 698 /* last logical block address */ 699 *num = be32toh(*(unsigned int *)buf); 700 if (*num) 701 *num += 1; 702 /* logical block length in bytes */ 703 *size = be32toh(*(unsigned int *)(buf + 4)); 704 705 return 0; 706 } 707 708 } while (retries-- > 0); 709 710 return -ETIMEDOUT; 711 } 712 713 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) 714 { 715 utp_utrd_t utrd; 716 resp_upiu_t *resp; 717 718 assert((ufs_params.reg_base != 0) && 719 (ufs_params.desc_base != 0) && 720 (ufs_params.desc_size >= UFS_DESC_SIZE)); 721 722 ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); 723 #ifdef UFS_RESP_DEBUG 724 dump_upiu(&utrd); 725 #endif 726 /* 727 * Invalidate prefetched cache contents before cpu 728 * accesses the buf. 729 */ 730 inv_dcache_range(buf, size); 731 resp = (resp_upiu_t *)utrd.resp_upiu; 732 return size - resp->res_trans_cnt; 733 } 734 735 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size) 736 { 737 utp_utrd_t utrd; 738 resp_upiu_t *resp; 739 740 assert((ufs_params.reg_base != 0) && 741 (ufs_params.desc_base != 0) && 742 (ufs_params.desc_size >= UFS_DESC_SIZE)); 743 744 ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); 745 #ifdef UFS_RESP_DEBUG 746 dump_upiu(&utrd); 747 #endif 748 resp = (resp_upiu_t *)utrd.resp_upiu; 749 return size - resp->res_trans_cnt; 750 } 751 752 static int ufs_set_fdevice_init(void) 753 { 754 unsigned int result; 755 int timeout; 756 757 ufs_set_flag(FLAG_DEVICE_INIT); 758 759 timeout = FDEVICEINIT_TIMEOUT_MS; 760 do { 761 result = ufs_read_flag(FLAG_DEVICE_INIT); 762 if (!result) { 763 break; 764 } 765 mdelay(5); 766 timeout -= 5; 767 } while (timeout > 0); 768 769 if (result != 0U) { 770 return -ETIMEDOUT; 771 } 772 773 return 0; 774 } 775 776 static void ufs_enum(void) 777 { 778 unsigned int blk_num, blk_size; 779 int i, result; 780 781 mmio_write_32(ufs_params.reg_base + UTRLBA, 782 ufs_params.desc_base & UINT32_MAX); 783 mmio_write_32(ufs_params.reg_base + UTRLBAU, 784 (ufs_params.desc_base >> 32) & UINT32_MAX); 785 786 ufs_verify_init(); 787 ufs_verify_ready(); 788 789 result = ufs_set_fdevice_init(); 790 assert(result == 0); 791 792 blk_num = 0; 793 blk_size = 0; 794 795 /* dump available LUNs */ 796 for (i = 0; i < UFS_MAX_LUNS; i++) { 797 result = ufs_read_capacity(i, &blk_num, &blk_size); 798 if (result != 0) { 799 WARN("UFS LUN%d dump failed\n", i); 800 } 801 if (blk_num && blk_size) { 802 INFO("UFS LUN%d contains %d blocks with %d-byte size\n", 803 i, blk_num, blk_size); 804 } 805 } 806 807 (void)result; 808 } 809 810 static void ufs_get_device_info(struct ufs_dev_desc *card_data) 811 { 812 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE]; 813 814 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0, 815 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE); 816 817 /* 818 * getting vendor (manufacturerID) and Bank Index in big endian 819 * format 820 */ 821 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) | 822 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1])); 823 } 824 825 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params) 826 { 827 int result; 828 unsigned int data; 829 uic_cmd_t cmd; 830 struct ufs_dev_desc card = {0}; 831 832 assert((params != NULL) && 833 (params->reg_base != 0) && 834 (params->desc_base != 0) && 835 (params->desc_size >= UFS_DESC_SIZE)); 836 837 memcpy(&ufs_params, params, sizeof(ufs_params_t)); 838 839 /* 0 means 1 slot */ 840 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; 841 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) { 842 nutrs = ufs_params.desc_size / UFS_DESC_SIZE; 843 } 844 845 846 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { 847 mmio_write_32(ufs_params.reg_base + UTRLBA, 848 ufs_params.desc_base & UINT32_MAX); 849 mmio_write_32(ufs_params.reg_base + UTRLBAU, 850 (ufs_params.desc_base >> 32) & UINT32_MAX); 851 852 result = ufshc_dme_get(0x1571, 0, &data); 853 assert(result == 0); 854 result = ufshc_dme_get(0x41, 0, &data); 855 assert(result == 0); 856 if (data == 1) { 857 /* prepare to exit hibernate mode */ 858 memset(&cmd, 0, sizeof(uic_cmd_t)); 859 cmd.op = DME_HIBERNATE_EXIT; 860 result = ufshc_send_uic_cmd(ufs_params.reg_base, 861 &cmd); 862 assert(result == 0); 863 data = mmio_read_32(ufs_params.reg_base + UCMDARG2); 864 assert(data == 0); 865 do { 866 data = mmio_read_32(ufs_params.reg_base + IS); 867 } while ((data & UFS_INT_UHXS) == 0); 868 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS); 869 data = mmio_read_32(ufs_params.reg_base + HCS); 870 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL); 871 } 872 result = ufshc_dme_get(0x1568, 0, &data); 873 assert(result == 0); 874 assert((data > 0) && (data <= 3)); 875 } else { 876 assert((ops != NULL) && (ops->phy_init != NULL) && 877 (ops->phy_set_pwr_mode != NULL)); 878 879 result = ufshc_reset(ufs_params.reg_base); 880 assert(result == 0); 881 ops->phy_init(&ufs_params); 882 result = ufshc_link_startup(ufs_params.reg_base); 883 assert(result == 0); 884 885 ufs_enum(); 886 887 ufs_get_device_info(&card); 888 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) { 889 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX; 890 } 891 892 ops->phy_set_pwr_mode(&ufs_params); 893 } 894 895 (void)result; 896 return 0; 897 } 898