1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <endian.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/ufs.h> 19 #include <lib/mmio.h> 20 21 #define CDB_ADDR_MASK 127 22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK) 23 #define ALIGN_8(x) (((x) + 7) & ~7) 24 25 #define UFS_DESC_SIZE 0x400 26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */ 27 28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */ 29 30 static ufs_params_t ufs_params; 31 static int nutrs; /* Number of UTP Transfer Request Slots */ 32 33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd) 34 { 35 unsigned int data; 36 37 if (base == 0 || cmd == NULL) 38 return -EINVAL; 39 40 data = mmio_read_32(base + HCS); 41 if ((data & HCS_UCRDY) == 0) 42 return -EBUSY; 43 mmio_write_32(base + IS, ~0); 44 mmio_write_32(base + UCMDARG1, cmd->arg1); 45 mmio_write_32(base + UCMDARG2, cmd->arg2); 46 mmio_write_32(base + UCMDARG3, cmd->arg3); 47 mmio_write_32(base + UICCMD, cmd->op); 48 49 do { 50 data = mmio_read_32(base + IS); 51 } while ((data & UFS_INT_UCCS) == 0); 52 mmio_write_32(base + IS, UFS_INT_UCCS); 53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK; 54 } 55 56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val) 57 { 58 uintptr_t base; 59 unsigned int data; 60 int result, retries; 61 uic_cmd_t cmd; 62 63 assert(ufs_params.reg_base != 0); 64 65 if (val == NULL) 66 return -EINVAL; 67 68 base = ufs_params.reg_base; 69 for (retries = 0; retries < 100; retries++) { 70 data = mmio_read_32(base + HCS); 71 if ((data & HCS_UCRDY) != 0) 72 break; 73 mdelay(1); 74 } 75 if (retries >= 100) 76 return -EBUSY; 77 78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 79 cmd.arg2 = 0; 80 cmd.arg3 = 0; 81 cmd.op = DME_GET; 82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 83 result = ufshc_send_uic_cmd(base, &cmd); 84 if (result == 0) 85 break; 86 data = mmio_read_32(base + IS); 87 if (data & UFS_INT_UE) 88 return -EINVAL; 89 } 90 if (retries >= UFS_UIC_COMMAND_RETRIES) 91 return -EIO; 92 93 *val = mmio_read_32(base + UCMDARG3); 94 return 0; 95 } 96 97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val) 98 { 99 uintptr_t base; 100 unsigned int data; 101 int result, retries; 102 uic_cmd_t cmd; 103 104 assert((ufs_params.reg_base != 0)); 105 106 base = ufs_params.reg_base; 107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 108 cmd.arg2 = 0; 109 cmd.arg3 = val; 110 cmd.op = DME_SET; 111 112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 113 result = ufshc_send_uic_cmd(base, &cmd); 114 if (result == 0) 115 break; 116 data = mmio_read_32(base + IS); 117 if (data & UFS_INT_UE) 118 return -EINVAL; 119 } 120 if (retries >= UFS_UIC_COMMAND_RETRIES) 121 return -EIO; 122 123 return 0; 124 } 125 126 static int ufshc_hce_enable(uintptr_t base) 127 { 128 unsigned int data; 129 int retries; 130 131 /* Enable Host Controller */ 132 mmio_write_32(base + HCE, HCE_ENABLE); 133 134 /* Wait until basic initialization sequence completed */ 135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) { 136 data = mmio_read_32(base + HCE); 137 if (data & HCE_ENABLE) { 138 break; 139 } 140 udelay(HCE_ENABLE_TIMEOUT_US); 141 } 142 if (retries >= HCE_ENABLE_INNER_RETRIES) { 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int ufshc_hce_disable(uintptr_t base) 150 { 151 unsigned int data; 152 int timeout; 153 154 /* Disable Host Controller */ 155 mmio_write_32(base + HCE, HCE_DISABLE); 156 timeout = HCE_DISABLE_TIMEOUT_US; 157 do { 158 data = mmio_read_32(base + HCE); 159 if ((data & HCE_ENABLE) == HCE_DISABLE) { 160 break; 161 } 162 udelay(1); 163 } while (--timeout > 0); 164 165 if (timeout <= 0) { 166 return -ETIMEDOUT; 167 } 168 169 return 0; 170 } 171 172 173 static int ufshc_reset(uintptr_t base) 174 { 175 unsigned int data; 176 int retries, result; 177 178 /* disable controller if enabled */ 179 if (mmio_read_32(base + HCE) & HCE_ENABLE) { 180 result = ufshc_hce_disable(base); 181 if (result != 0) { 182 return -EIO; 183 } 184 } 185 186 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) { 187 result = ufshc_hce_enable(base); 188 if (result == 0) { 189 break; 190 } 191 } 192 if (retries >= HCE_ENABLE_OUTER_RETRIES) { 193 return -EIO; 194 } 195 196 /* Enable Interrupts */ 197 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES | 198 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES; 199 mmio_write_32(base + IE, data); 200 201 return 0; 202 } 203 204 static int ufshc_dme_link_startup(uintptr_t base) 205 { 206 uic_cmd_t cmd; 207 208 memset(&cmd, 0, sizeof(cmd)); 209 cmd.op = DME_LINKSTARTUP; 210 return ufshc_send_uic_cmd(base, &cmd); 211 } 212 213 static int ufshc_link_startup(uintptr_t base) 214 { 215 int data, result; 216 int retries; 217 218 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) { 219 result = ufshc_dme_link_startup(base); 220 if (result != 0) { 221 /* Reset controller before trying again */ 222 result = ufshc_reset(base); 223 if (result != 0) { 224 return result; 225 } 226 continue; 227 } 228 assert(mmio_read_32(base + HCS) & HCS_DP); 229 data = mmio_read_32(base + IS); 230 if (data & UFS_INT_ULSS) 231 mmio_write_32(base + IS, UFS_INT_ULSS); 232 return 0; 233 } 234 return -EIO; 235 } 236 237 /* Read Door Bell register to check if slot zero is available */ 238 static int is_slot_available(void) 239 { 240 if (mmio_read_32(ufs_params.reg_base + UTRLDBR) & 0x1) { 241 return -EBUSY; 242 } 243 return 0; 244 } 245 246 static void get_utrd(utp_utrd_t *utrd) 247 { 248 uintptr_t base; 249 int result; 250 utrd_header_t *hd; 251 252 assert(utrd != NULL); 253 result = is_slot_available(); 254 assert(result == 0); 255 256 /* clear utrd */ 257 memset((void *)utrd, 0, sizeof(utp_utrd_t)); 258 base = ufs_params.desc_base; 259 /* clear the descriptor */ 260 memset((void *)base, 0, UFS_DESC_SIZE); 261 262 utrd->header = base; 263 utrd->task_tag = 1; /* We always use the first slot */ 264 /* CDB address should be aligned with 128 bytes */ 265 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t)); 266 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t)); 267 utrd->size_upiu = utrd->resp_upiu - utrd->upiu; 268 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t)); 269 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu; 270 271 hd = (utrd_header_t *)utrd->header; 272 hd->ucdba = utrd->upiu & UINT32_MAX; 273 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX; 274 /* Both RUL and RUO is based on DWORD */ 275 hd->rul = utrd->size_resp_upiu >> 2; 276 hd->ruo = utrd->size_upiu >> 2; 277 (void)result; 278 } 279 280 /* 281 * Prepare UTRD, Command UPIU, Response UPIU. 282 */ 283 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, 284 int lba, uintptr_t buf, size_t length) 285 { 286 utrd_header_t *hd; 287 cmd_upiu_t *upiu; 288 prdt_t *prdt; 289 unsigned int ulba; 290 unsigned int lba_cnt; 291 uintptr_t desc_limit; 292 uintptr_t prdt_end; 293 294 hd = (utrd_header_t *)utrd->header; 295 upiu = (cmd_upiu_t *)utrd->upiu; 296 297 hd->i = 1; 298 hd->ct = CT_UFS_STORAGE; 299 hd->ocs = OCS_MASK; 300 301 upiu->trans_type = CMD_UPIU; 302 upiu->task_tag = utrd->task_tag; 303 upiu->cdb[0] = op; 304 ulba = (unsigned int)lba; 305 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT); 306 switch (op) { 307 case CDBCMD_TEST_UNIT_READY: 308 break; 309 case CDBCMD_READ_CAPACITY_10: 310 hd->dd = DD_OUT; 311 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 312 upiu->lun = lun; 313 break; 314 case CDBCMD_READ_10: 315 hd->dd = DD_OUT; 316 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 317 upiu->lun = lun; 318 upiu->cdb[1] = RW_WITHOUT_CACHE; 319 /* set logical block address */ 320 upiu->cdb[2] = (ulba >> 24) & 0xff; 321 upiu->cdb[3] = (ulba >> 16) & 0xff; 322 upiu->cdb[4] = (ulba >> 8) & 0xff; 323 upiu->cdb[5] = ulba & 0xff; 324 /* set transfer length */ 325 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 326 upiu->cdb[8] = lba_cnt & 0xff; 327 break; 328 case CDBCMD_WRITE_10: 329 hd->dd = DD_IN; 330 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S; 331 upiu->lun = lun; 332 upiu->cdb[1] = RW_WITHOUT_CACHE; 333 /* set logical block address */ 334 upiu->cdb[2] = (ulba >> 24) & 0xff; 335 upiu->cdb[3] = (ulba >> 16) & 0xff; 336 upiu->cdb[4] = (ulba >> 8) & 0xff; 337 upiu->cdb[5] = ulba & 0xff; 338 /* set transfer length */ 339 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 340 upiu->cdb[8] = lba_cnt & 0xff; 341 break; 342 default: 343 assert(0); 344 break; 345 } 346 if (hd->dd == DD_IN) { 347 flush_dcache_range(buf, length); 348 } else if (hd->dd == DD_OUT) { 349 inv_dcache_range(buf, length); 350 } 351 352 utrd->prdt_length = 0; 353 if (length) { 354 upiu->exp_data_trans_len = htobe32(length); 355 assert(lba_cnt <= UINT16_MAX); 356 prdt = (prdt_t *)utrd->prdt; 357 358 desc_limit = ufs_params.desc_base + ufs_params.desc_size; 359 while (length > 0) { 360 if ((uintptr_t)prdt + sizeof(prdt_t) > desc_limit) { 361 ERROR("UFS: Exceeded descriptor limit. Image is too large\n"); 362 panic(); 363 } 364 prdt->dba = (unsigned int)(buf & UINT32_MAX); 365 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX); 366 /* prdt->dbc counts from 0 */ 367 if (length > MAX_PRDT_SIZE) { 368 prdt->dbc = MAX_PRDT_SIZE - 1; 369 length = length - MAX_PRDT_SIZE; 370 } else { 371 prdt->dbc = length - 1; 372 length = 0; 373 } 374 buf += MAX_PRDT_SIZE; 375 prdt++; 376 utrd->prdt_length++; 377 } 378 hd->prdtl = utrd->prdt_length; 379 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2; 380 } 381 382 prdt_end = utrd->prdt + utrd->prdt_length * sizeof(prdt_t); 383 flush_dcache_range(utrd->header, prdt_end - utrd->header); 384 return 0; 385 } 386 387 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, 388 uint8_t index, uint8_t sel, 389 uintptr_t buf, size_t length) 390 { 391 utrd_header_t *hd; 392 query_upiu_t *query_upiu; 393 394 395 hd = (utrd_header_t *)utrd->header; 396 query_upiu = (query_upiu_t *)utrd->upiu; 397 398 hd->i = 1; 399 hd->ct = CT_UFS_STORAGE; 400 hd->ocs = OCS_MASK; 401 402 query_upiu->trans_type = QUERY_REQUEST_UPIU; 403 query_upiu->task_tag = utrd->task_tag; 404 query_upiu->ts.desc.opcode = op; 405 query_upiu->ts.desc.idn = idn; 406 query_upiu->ts.desc.index = index; 407 query_upiu->ts.desc.selector = sel; 408 switch (op) { 409 case QUERY_READ_DESC: 410 query_upiu->query_func = QUERY_FUNC_STD_READ; 411 query_upiu->ts.desc.length = htobe16(length); 412 break; 413 case QUERY_WRITE_DESC: 414 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 415 query_upiu->ts.desc.length = htobe16(length); 416 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)), 417 (void *)buf, length); 418 break; 419 case QUERY_READ_ATTR: 420 case QUERY_READ_FLAG: 421 query_upiu->query_func = QUERY_FUNC_STD_READ; 422 break; 423 case QUERY_CLEAR_FLAG: 424 case QUERY_SET_FLAG: 425 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 426 break; 427 case QUERY_WRITE_ATTR: 428 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 429 query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf)); 430 break; 431 default: 432 assert(0); 433 break; 434 } 435 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 436 return 0; 437 } 438 439 static void ufs_prepare_nop_out(utp_utrd_t *utrd) 440 { 441 utrd_header_t *hd; 442 nop_out_upiu_t *nop_out; 443 444 hd = (utrd_header_t *)utrd->header; 445 nop_out = (nop_out_upiu_t *)utrd->upiu; 446 447 hd->i = 1; 448 hd->ct = CT_UFS_STORAGE; 449 hd->ocs = OCS_MASK; 450 451 nop_out->trans_type = 0; 452 nop_out->task_tag = utrd->task_tag; 453 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 454 } 455 456 static void ufs_send_request(int task_tag) 457 { 458 unsigned int data; 459 int slot; 460 461 slot = task_tag - 1; 462 /* clear all interrupts */ 463 mmio_write_32(ufs_params.reg_base + IS, ~0); 464 465 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1); 466 assert(mmio_read_32(ufs_params.reg_base + UTRLRSR) == 1); 467 468 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) | 469 UTRIACR_IATOVAL(0xFF); 470 mmio_write_32(ufs_params.reg_base + UTRIACR, data); 471 /* send request */ 472 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot); 473 } 474 475 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) 476 { 477 utrd_header_t *hd; 478 resp_upiu_t *resp; 479 sense_data_t *sense; 480 unsigned int data; 481 int slot; 482 483 hd = (utrd_header_t *)utrd->header; 484 resp = (resp_upiu_t *)utrd->resp_upiu; 485 do { 486 data = mmio_read_32(ufs_params.reg_base + IS); 487 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0) 488 return -EIO; 489 } while ((data & UFS_INT_UTRCS) == 0); 490 slot = utrd->task_tag - 1; 491 492 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 493 assert((data & (1 << slot)) == 0); 494 /* 495 * Invalidate the header after DMA read operation has 496 * completed to avoid cpu referring to the prefetched 497 * data brought in before DMA completion. 498 */ 499 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); 500 assert(hd->ocs == OCS_SUCCESS); 501 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); 502 503 sense = &resp->sd.sense; 504 if (sense->resp_code == SENSE_DATA_VALID && 505 sense->sense_key == SENSE_KEY_UNIT_ATTENTION && sense->asc == 0x29 && 506 sense->ascq == 0) { 507 WARN("Unit Attention Condition\n"); 508 return -EAGAIN; 509 } 510 511 (void)resp; 512 (void)slot; 513 return 0; 514 } 515 516 static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf, 517 size_t length) 518 { 519 int result, i; 520 521 for (i = 0; i < UFS_CMD_RETRIES; ++i) { 522 get_utrd(utrd); 523 result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length); 524 assert(result == 0); 525 ufs_send_request(utrd->task_tag); 526 result = ufs_check_resp(utrd, RESPONSE_UPIU); 527 if (result == 0 || result == -EIO) { 528 break; 529 } 530 } 531 assert(result == 0); 532 (void)result; 533 } 534 535 #ifdef UFS_RESP_DEBUG 536 static void dump_upiu(utp_utrd_t *utrd) 537 { 538 utrd_header_t *hd; 539 int i; 540 541 hd = (utrd_header_t *)utrd->header; 542 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n", 543 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs, 544 mmio_read_32(ufs_params.reg_base + UTRLDBR)); 545 for (i = 0; i < sizeof(utrd_header_t); i += 4) { 546 INFO("[%lx]:0x%x\n", 547 (uintptr_t)utrd->header + i, 548 *(unsigned int *)((uintptr_t)utrd->header + i)); 549 } 550 551 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) { 552 INFO("cmd[%lx]:0x%x\n", 553 utrd->upiu + i, 554 *(unsigned int *)(utrd->upiu + i)); 555 } 556 for (i = 0; i < sizeof(resp_upiu_t); i += 4) { 557 INFO("resp[%lx]:0x%x\n", 558 utrd->resp_upiu + i, 559 *(unsigned int *)(utrd->resp_upiu + i)); 560 } 561 for (i = 0; i < sizeof(prdt_t); i += 4) { 562 INFO("prdt[%lx]:0x%x\n", 563 utrd->prdt + i, 564 *(unsigned int *)(utrd->prdt + i)); 565 } 566 } 567 #endif 568 569 static void ufs_verify_init(void) 570 { 571 utp_utrd_t utrd; 572 int result; 573 574 get_utrd(&utrd); 575 ufs_prepare_nop_out(&utrd); 576 ufs_send_request(utrd.task_tag); 577 result = ufs_check_resp(&utrd, NOP_IN_UPIU); 578 assert(result == 0); 579 (void)result; 580 } 581 582 static void ufs_verify_ready(void) 583 { 584 utp_utrd_t utrd; 585 ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); 586 } 587 588 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, 589 uintptr_t buf, size_t size) 590 { 591 utp_utrd_t utrd; 592 query_resp_upiu_t *resp; 593 int result; 594 595 switch (op) { 596 case QUERY_READ_FLAG: 597 case QUERY_READ_ATTR: 598 case QUERY_READ_DESC: 599 case QUERY_WRITE_DESC: 600 case QUERY_WRITE_ATTR: 601 assert(((buf & 3) == 0) && (size != 0)); 602 break; 603 default: 604 /* Do nothing in default case */ 605 break; 606 } 607 get_utrd(&utrd); 608 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); 609 ufs_send_request(utrd.task_tag); 610 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU); 611 assert(result == 0); 612 resp = (query_resp_upiu_t *)utrd.resp_upiu; 613 #ifdef UFS_RESP_DEBUG 614 dump_upiu(&utrd); 615 #endif 616 assert(resp->query_resp == QUERY_RESP_SUCCESS); 617 618 switch (op) { 619 case QUERY_READ_FLAG: 620 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value; 621 break; 622 case QUERY_READ_DESC: 623 memcpy((void *)buf, 624 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), 625 size); 626 break; 627 case QUERY_READ_ATTR: 628 *(uint32_t *)buf = htobe32(resp->ts.attr.value); 629 break; 630 default: 631 /* Do nothing in default case */ 632 break; 633 } 634 (void)result; 635 } 636 637 unsigned int ufs_read_attr(int idn) 638 { 639 unsigned int value; 640 641 ufs_query(QUERY_READ_ATTR, idn, 0, 0, 642 (uintptr_t)&value, sizeof(value)); 643 return value; 644 } 645 646 void ufs_write_attr(int idn, unsigned int value) 647 { 648 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0, 649 (uintptr_t)&value, sizeof(value)); 650 } 651 652 unsigned int ufs_read_flag(int idn) 653 { 654 unsigned int value; 655 656 ufs_query(QUERY_READ_FLAG, idn, 0, 0, 657 (uintptr_t)&value, sizeof(value)); 658 return value; 659 } 660 661 void ufs_set_flag(int idn) 662 { 663 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0); 664 } 665 666 void ufs_clear_flag(int idn) 667 { 668 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0); 669 } 670 671 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size) 672 { 673 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size); 674 } 675 676 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size) 677 { 678 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size); 679 } 680 681 static int ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) 682 { 683 utp_utrd_t utrd; 684 resp_upiu_t *resp; 685 sense_data_t *sense; 686 unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; 687 uintptr_t buf; 688 int retries = UFS_READ_CAPACITY_RETRIES; 689 690 assert((ufs_params.reg_base != 0) && 691 (ufs_params.desc_base != 0) && 692 (ufs_params.desc_size >= UFS_DESC_SIZE) && 693 (num != NULL) && (size != NULL)); 694 695 /* align buf address */ 696 buf = (uintptr_t)data; 697 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) & 698 ~(CACHE_WRITEBACK_GRANULE - 1); 699 do { 700 ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, 701 buf, READ_CAPACITY_LENGTH); 702 #ifdef UFS_RESP_DEBUG 703 dump_upiu(&utrd); 704 #endif 705 resp = (resp_upiu_t *)utrd.resp_upiu; 706 sense = &resp->sd.sense; 707 if (!((sense->resp_code == SENSE_DATA_VALID) && 708 (sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && 709 (sense->asc == 0x29) && (sense->ascq == 0))) { 710 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); 711 /* last logical block address */ 712 *num = be32toh(*(unsigned int *)buf); 713 if (*num) 714 *num += 1; 715 /* logical block length in bytes */ 716 *size = be32toh(*(unsigned int *)(buf + 4)); 717 718 return 0; 719 } 720 721 } while (retries-- > 0); 722 723 return -ETIMEDOUT; 724 } 725 726 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) 727 { 728 utp_utrd_t utrd; 729 resp_upiu_t *resp; 730 731 assert((ufs_params.reg_base != 0) && 732 (ufs_params.desc_base != 0) && 733 (ufs_params.desc_size >= UFS_DESC_SIZE)); 734 735 ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); 736 #ifdef UFS_RESP_DEBUG 737 dump_upiu(&utrd); 738 #endif 739 /* 740 * Invalidate prefetched cache contents before cpu 741 * accesses the buf. 742 */ 743 inv_dcache_range(buf, size); 744 resp = (resp_upiu_t *)utrd.resp_upiu; 745 return size - resp->res_trans_cnt; 746 } 747 748 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size) 749 { 750 utp_utrd_t utrd; 751 resp_upiu_t *resp; 752 753 assert((ufs_params.reg_base != 0) && 754 (ufs_params.desc_base != 0) && 755 (ufs_params.desc_size >= UFS_DESC_SIZE)); 756 757 ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); 758 #ifdef UFS_RESP_DEBUG 759 dump_upiu(&utrd); 760 #endif 761 resp = (resp_upiu_t *)utrd.resp_upiu; 762 return size - resp->res_trans_cnt; 763 } 764 765 static int ufs_set_fdevice_init(void) 766 { 767 unsigned int result; 768 int timeout; 769 770 ufs_set_flag(FLAG_DEVICE_INIT); 771 772 timeout = FDEVICEINIT_TIMEOUT_MS; 773 do { 774 result = ufs_read_flag(FLAG_DEVICE_INIT); 775 if (!result) { 776 break; 777 } 778 mdelay(5); 779 timeout -= 5; 780 } while (timeout > 0); 781 782 if (result != 0U) { 783 return -ETIMEDOUT; 784 } 785 786 return 0; 787 } 788 789 static void ufs_enum(void) 790 { 791 unsigned int blk_num, blk_size; 792 int i, result; 793 794 mmio_write_32(ufs_params.reg_base + UTRLBA, 795 ufs_params.desc_base & UINT32_MAX); 796 mmio_write_32(ufs_params.reg_base + UTRLBAU, 797 (ufs_params.desc_base >> 32) & UINT32_MAX); 798 799 ufs_verify_init(); 800 ufs_verify_ready(); 801 802 result = ufs_set_fdevice_init(); 803 assert(result == 0); 804 805 blk_num = 0; 806 blk_size = 0; 807 808 /* dump available LUNs */ 809 for (i = 0; i < UFS_MAX_LUNS; i++) { 810 result = ufs_read_capacity(i, &blk_num, &blk_size); 811 if (result != 0) { 812 WARN("UFS LUN%d dump failed\n", i); 813 } 814 if (blk_num && blk_size) { 815 INFO("UFS LUN%d contains %d blocks with %d-byte size\n", 816 i, blk_num, blk_size); 817 } 818 } 819 820 (void)result; 821 } 822 823 static void ufs_get_device_info(struct ufs_dev_desc *card_data) 824 { 825 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE]; 826 827 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0, 828 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE); 829 830 /* 831 * getting vendor (manufacturerID) and Bank Index in big endian 832 * format 833 */ 834 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) | 835 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1])); 836 } 837 838 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params) 839 { 840 int result; 841 unsigned int data; 842 uic_cmd_t cmd; 843 struct ufs_dev_desc card = {0}; 844 845 assert((params != NULL) && 846 (params->reg_base != 0) && 847 (params->desc_base != 0) && 848 (params->desc_size >= UFS_DESC_SIZE)); 849 850 memcpy(&ufs_params, params, sizeof(ufs_params_t)); 851 852 /* 0 means 1 slot */ 853 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; 854 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) { 855 nutrs = ufs_params.desc_size / UFS_DESC_SIZE; 856 } 857 858 859 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { 860 mmio_write_32(ufs_params.reg_base + UTRLBA, 861 ufs_params.desc_base & UINT32_MAX); 862 mmio_write_32(ufs_params.reg_base + UTRLBAU, 863 (ufs_params.desc_base >> 32) & UINT32_MAX); 864 865 result = ufshc_dme_get(0x1571, 0, &data); 866 assert(result == 0); 867 result = ufshc_dme_get(0x41, 0, &data); 868 assert(result == 0); 869 if (data == 1) { 870 /* prepare to exit hibernate mode */ 871 memset(&cmd, 0, sizeof(uic_cmd_t)); 872 cmd.op = DME_HIBERNATE_EXIT; 873 result = ufshc_send_uic_cmd(ufs_params.reg_base, 874 &cmd); 875 assert(result == 0); 876 data = mmio_read_32(ufs_params.reg_base + UCMDARG2); 877 assert(data == 0); 878 do { 879 data = mmio_read_32(ufs_params.reg_base + IS); 880 } while ((data & UFS_INT_UHXS) == 0); 881 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS); 882 data = mmio_read_32(ufs_params.reg_base + HCS); 883 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL); 884 } 885 result = ufshc_dme_get(0x1568, 0, &data); 886 assert(result == 0); 887 assert((data > 0) && (data <= 3)); 888 } else { 889 assert((ops != NULL) && (ops->phy_init != NULL) && 890 (ops->phy_set_pwr_mode != NULL)); 891 892 result = ufshc_reset(ufs_params.reg_base); 893 assert(result == 0); 894 ops->phy_init(&ufs_params); 895 result = ufshc_link_startup(ufs_params.reg_base); 896 assert(result == 0); 897 898 ufs_enum(); 899 900 ufs_get_device_info(&card); 901 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) { 902 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX; 903 } 904 905 ops->phy_set_pwr_mode(&ufs_params); 906 } 907 908 (void)result; 909 return 0; 910 } 911