1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <endian.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/ufs.h> 19 #include <lib/mmio.h> 20 21 #define CDB_ADDR_MASK 127 22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK) 23 #define ALIGN_8(x) (((x) + 7) & ~7) 24 25 #define UFS_DESC_SIZE 0x400 26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */ 27 28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */ 29 30 static ufs_params_t ufs_params; 31 static int nutrs; /* Number of UTP Transfer Request Slots */ 32 33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd) 34 { 35 unsigned int data; 36 37 if (base == 0 || cmd == NULL) 38 return -EINVAL; 39 40 data = mmio_read_32(base + HCS); 41 if ((data & HCS_UCRDY) == 0) 42 return -EBUSY; 43 mmio_write_32(base + IS, ~0); 44 mmio_write_32(base + UCMDARG1, cmd->arg1); 45 mmio_write_32(base + UCMDARG2, cmd->arg2); 46 mmio_write_32(base + UCMDARG3, cmd->arg3); 47 mmio_write_32(base + UICCMD, cmd->op); 48 49 do { 50 data = mmio_read_32(base + IS); 51 } while ((data & UFS_INT_UCCS) == 0); 52 mmio_write_32(base + IS, UFS_INT_UCCS); 53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK; 54 } 55 56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val) 57 { 58 uintptr_t base; 59 unsigned int data; 60 int result, retries; 61 uic_cmd_t cmd; 62 63 assert(ufs_params.reg_base != 0); 64 65 if (val == NULL) 66 return -EINVAL; 67 68 base = ufs_params.reg_base; 69 for (retries = 0; retries < 100; retries++) { 70 data = mmio_read_32(base + HCS); 71 if ((data & HCS_UCRDY) != 0) 72 break; 73 mdelay(1); 74 } 75 if (retries >= 100) 76 return -EBUSY; 77 78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 79 cmd.arg2 = 0; 80 cmd.arg3 = 0; 81 cmd.op = DME_GET; 82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 83 result = ufshc_send_uic_cmd(base, &cmd); 84 if (result == 0) 85 break; 86 data = mmio_read_32(base + IS); 87 if (data & UFS_INT_UE) 88 return -EINVAL; 89 } 90 if (retries >= UFS_UIC_COMMAND_RETRIES) 91 return -EIO; 92 93 *val = mmio_read_32(base + UCMDARG3); 94 return 0; 95 } 96 97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val) 98 { 99 uintptr_t base; 100 unsigned int data; 101 int result, retries; 102 uic_cmd_t cmd; 103 104 assert((ufs_params.reg_base != 0)); 105 106 base = ufs_params.reg_base; 107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 108 cmd.arg2 = 0; 109 cmd.arg3 = val; 110 cmd.op = DME_SET; 111 112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 113 result = ufshc_send_uic_cmd(base, &cmd); 114 if (result == 0) 115 break; 116 data = mmio_read_32(base + IS); 117 if (data & UFS_INT_UE) 118 return -EINVAL; 119 } 120 if (retries >= UFS_UIC_COMMAND_RETRIES) 121 return -EIO; 122 123 return 0; 124 } 125 126 static int ufshc_hce_enable(uintptr_t base) 127 { 128 unsigned int data; 129 int retries; 130 131 /* Enable Host Controller */ 132 mmio_write_32(base + HCE, HCE_ENABLE); 133 134 /* Wait until basic initialization sequence completed */ 135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) { 136 data = mmio_read_32(base + HCE); 137 if (data & HCE_ENABLE) { 138 break; 139 } 140 udelay(HCE_ENABLE_TIMEOUT_US); 141 } 142 if (retries >= HCE_ENABLE_INNER_RETRIES) { 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int ufshc_reset(uintptr_t base) 150 { 151 unsigned int data; 152 int retries, result; 153 154 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) { 155 result = ufshc_hce_enable(base); 156 if (result == 0) { 157 break; 158 } 159 } 160 if (retries >= HCE_ENABLE_OUTER_RETRIES) { 161 return -EIO; 162 } 163 164 /* Enable Interrupts */ 165 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES | 166 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES; 167 mmio_write_32(base + IE, data); 168 169 return 0; 170 } 171 172 static int ufshc_dme_link_startup(uintptr_t base) 173 { 174 uic_cmd_t cmd; 175 176 memset(&cmd, 0, sizeof(cmd)); 177 cmd.op = DME_LINKSTARTUP; 178 return ufshc_send_uic_cmd(base, &cmd); 179 } 180 181 static int ufshc_link_startup(uintptr_t base) 182 { 183 int data, result; 184 int retries; 185 186 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) { 187 result = ufshc_dme_link_startup(base); 188 if (result != 0) { 189 /* Reset controller before trying again */ 190 result = ufshc_reset(base); 191 if (result != 0) { 192 return result; 193 } 194 continue; 195 } 196 while ((mmio_read_32(base + HCS) & HCS_DP) == 0) 197 ; 198 data = mmio_read_32(base + IS); 199 if (data & UFS_INT_ULSS) 200 mmio_write_32(base + IS, UFS_INT_ULSS); 201 return 0; 202 } 203 return -EIO; 204 } 205 206 /* Check Door Bell register to get an empty slot */ 207 static int get_empty_slot(int *slot) 208 { 209 unsigned int data; 210 int i; 211 212 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 213 for (i = 0; i < nutrs; i++) { 214 if ((data & 1) == 0) 215 break; 216 data = data >> 1; 217 } 218 if (i >= nutrs) 219 return -EBUSY; 220 *slot = i; 221 return 0; 222 } 223 224 static void get_utrd(utp_utrd_t *utrd) 225 { 226 uintptr_t base; 227 int slot = 0, result; 228 utrd_header_t *hd; 229 230 assert(utrd != NULL); 231 result = get_empty_slot(&slot); 232 assert(result == 0); 233 234 /* clear utrd */ 235 memset((void *)utrd, 0, sizeof(utp_utrd_t)); 236 base = ufs_params.desc_base + (slot * UFS_DESC_SIZE); 237 /* clear the descriptor */ 238 memset((void *)base, 0, UFS_DESC_SIZE); 239 240 utrd->header = base; 241 utrd->task_tag = slot + 1; 242 /* CDB address should be aligned with 128 bytes */ 243 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t)); 244 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t)); 245 utrd->size_upiu = utrd->resp_upiu - utrd->upiu; 246 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t)); 247 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu; 248 249 hd = (utrd_header_t *)utrd->header; 250 hd->ucdba = utrd->upiu & UINT32_MAX; 251 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX; 252 /* Both RUL and RUO is based on DWORD */ 253 hd->rul = utrd->size_resp_upiu >> 2; 254 hd->ruo = utrd->size_upiu >> 2; 255 (void)result; 256 } 257 258 /* 259 * Prepare UTRD, Command UPIU, Response UPIU. 260 */ 261 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, 262 int lba, uintptr_t buf, size_t length) 263 { 264 utrd_header_t *hd; 265 cmd_upiu_t *upiu; 266 prdt_t *prdt; 267 unsigned int ulba; 268 unsigned int lba_cnt; 269 int prdt_size; 270 271 272 mmio_write_32(ufs_params.reg_base + UTRLBA, 273 utrd->header & UINT32_MAX); 274 mmio_write_32(ufs_params.reg_base + UTRLBAU, 275 (utrd->upiu >> 32) & UINT32_MAX); 276 277 hd = (utrd_header_t *)utrd->header; 278 upiu = (cmd_upiu_t *)utrd->upiu; 279 280 hd->i = 1; 281 hd->ct = CT_UFS_STORAGE; 282 hd->ocs = OCS_MASK; 283 284 upiu->trans_type = CMD_UPIU; 285 upiu->task_tag = utrd->task_tag; 286 upiu->cdb[0] = op; 287 ulba = (unsigned int)lba; 288 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT); 289 switch (op) { 290 case CDBCMD_TEST_UNIT_READY: 291 break; 292 case CDBCMD_READ_CAPACITY_10: 293 hd->dd = DD_OUT; 294 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 295 upiu->lun = lun; 296 break; 297 case CDBCMD_READ_10: 298 hd->dd = DD_OUT; 299 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 300 upiu->lun = lun; 301 upiu->cdb[1] = RW_WITHOUT_CACHE; 302 /* set logical block address */ 303 upiu->cdb[2] = (ulba >> 24) & 0xff; 304 upiu->cdb[3] = (ulba >> 16) & 0xff; 305 upiu->cdb[4] = (ulba >> 8) & 0xff; 306 upiu->cdb[5] = ulba & 0xff; 307 /* set transfer length */ 308 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 309 upiu->cdb[8] = lba_cnt & 0xff; 310 break; 311 case CDBCMD_WRITE_10: 312 hd->dd = DD_IN; 313 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S; 314 upiu->lun = lun; 315 upiu->cdb[1] = RW_WITHOUT_CACHE; 316 /* set logical block address */ 317 upiu->cdb[2] = (ulba >> 24) & 0xff; 318 upiu->cdb[3] = (ulba >> 16) & 0xff; 319 upiu->cdb[4] = (ulba >> 8) & 0xff; 320 upiu->cdb[5] = ulba & 0xff; 321 /* set transfer length */ 322 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 323 upiu->cdb[8] = lba_cnt & 0xff; 324 break; 325 default: 326 assert(0); 327 break; 328 } 329 if (hd->dd == DD_IN) 330 flush_dcache_range(buf, length); 331 else if (hd->dd == DD_OUT) 332 inv_dcache_range(buf, length); 333 if (length) { 334 upiu->exp_data_trans_len = htobe32(length); 335 assert(lba_cnt <= UINT16_MAX); 336 prdt = (prdt_t *)utrd->prdt; 337 338 prdt_size = 0; 339 while (length > 0) { 340 prdt->dba = (unsigned int)(buf & UINT32_MAX); 341 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX); 342 /* prdt->dbc counts from 0 */ 343 if (length > MAX_PRDT_SIZE) { 344 prdt->dbc = MAX_PRDT_SIZE - 1; 345 length = length - MAX_PRDT_SIZE; 346 } else { 347 prdt->dbc = length - 1; 348 length = 0; 349 } 350 buf += MAX_PRDT_SIZE; 351 prdt++; 352 prdt_size += sizeof(prdt_t); 353 } 354 utrd->size_prdt = ALIGN_8(prdt_size); 355 hd->prdtl = utrd->size_prdt >> 2; 356 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2; 357 } 358 359 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 360 return 0; 361 } 362 363 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, 364 uint8_t index, uint8_t sel, 365 uintptr_t buf, size_t length) 366 { 367 utrd_header_t *hd; 368 query_upiu_t *query_upiu; 369 370 371 hd = (utrd_header_t *)utrd->header; 372 query_upiu = (query_upiu_t *)utrd->upiu; 373 374 mmio_write_32(ufs_params.reg_base + UTRLBA, 375 utrd->header & UINT32_MAX); 376 mmio_write_32(ufs_params.reg_base + UTRLBAU, 377 (utrd->header >> 32) & UINT32_MAX); 378 379 380 hd->i = 1; 381 hd->ct = CT_UFS_STORAGE; 382 hd->ocs = OCS_MASK; 383 384 query_upiu->trans_type = QUERY_REQUEST_UPIU; 385 query_upiu->task_tag = utrd->task_tag; 386 query_upiu->ts.desc.opcode = op; 387 query_upiu->ts.desc.idn = idn; 388 query_upiu->ts.desc.index = index; 389 query_upiu->ts.desc.selector = sel; 390 switch (op) { 391 case QUERY_READ_DESC: 392 query_upiu->query_func = QUERY_FUNC_STD_READ; 393 query_upiu->ts.desc.length = htobe16(length); 394 break; 395 case QUERY_WRITE_DESC: 396 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 397 query_upiu->ts.desc.length = htobe16(length); 398 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)), 399 (void *)buf, length); 400 break; 401 case QUERY_READ_ATTR: 402 case QUERY_READ_FLAG: 403 query_upiu->query_func = QUERY_FUNC_STD_READ; 404 break; 405 case QUERY_CLEAR_FLAG: 406 case QUERY_SET_FLAG: 407 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 408 break; 409 case QUERY_WRITE_ATTR: 410 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 411 memcpy((void *)&query_upiu->ts.attr.value, (void *)buf, length); 412 break; 413 default: 414 assert(0); 415 break; 416 } 417 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 418 return 0; 419 } 420 421 static void ufs_prepare_nop_out(utp_utrd_t *utrd) 422 { 423 utrd_header_t *hd; 424 nop_out_upiu_t *nop_out; 425 426 mmio_write_32(ufs_params.reg_base + UTRLBA, 427 utrd->header & UINT32_MAX); 428 mmio_write_32(ufs_params.reg_base + UTRLBAU, 429 (utrd->header >> 32) & UINT32_MAX); 430 431 hd = (utrd_header_t *)utrd->header; 432 nop_out = (nop_out_upiu_t *)utrd->upiu; 433 434 hd->i = 1; 435 hd->ct = CT_UFS_STORAGE; 436 hd->ocs = OCS_MASK; 437 438 nop_out->trans_type = 0; 439 nop_out->task_tag = utrd->task_tag; 440 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 441 } 442 443 static void ufs_send_request(int task_tag) 444 { 445 unsigned int data; 446 int slot; 447 448 slot = task_tag - 1; 449 /* clear all interrupts */ 450 mmio_write_32(ufs_params.reg_base + IS, ~0); 451 452 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1); 453 do { 454 data = mmio_read_32(ufs_params.reg_base + UTRLRSR); 455 } while (data == 0); 456 457 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) | 458 UTRIACR_IATOVAL(0xFF); 459 mmio_write_32(ufs_params.reg_base + UTRIACR, data); 460 /* send request */ 461 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot); 462 } 463 464 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) 465 { 466 utrd_header_t *hd; 467 resp_upiu_t *resp; 468 unsigned int data; 469 int slot; 470 471 hd = (utrd_header_t *)utrd->header; 472 resp = (resp_upiu_t *)utrd->resp_upiu; 473 do { 474 data = mmio_read_32(ufs_params.reg_base + IS); 475 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0) 476 return -EIO; 477 } while ((data & UFS_INT_UTRCS) == 0); 478 slot = utrd->task_tag - 1; 479 480 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 481 assert((data & (1 << slot)) == 0); 482 /* 483 * Invalidate the header after DMA read operation has 484 * completed to avoid cpu referring to the prefetched 485 * data brought in before DMA completion. 486 */ 487 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); 488 assert(hd->ocs == OCS_SUCCESS); 489 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); 490 (void)resp; 491 (void)slot; 492 return 0; 493 } 494 495 #ifdef UFS_RESP_DEBUG 496 static void dump_upiu(utp_utrd_t *utrd) 497 { 498 utrd_header_t *hd; 499 int i; 500 501 hd = (utrd_header_t *)utrd->header; 502 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n", 503 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs, 504 mmio_read_32(ufs_params.reg_base + UTRLDBR)); 505 for (i = 0; i < sizeof(utrd_header_t); i += 4) { 506 INFO("[%lx]:0x%x\n", 507 (uintptr_t)utrd->header + i, 508 *(unsigned int *)((uintptr_t)utrd->header + i)); 509 } 510 511 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) { 512 INFO("cmd[%lx]:0x%x\n", 513 utrd->upiu + i, 514 *(unsigned int *)(utrd->upiu + i)); 515 } 516 for (i = 0; i < sizeof(resp_upiu_t); i += 4) { 517 INFO("resp[%lx]:0x%x\n", 518 utrd->resp_upiu + i, 519 *(unsigned int *)(utrd->resp_upiu + i)); 520 } 521 for (i = 0; i < sizeof(prdt_t); i += 4) { 522 INFO("prdt[%lx]:0x%x\n", 523 utrd->prdt + i, 524 *(unsigned int *)(utrd->prdt + i)); 525 } 526 } 527 #endif 528 529 static void ufs_verify_init(void) 530 { 531 utp_utrd_t utrd; 532 int result; 533 534 get_utrd(&utrd); 535 ufs_prepare_nop_out(&utrd); 536 ufs_send_request(utrd.task_tag); 537 result = ufs_check_resp(&utrd, NOP_IN_UPIU); 538 assert(result == 0); 539 (void)result; 540 } 541 542 static void ufs_verify_ready(void) 543 { 544 utp_utrd_t utrd; 545 int result; 546 547 get_utrd(&utrd); 548 ufs_prepare_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); 549 ufs_send_request(utrd.task_tag); 550 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 551 assert(result == 0); 552 (void)result; 553 } 554 555 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, 556 uintptr_t buf, size_t size) 557 { 558 utp_utrd_t utrd; 559 query_resp_upiu_t *resp; 560 int result; 561 562 switch (op) { 563 case QUERY_READ_FLAG: 564 case QUERY_READ_ATTR: 565 case QUERY_READ_DESC: 566 case QUERY_WRITE_DESC: 567 case QUERY_WRITE_ATTR: 568 assert(((buf & 3) == 0) && (size != 0)); 569 break; 570 default: 571 /* Do nothing in default case */ 572 break; 573 } 574 get_utrd(&utrd); 575 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); 576 ufs_send_request(utrd.task_tag); 577 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU); 578 assert(result == 0); 579 resp = (query_resp_upiu_t *)utrd.resp_upiu; 580 #ifdef UFS_RESP_DEBUG 581 dump_upiu(&utrd); 582 #endif 583 assert(resp->query_resp == QUERY_RESP_SUCCESS); 584 585 switch (op) { 586 case QUERY_READ_FLAG: 587 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value; 588 break; 589 case QUERY_READ_ATTR: 590 case QUERY_READ_DESC: 591 memcpy((void *)buf, 592 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), 593 size); 594 break; 595 default: 596 /* Do nothing in default case */ 597 break; 598 } 599 (void)result; 600 } 601 602 unsigned int ufs_read_attr(int idn) 603 { 604 unsigned int value; 605 606 ufs_query(QUERY_READ_ATTR, idn, 0, 0, 607 (uintptr_t)&value, sizeof(value)); 608 return value; 609 } 610 611 void ufs_write_attr(int idn, unsigned int value) 612 { 613 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0, 614 (uintptr_t)&value, sizeof(value)); 615 } 616 617 unsigned int ufs_read_flag(int idn) 618 { 619 unsigned int value; 620 621 ufs_query(QUERY_READ_FLAG, idn, 0, 0, 622 (uintptr_t)&value, sizeof(value)); 623 return value; 624 } 625 626 void ufs_set_flag(int idn) 627 { 628 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0); 629 } 630 631 void ufs_clear_flag(int idn) 632 { 633 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0); 634 } 635 636 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size) 637 { 638 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size); 639 } 640 641 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size) 642 { 643 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size); 644 } 645 646 static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) 647 { 648 utp_utrd_t utrd; 649 resp_upiu_t *resp; 650 sense_data_t *sense; 651 unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; 652 uintptr_t buf; 653 int result; 654 int retry; 655 656 assert((ufs_params.reg_base != 0) && 657 (ufs_params.desc_base != 0) && 658 (ufs_params.desc_size >= UFS_DESC_SIZE) && 659 (num != NULL) && (size != NULL)); 660 661 /* align buf address */ 662 buf = (uintptr_t)data; 663 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) & 664 ~(CACHE_WRITEBACK_GRANULE - 1); 665 do { 666 get_utrd(&utrd); 667 ufs_prepare_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, 668 buf, READ_CAPACITY_LENGTH); 669 ufs_send_request(utrd.task_tag); 670 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 671 assert(result == 0); 672 #ifdef UFS_RESP_DEBUG 673 dump_upiu(&utrd); 674 #endif 675 resp = (resp_upiu_t *)utrd.resp_upiu; 676 retry = 0; 677 sense = &resp->sd.sense; 678 if (sense->resp_code == SENSE_DATA_VALID) { 679 if ((sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && 680 (sense->asc == 0x29) && (sense->ascq == 0)) { 681 retry = 1; 682 } 683 } 684 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); 685 /* last logical block address */ 686 *num = be32toh(*(unsigned int *)buf); 687 if (*num) 688 *num += 1; 689 /* logical block length in bytes */ 690 *size = be32toh(*(unsigned int *)(buf + 4)); 691 } while (retry); 692 (void)result; 693 } 694 695 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) 696 { 697 utp_utrd_t utrd; 698 resp_upiu_t *resp; 699 int result; 700 701 assert((ufs_params.reg_base != 0) && 702 (ufs_params.desc_base != 0) && 703 (ufs_params.desc_size >= UFS_DESC_SIZE)); 704 705 get_utrd(&utrd); 706 ufs_prepare_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); 707 ufs_send_request(utrd.task_tag); 708 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 709 assert(result == 0); 710 #ifdef UFS_RESP_DEBUG 711 dump_upiu(&utrd); 712 #endif 713 /* 714 * Invalidate prefetched cache contents before cpu 715 * accesses the buf. 716 */ 717 inv_dcache_range(buf, size); 718 resp = (resp_upiu_t *)utrd.resp_upiu; 719 (void)result; 720 return size - resp->res_trans_cnt; 721 } 722 723 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size) 724 { 725 utp_utrd_t utrd; 726 resp_upiu_t *resp; 727 int result; 728 729 assert((ufs_params.reg_base != 0) && 730 (ufs_params.desc_base != 0) && 731 (ufs_params.desc_size >= UFS_DESC_SIZE)); 732 733 get_utrd(&utrd); 734 ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); 735 ufs_send_request(utrd.task_tag); 736 result = ufs_check_resp(&utrd, RESPONSE_UPIU); 737 assert(result == 0); 738 #ifdef UFS_RESP_DEBUG 739 dump_upiu(&utrd); 740 #endif 741 resp = (resp_upiu_t *)utrd.resp_upiu; 742 (void)result; 743 return size - resp->res_trans_cnt; 744 } 745 746 static void ufs_enum(void) 747 { 748 unsigned int blk_num, blk_size; 749 int i; 750 751 /* 0 means 1 slot */ 752 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; 753 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) 754 nutrs = ufs_params.desc_size / UFS_DESC_SIZE; 755 756 ufs_verify_init(); 757 ufs_verify_ready(); 758 759 ufs_set_flag(FLAG_DEVICE_INIT); 760 mdelay(200); 761 /* dump available LUNs */ 762 for (i = 0; i < UFS_MAX_LUNS; i++) { 763 ufs_read_capacity(i, &blk_num, &blk_size); 764 if (blk_num && blk_size) { 765 INFO("UFS LUN%d contains %d blocks with %d-byte size\n", 766 i, blk_num, blk_size); 767 } 768 } 769 } 770 771 static void ufs_get_device_info(struct ufs_dev_desc *card_data) 772 { 773 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE]; 774 775 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0, 776 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE); 777 778 /* 779 * getting vendor (manufacturerID) and Bank Index in big endian 780 * format 781 */ 782 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) | 783 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1])); 784 } 785 786 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params) 787 { 788 int result; 789 unsigned int data; 790 uic_cmd_t cmd; 791 struct ufs_dev_desc card = {0}; 792 793 assert((params != NULL) && 794 (params->reg_base != 0) && 795 (params->desc_base != 0) && 796 (params->desc_size >= UFS_DESC_SIZE)); 797 798 memcpy(&ufs_params, params, sizeof(ufs_params_t)); 799 800 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { 801 result = ufshc_dme_get(0x1571, 0, &data); 802 assert(result == 0); 803 result = ufshc_dme_get(0x41, 0, &data); 804 assert(result == 0); 805 if (data == 1) { 806 /* prepare to exit hibernate mode */ 807 memset(&cmd, 0, sizeof(uic_cmd_t)); 808 cmd.op = DME_HIBERNATE_EXIT; 809 result = ufshc_send_uic_cmd(ufs_params.reg_base, 810 &cmd); 811 assert(result == 0); 812 data = mmio_read_32(ufs_params.reg_base + UCMDARG2); 813 assert(data == 0); 814 do { 815 data = mmio_read_32(ufs_params.reg_base + IS); 816 } while ((data & UFS_INT_UHXS) == 0); 817 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS); 818 data = mmio_read_32(ufs_params.reg_base + HCS); 819 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL); 820 } 821 result = ufshc_dme_get(0x1568, 0, &data); 822 assert(result == 0); 823 assert((data > 0) && (data <= 3)); 824 } else { 825 assert((ops != NULL) && (ops->phy_init != NULL) && 826 (ops->phy_set_pwr_mode != NULL)); 827 828 result = ufshc_reset(ufs_params.reg_base); 829 assert(result == 0); 830 ops->phy_init(&ufs_params); 831 result = ufshc_link_startup(ufs_params.reg_base); 832 assert(result == 0); 833 834 ufs_enum(); 835 836 ufs_get_device_info(&card); 837 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) { 838 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX; 839 } 840 841 ops->phy_set_pwr_mode(&ufs_params); 842 } 843 844 (void)result; 845 return 0; 846 } 847