1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <endian.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/ufs.h> 19 #include <lib/mmio.h> 20 21 #define CDB_ADDR_MASK 127 22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK) 23 #define ALIGN_8(x) (((x) + 7) & ~7) 24 25 #define UFS_DESC_SIZE 0x400 26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */ 27 28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */ 29 30 static ufs_params_t ufs_params; 31 static int nutrs; /* Number of UTP Transfer Request Slots */ 32 33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd) 34 { 35 unsigned int data; 36 37 if (base == 0 || cmd == NULL) 38 return -EINVAL; 39 40 data = mmio_read_32(base + HCS); 41 if ((data & HCS_UCRDY) == 0) 42 return -EBUSY; 43 mmio_write_32(base + IS, ~0); 44 mmio_write_32(base + UCMDARG1, cmd->arg1); 45 mmio_write_32(base + UCMDARG2, cmd->arg2); 46 mmio_write_32(base + UCMDARG3, cmd->arg3); 47 mmio_write_32(base + UICCMD, cmd->op); 48 49 do { 50 data = mmio_read_32(base + IS); 51 } while ((data & UFS_INT_UCCS) == 0); 52 mmio_write_32(base + IS, UFS_INT_UCCS); 53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK; 54 } 55 56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val) 57 { 58 uintptr_t base; 59 unsigned int data; 60 int result, retries; 61 uic_cmd_t cmd; 62 63 assert(ufs_params.reg_base != 0); 64 65 if (val == NULL) 66 return -EINVAL; 67 68 base = ufs_params.reg_base; 69 for (retries = 0; retries < 100; retries++) { 70 data = mmio_read_32(base + HCS); 71 if ((data & HCS_UCRDY) != 0) 72 break; 73 mdelay(1); 74 } 75 if (retries >= 100) 76 return -EBUSY; 77 78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 79 cmd.arg2 = 0; 80 cmd.arg3 = 0; 81 cmd.op = DME_GET; 82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 83 result = ufshc_send_uic_cmd(base, &cmd); 84 if (result == 0) 85 break; 86 data = mmio_read_32(base + IS); 87 if (data & UFS_INT_UE) 88 return -EINVAL; 89 } 90 if (retries >= UFS_UIC_COMMAND_RETRIES) 91 return -EIO; 92 93 *val = mmio_read_32(base + UCMDARG3); 94 return 0; 95 } 96 97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val) 98 { 99 uintptr_t base; 100 unsigned int data; 101 int result, retries; 102 uic_cmd_t cmd; 103 104 assert((ufs_params.reg_base != 0)); 105 106 base = ufs_params.reg_base; 107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx); 108 cmd.arg2 = 0; 109 cmd.arg3 = val; 110 cmd.op = DME_SET; 111 112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) { 113 result = ufshc_send_uic_cmd(base, &cmd); 114 if (result == 0) 115 break; 116 data = mmio_read_32(base + IS); 117 if (data & UFS_INT_UE) 118 return -EINVAL; 119 } 120 if (retries >= UFS_UIC_COMMAND_RETRIES) 121 return -EIO; 122 123 return 0; 124 } 125 126 static int ufshc_hce_enable(uintptr_t base) 127 { 128 unsigned int data; 129 int retries; 130 131 /* Enable Host Controller */ 132 mmio_write_32(base + HCE, HCE_ENABLE); 133 134 /* Wait until basic initialization sequence completed */ 135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) { 136 data = mmio_read_32(base + HCE); 137 if (data & HCE_ENABLE) { 138 break; 139 } 140 udelay(HCE_ENABLE_TIMEOUT_US); 141 } 142 if (retries >= HCE_ENABLE_INNER_RETRIES) { 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int ufshc_hce_disable(uintptr_t base) 150 { 151 unsigned int data; 152 int timeout; 153 154 /* Disable Host Controller */ 155 mmio_write_32(base + HCE, HCE_DISABLE); 156 timeout = HCE_DISABLE_TIMEOUT_US; 157 do { 158 data = mmio_read_32(base + HCE); 159 if ((data & HCE_ENABLE) == HCE_DISABLE) { 160 break; 161 } 162 udelay(1); 163 } while (--timeout > 0); 164 165 if (timeout <= 0) { 166 return -ETIMEDOUT; 167 } 168 169 return 0; 170 } 171 172 173 static int ufshc_reset(uintptr_t base) 174 { 175 unsigned int data; 176 int retries, result; 177 178 /* disable controller if enabled */ 179 if (mmio_read_32(base + HCE) & HCE_ENABLE) { 180 result = ufshc_hce_disable(base); 181 if (result != 0) { 182 return -EIO; 183 } 184 } 185 186 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) { 187 result = ufshc_hce_enable(base); 188 if (result == 0) { 189 break; 190 } 191 } 192 if (retries >= HCE_ENABLE_OUTER_RETRIES) { 193 return -EIO; 194 } 195 196 /* Enable Interrupts */ 197 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES | 198 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES; 199 mmio_write_32(base + IE, data); 200 201 return 0; 202 } 203 204 static int ufshc_dme_link_startup(uintptr_t base) 205 { 206 uic_cmd_t cmd; 207 208 memset(&cmd, 0, sizeof(cmd)); 209 cmd.op = DME_LINKSTARTUP; 210 return ufshc_send_uic_cmd(base, &cmd); 211 } 212 213 static int ufshc_link_startup(uintptr_t base) 214 { 215 int data, result; 216 int retries; 217 218 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) { 219 result = ufshc_dme_link_startup(base); 220 if (result != 0) { 221 /* Reset controller before trying again */ 222 result = ufshc_reset(base); 223 if (result != 0) { 224 return result; 225 } 226 continue; 227 } 228 while ((mmio_read_32(base + HCS) & HCS_DP) == 0) 229 ; 230 data = mmio_read_32(base + IS); 231 if (data & UFS_INT_ULSS) 232 mmio_write_32(base + IS, UFS_INT_ULSS); 233 return 0; 234 } 235 return -EIO; 236 } 237 238 /* Check Door Bell register to get an empty slot */ 239 static int get_empty_slot(int *slot) 240 { 241 unsigned int data; 242 int i; 243 244 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 245 for (i = 0; i < nutrs; i++) { 246 if ((data & 1) == 0) 247 break; 248 data = data >> 1; 249 } 250 if (i >= nutrs) 251 return -EBUSY; 252 *slot = i; 253 return 0; 254 } 255 256 static void get_utrd(utp_utrd_t *utrd) 257 { 258 uintptr_t base; 259 int slot = 0, result; 260 utrd_header_t *hd; 261 262 assert(utrd != NULL); 263 result = get_empty_slot(&slot); 264 assert(result == 0); 265 266 /* clear utrd */ 267 memset((void *)utrd, 0, sizeof(utp_utrd_t)); 268 base = ufs_params.desc_base + (slot * UFS_DESC_SIZE); 269 /* clear the descriptor */ 270 memset((void *)base, 0, UFS_DESC_SIZE); 271 272 utrd->header = base; 273 utrd->task_tag = slot + 1; 274 /* CDB address should be aligned with 128 bytes */ 275 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t)); 276 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t)); 277 utrd->size_upiu = utrd->resp_upiu - utrd->upiu; 278 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t)); 279 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu; 280 281 hd = (utrd_header_t *)utrd->header; 282 hd->ucdba = utrd->upiu & UINT32_MAX; 283 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX; 284 /* Both RUL and RUO is based on DWORD */ 285 hd->rul = utrd->size_resp_upiu >> 2; 286 hd->ruo = utrd->size_upiu >> 2; 287 (void)result; 288 } 289 290 /* 291 * Prepare UTRD, Command UPIU, Response UPIU. 292 */ 293 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, 294 int lba, uintptr_t buf, size_t length) 295 { 296 utrd_header_t *hd; 297 cmd_upiu_t *upiu; 298 prdt_t *prdt; 299 unsigned int ulba; 300 unsigned int lba_cnt; 301 int prdt_size; 302 303 304 mmio_write_32(ufs_params.reg_base + UTRLBA, 305 utrd->header & UINT32_MAX); 306 mmio_write_32(ufs_params.reg_base + UTRLBAU, 307 (utrd->upiu >> 32) & UINT32_MAX); 308 309 hd = (utrd_header_t *)utrd->header; 310 upiu = (cmd_upiu_t *)utrd->upiu; 311 312 hd->i = 1; 313 hd->ct = CT_UFS_STORAGE; 314 hd->ocs = OCS_MASK; 315 316 upiu->trans_type = CMD_UPIU; 317 upiu->task_tag = utrd->task_tag; 318 upiu->cdb[0] = op; 319 ulba = (unsigned int)lba; 320 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT); 321 switch (op) { 322 case CDBCMD_TEST_UNIT_READY: 323 break; 324 case CDBCMD_READ_CAPACITY_10: 325 hd->dd = DD_OUT; 326 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 327 upiu->lun = lun; 328 break; 329 case CDBCMD_READ_10: 330 hd->dd = DD_OUT; 331 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S; 332 upiu->lun = lun; 333 upiu->cdb[1] = RW_WITHOUT_CACHE; 334 /* set logical block address */ 335 upiu->cdb[2] = (ulba >> 24) & 0xff; 336 upiu->cdb[3] = (ulba >> 16) & 0xff; 337 upiu->cdb[4] = (ulba >> 8) & 0xff; 338 upiu->cdb[5] = ulba & 0xff; 339 /* set transfer length */ 340 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 341 upiu->cdb[8] = lba_cnt & 0xff; 342 break; 343 case CDBCMD_WRITE_10: 344 hd->dd = DD_IN; 345 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S; 346 upiu->lun = lun; 347 upiu->cdb[1] = RW_WITHOUT_CACHE; 348 /* set logical block address */ 349 upiu->cdb[2] = (ulba >> 24) & 0xff; 350 upiu->cdb[3] = (ulba >> 16) & 0xff; 351 upiu->cdb[4] = (ulba >> 8) & 0xff; 352 upiu->cdb[5] = ulba & 0xff; 353 /* set transfer length */ 354 upiu->cdb[7] = (lba_cnt >> 8) & 0xff; 355 upiu->cdb[8] = lba_cnt & 0xff; 356 break; 357 default: 358 assert(0); 359 break; 360 } 361 if (hd->dd == DD_IN) 362 flush_dcache_range(buf, length); 363 else if (hd->dd == DD_OUT) 364 inv_dcache_range(buf, length); 365 if (length) { 366 upiu->exp_data_trans_len = htobe32(length); 367 assert(lba_cnt <= UINT16_MAX); 368 prdt = (prdt_t *)utrd->prdt; 369 370 prdt_size = 0; 371 while (length > 0) { 372 prdt->dba = (unsigned int)(buf & UINT32_MAX); 373 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX); 374 /* prdt->dbc counts from 0 */ 375 if (length > MAX_PRDT_SIZE) { 376 prdt->dbc = MAX_PRDT_SIZE - 1; 377 length = length - MAX_PRDT_SIZE; 378 } else { 379 prdt->dbc = length - 1; 380 length = 0; 381 } 382 buf += MAX_PRDT_SIZE; 383 prdt++; 384 prdt_size += sizeof(prdt_t); 385 } 386 utrd->size_prdt = ALIGN_8(prdt_size); 387 hd->prdtl = utrd->size_prdt >> 2; 388 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2; 389 } 390 391 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 392 return 0; 393 } 394 395 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, 396 uint8_t index, uint8_t sel, 397 uintptr_t buf, size_t length) 398 { 399 utrd_header_t *hd; 400 query_upiu_t *query_upiu; 401 402 403 hd = (utrd_header_t *)utrd->header; 404 query_upiu = (query_upiu_t *)utrd->upiu; 405 406 mmio_write_32(ufs_params.reg_base + UTRLBA, 407 utrd->header & UINT32_MAX); 408 mmio_write_32(ufs_params.reg_base + UTRLBAU, 409 (utrd->header >> 32) & UINT32_MAX); 410 411 412 hd->i = 1; 413 hd->ct = CT_UFS_STORAGE; 414 hd->ocs = OCS_MASK; 415 416 query_upiu->trans_type = QUERY_REQUEST_UPIU; 417 query_upiu->task_tag = utrd->task_tag; 418 query_upiu->ts.desc.opcode = op; 419 query_upiu->ts.desc.idn = idn; 420 query_upiu->ts.desc.index = index; 421 query_upiu->ts.desc.selector = sel; 422 switch (op) { 423 case QUERY_READ_DESC: 424 query_upiu->query_func = QUERY_FUNC_STD_READ; 425 query_upiu->ts.desc.length = htobe16(length); 426 break; 427 case QUERY_WRITE_DESC: 428 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 429 query_upiu->ts.desc.length = htobe16(length); 430 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)), 431 (void *)buf, length); 432 break; 433 case QUERY_READ_ATTR: 434 case QUERY_READ_FLAG: 435 query_upiu->query_func = QUERY_FUNC_STD_READ; 436 break; 437 case QUERY_CLEAR_FLAG: 438 case QUERY_SET_FLAG: 439 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 440 break; 441 case QUERY_WRITE_ATTR: 442 query_upiu->query_func = QUERY_FUNC_STD_WRITE; 443 query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf)); 444 break; 445 default: 446 assert(0); 447 break; 448 } 449 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 450 return 0; 451 } 452 453 static void ufs_prepare_nop_out(utp_utrd_t *utrd) 454 { 455 utrd_header_t *hd; 456 nop_out_upiu_t *nop_out; 457 458 mmio_write_32(ufs_params.reg_base + UTRLBA, 459 utrd->header & UINT32_MAX); 460 mmio_write_32(ufs_params.reg_base + UTRLBAU, 461 (utrd->header >> 32) & UINT32_MAX); 462 463 hd = (utrd_header_t *)utrd->header; 464 nop_out = (nop_out_upiu_t *)utrd->upiu; 465 466 hd->i = 1; 467 hd->ct = CT_UFS_STORAGE; 468 hd->ocs = OCS_MASK; 469 470 nop_out->trans_type = 0; 471 nop_out->task_tag = utrd->task_tag; 472 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); 473 } 474 475 static void ufs_send_request(int task_tag) 476 { 477 unsigned int data; 478 int slot; 479 480 slot = task_tag - 1; 481 /* clear all interrupts */ 482 mmio_write_32(ufs_params.reg_base + IS, ~0); 483 484 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1); 485 do { 486 data = mmio_read_32(ufs_params.reg_base + UTRLRSR); 487 } while (data == 0); 488 489 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) | 490 UTRIACR_IATOVAL(0xFF); 491 mmio_write_32(ufs_params.reg_base + UTRIACR, data); 492 /* send request */ 493 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot); 494 } 495 496 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) 497 { 498 utrd_header_t *hd; 499 resp_upiu_t *resp; 500 unsigned int data; 501 int slot; 502 503 hd = (utrd_header_t *)utrd->header; 504 resp = (resp_upiu_t *)utrd->resp_upiu; 505 do { 506 data = mmio_read_32(ufs_params.reg_base + IS); 507 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0) 508 return -EIO; 509 } while ((data & UFS_INT_UTRCS) == 0); 510 slot = utrd->task_tag - 1; 511 512 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); 513 assert((data & (1 << slot)) == 0); 514 /* 515 * Invalidate the header after DMA read operation has 516 * completed to avoid cpu referring to the prefetched 517 * data brought in before DMA completion. 518 */ 519 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); 520 assert(hd->ocs == OCS_SUCCESS); 521 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); 522 (void)resp; 523 (void)slot; 524 return 0; 525 } 526 527 static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf, 528 size_t length) 529 { 530 int result; 531 532 get_utrd(utrd); 533 534 result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length); 535 assert(result == 0); 536 ufs_send_request(utrd->task_tag); 537 result = ufs_check_resp(utrd, RESPONSE_UPIU); 538 assert(result == 0); 539 (void)result; 540 } 541 542 #ifdef UFS_RESP_DEBUG 543 static void dump_upiu(utp_utrd_t *utrd) 544 { 545 utrd_header_t *hd; 546 int i; 547 548 hd = (utrd_header_t *)utrd->header; 549 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n", 550 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs, 551 mmio_read_32(ufs_params.reg_base + UTRLDBR)); 552 for (i = 0; i < sizeof(utrd_header_t); i += 4) { 553 INFO("[%lx]:0x%x\n", 554 (uintptr_t)utrd->header + i, 555 *(unsigned int *)((uintptr_t)utrd->header + i)); 556 } 557 558 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) { 559 INFO("cmd[%lx]:0x%x\n", 560 utrd->upiu + i, 561 *(unsigned int *)(utrd->upiu + i)); 562 } 563 for (i = 0; i < sizeof(resp_upiu_t); i += 4) { 564 INFO("resp[%lx]:0x%x\n", 565 utrd->resp_upiu + i, 566 *(unsigned int *)(utrd->resp_upiu + i)); 567 } 568 for (i = 0; i < sizeof(prdt_t); i += 4) { 569 INFO("prdt[%lx]:0x%x\n", 570 utrd->prdt + i, 571 *(unsigned int *)(utrd->prdt + i)); 572 } 573 } 574 #endif 575 576 static void ufs_verify_init(void) 577 { 578 utp_utrd_t utrd; 579 int result; 580 581 get_utrd(&utrd); 582 ufs_prepare_nop_out(&utrd); 583 ufs_send_request(utrd.task_tag); 584 result = ufs_check_resp(&utrd, NOP_IN_UPIU); 585 assert(result == 0); 586 (void)result; 587 } 588 589 static void ufs_verify_ready(void) 590 { 591 utp_utrd_t utrd; 592 ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); 593 } 594 595 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, 596 uintptr_t buf, size_t size) 597 { 598 utp_utrd_t utrd; 599 query_resp_upiu_t *resp; 600 int result; 601 602 switch (op) { 603 case QUERY_READ_FLAG: 604 case QUERY_READ_ATTR: 605 case QUERY_READ_DESC: 606 case QUERY_WRITE_DESC: 607 case QUERY_WRITE_ATTR: 608 assert(((buf & 3) == 0) && (size != 0)); 609 break; 610 default: 611 /* Do nothing in default case */ 612 break; 613 } 614 get_utrd(&utrd); 615 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); 616 ufs_send_request(utrd.task_tag); 617 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU); 618 assert(result == 0); 619 resp = (query_resp_upiu_t *)utrd.resp_upiu; 620 #ifdef UFS_RESP_DEBUG 621 dump_upiu(&utrd); 622 #endif 623 assert(resp->query_resp == QUERY_RESP_SUCCESS); 624 625 switch (op) { 626 case QUERY_READ_FLAG: 627 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value; 628 break; 629 case QUERY_READ_DESC: 630 memcpy((void *)buf, 631 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), 632 size); 633 break; 634 case QUERY_READ_ATTR: 635 *(uint32_t *)buf = htobe32(resp->ts.attr.value); 636 break; 637 default: 638 /* Do nothing in default case */ 639 break; 640 } 641 (void)result; 642 } 643 644 unsigned int ufs_read_attr(int idn) 645 { 646 unsigned int value; 647 648 ufs_query(QUERY_READ_ATTR, idn, 0, 0, 649 (uintptr_t)&value, sizeof(value)); 650 return value; 651 } 652 653 void ufs_write_attr(int idn, unsigned int value) 654 { 655 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0, 656 (uintptr_t)&value, sizeof(value)); 657 } 658 659 unsigned int ufs_read_flag(int idn) 660 { 661 unsigned int value; 662 663 ufs_query(QUERY_READ_FLAG, idn, 0, 0, 664 (uintptr_t)&value, sizeof(value)); 665 return value; 666 } 667 668 void ufs_set_flag(int idn) 669 { 670 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0); 671 } 672 673 void ufs_clear_flag(int idn) 674 { 675 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0); 676 } 677 678 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size) 679 { 680 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size); 681 } 682 683 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size) 684 { 685 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size); 686 } 687 688 static int ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) 689 { 690 utp_utrd_t utrd; 691 resp_upiu_t *resp; 692 sense_data_t *sense; 693 unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; 694 uintptr_t buf; 695 int retries = UFS_READ_CAPACITY_RETRIES; 696 697 assert((ufs_params.reg_base != 0) && 698 (ufs_params.desc_base != 0) && 699 (ufs_params.desc_size >= UFS_DESC_SIZE) && 700 (num != NULL) && (size != NULL)); 701 702 /* align buf address */ 703 buf = (uintptr_t)data; 704 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) & 705 ~(CACHE_WRITEBACK_GRANULE - 1); 706 do { 707 ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, 708 buf, READ_CAPACITY_LENGTH); 709 #ifdef UFS_RESP_DEBUG 710 dump_upiu(&utrd); 711 #endif 712 resp = (resp_upiu_t *)utrd.resp_upiu; 713 sense = &resp->sd.sense; 714 if (!((sense->resp_code == SENSE_DATA_VALID) && 715 (sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && 716 (sense->asc == 0x29) && (sense->ascq == 0))) { 717 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); 718 /* last logical block address */ 719 *num = be32toh(*(unsigned int *)buf); 720 if (*num) 721 *num += 1; 722 /* logical block length in bytes */ 723 *size = be32toh(*(unsigned int *)(buf + 4)); 724 725 return 0; 726 } 727 728 } while (retries-- > 0); 729 730 return -ETIMEDOUT; 731 } 732 733 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) 734 { 735 utp_utrd_t utrd; 736 resp_upiu_t *resp; 737 738 assert((ufs_params.reg_base != 0) && 739 (ufs_params.desc_base != 0) && 740 (ufs_params.desc_size >= UFS_DESC_SIZE)); 741 742 ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); 743 #ifdef UFS_RESP_DEBUG 744 dump_upiu(&utrd); 745 #endif 746 /* 747 * Invalidate prefetched cache contents before cpu 748 * accesses the buf. 749 */ 750 inv_dcache_range(buf, size); 751 resp = (resp_upiu_t *)utrd.resp_upiu; 752 return size - resp->res_trans_cnt; 753 } 754 755 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size) 756 { 757 utp_utrd_t utrd; 758 resp_upiu_t *resp; 759 760 assert((ufs_params.reg_base != 0) && 761 (ufs_params.desc_base != 0) && 762 (ufs_params.desc_size >= UFS_DESC_SIZE)); 763 764 ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); 765 #ifdef UFS_RESP_DEBUG 766 dump_upiu(&utrd); 767 #endif 768 resp = (resp_upiu_t *)utrd.resp_upiu; 769 return size - resp->res_trans_cnt; 770 } 771 772 static int ufs_set_fdevice_init(void) 773 { 774 unsigned int result; 775 int timeout; 776 777 ufs_set_flag(FLAG_DEVICE_INIT); 778 779 timeout = FDEVICEINIT_TIMEOUT_MS; 780 do { 781 result = ufs_read_flag(FLAG_DEVICE_INIT); 782 if (!result) { 783 break; 784 } 785 mdelay(5); 786 timeout -= 5; 787 } while (timeout > 0); 788 789 if (result != 0U) { 790 return -ETIMEDOUT; 791 } 792 793 return 0; 794 } 795 796 static void ufs_enum(void) 797 { 798 unsigned int blk_num, blk_size; 799 int i, result; 800 801 ufs_verify_init(); 802 ufs_verify_ready(); 803 804 result = ufs_set_fdevice_init(); 805 assert(result == 0); 806 807 blk_num = 0; 808 blk_size = 0; 809 810 /* dump available LUNs */ 811 for (i = 0; i < UFS_MAX_LUNS; i++) { 812 result = ufs_read_capacity(i, &blk_num, &blk_size); 813 if (result != 0) { 814 WARN("UFS LUN%d dump failed\n", i); 815 } 816 if (blk_num && blk_size) { 817 INFO("UFS LUN%d contains %d blocks with %d-byte size\n", 818 i, blk_num, blk_size); 819 } 820 } 821 822 (void)result; 823 } 824 825 static void ufs_get_device_info(struct ufs_dev_desc *card_data) 826 { 827 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE]; 828 829 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0, 830 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE); 831 832 /* 833 * getting vendor (manufacturerID) and Bank Index in big endian 834 * format 835 */ 836 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) | 837 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1])); 838 } 839 840 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params) 841 { 842 int result; 843 unsigned int data; 844 uic_cmd_t cmd; 845 struct ufs_dev_desc card = {0}; 846 847 assert((params != NULL) && 848 (params->reg_base != 0) && 849 (params->desc_base != 0) && 850 (params->desc_size >= UFS_DESC_SIZE)); 851 852 memcpy(&ufs_params, params, sizeof(ufs_params_t)); 853 854 /* 0 means 1 slot */ 855 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; 856 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) { 857 nutrs = ufs_params.desc_size / UFS_DESC_SIZE; 858 } 859 860 861 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { 862 result = ufshc_dme_get(0x1571, 0, &data); 863 assert(result == 0); 864 result = ufshc_dme_get(0x41, 0, &data); 865 assert(result == 0); 866 if (data == 1) { 867 /* prepare to exit hibernate mode */ 868 memset(&cmd, 0, sizeof(uic_cmd_t)); 869 cmd.op = DME_HIBERNATE_EXIT; 870 result = ufshc_send_uic_cmd(ufs_params.reg_base, 871 &cmd); 872 assert(result == 0); 873 data = mmio_read_32(ufs_params.reg_base + UCMDARG2); 874 assert(data == 0); 875 do { 876 data = mmio_read_32(ufs_params.reg_base + IS); 877 } while ((data & UFS_INT_UHXS) == 0); 878 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS); 879 data = mmio_read_32(ufs_params.reg_base + HCS); 880 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL); 881 } 882 result = ufshc_dme_get(0x1568, 0, &data); 883 assert(result == 0); 884 assert((data > 0) && (data <= 3)); 885 } else { 886 assert((ops != NULL) && (ops->phy_init != NULL) && 887 (ops->phy_set_pwr_mode != NULL)); 888 889 result = ufshc_reset(ufs_params.reg_base); 890 assert(result == 0); 891 ops->phy_init(&ufs_params); 892 result = ufshc_link_startup(ufs_params.reg_base); 893 assert(result == 0); 894 895 ufs_enum(); 896 897 ufs_get_device_info(&card); 898 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) { 899 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX; 900 } 901 902 ops->phy_set_pwr_mode(&ufs_params); 903 } 904 905 (void)result; 906 return 0; 907 } 908