1*6fa56e93SAbhi Singh /*
2*6fa56e93SAbhi Singh * Copyright (c) 2025, Arm Limited. All rights reserved.
3*6fa56e93SAbhi Singh *
4*6fa56e93SAbhi Singh * SPDX-License-Identifier: BSD-3-Clause
5*6fa56e93SAbhi Singh */
6*6fa56e93SAbhi Singh
7*6fa56e93SAbhi Singh #include <drivers/delay_timer.h>
8*6fa56e93SAbhi Singh #include <drivers/gpio.h>
9*6fa56e93SAbhi Singh #include <drivers/tpm/tpm2_slb9670/slb9670_gpio.h>
10*6fa56e93SAbhi Singh
11*6fa56e93SAbhi Singh /*
12*6fa56e93SAbhi Singh * Infineon SLB9670 Chip Reset Parameters
13*6fa56e93SAbhi Singh */
14*6fa56e93SAbhi Singh #define t_WRST 2 /* Warm Reset Time (us) */
15*6fa56e93SAbhi Singh #define t_RSTIN 60 /* Reset Inactive Time (ms) */
16*6fa56e93SAbhi Singh
17*6fa56e93SAbhi Singh /*
18*6fa56e93SAbhi Singh * RPi3 GPIO pin configuration for TPM via bit-bang SPI
19*6fa56e93SAbhi Singh * References: https://pinout.xyz/pinout/spi
20*6fa56e93SAbhi Singh * - docs/design_documents/measured_boot_dtpm_poc.rst
21*6fa56e93SAbhi Singh */
22*6fa56e93SAbhi Singh const struct gpio_spi_data tpm_rpi3_gpio_data = {
23*6fa56e93SAbhi Singh .cs_gpio = 7,
24*6fa56e93SAbhi Singh .sclk_gpio = 11,
25*6fa56e93SAbhi Singh .mosi_gpio = 10,
26*6fa56e93SAbhi Singh .miso_gpio = 9,
27*6fa56e93SAbhi Singh .reset_gpio = 24,
28*6fa56e93SAbhi Singh .spi_delay_us = 0,
29*6fa56e93SAbhi Singh .spi_mode = 0
30*6fa56e93SAbhi Singh };
31*6fa56e93SAbhi Singh
32*6fa56e93SAbhi Singh /*
33*6fa56e93SAbhi Singh * When RST is asserted at certain points in time, then this
34*6fa56e93SAbhi Singh * triggers the TPM's security functions, in the case where
35*6fa56e93SAbhi Singh * multiple resets need to be asserted, there must be a wait
36*6fa56e93SAbhi Singh * of at least t_RSTIN between the resets
37*6fa56e93SAbhi Singh *
38*6fa56e93SAbhi Singh * In most cases this is not needed since RST is only being asserted
39*6fa56e93SAbhi Singh * once, ie for TPM initialization at the beginning of TFA.
40*6fa56e93SAbhi Singh */
tpm2_slb9670_reset_chip(struct gpio_spi_data * tpm_gpio_data)41*6fa56e93SAbhi Singh void tpm2_slb9670_reset_chip(struct gpio_spi_data *tpm_gpio_data)
42*6fa56e93SAbhi Singh {
43*6fa56e93SAbhi Singh /*
44*6fa56e93SAbhi Singh * since we don't know the value of the pin before it was init to 1
45*6fa56e93SAbhi Singh * it is best to assume the state was 0, and account for that by
46*6fa56e93SAbhi Singh * adding an initial RST inactive delay
47*6fa56e93SAbhi Singh */
48*6fa56e93SAbhi Singh mdelay(t_RSTIN);
49*6fa56e93SAbhi Singh /* pull #RST pin to active low for 2us */
50*6fa56e93SAbhi Singh gpio_set_value(tpm_gpio_data->reset_gpio, 0);
51*6fa56e93SAbhi Singh udelay(t_WRST);
52*6fa56e93SAbhi Singh /* wait 60ms after warm reset before sending TPM commands */
53*6fa56e93SAbhi Singh gpio_set_value(tpm_gpio_data->reset_gpio, 1);
54*6fa56e93SAbhi Singh mdelay(t_RSTIN);
55*6fa56e93SAbhi Singh }
56*6fa56e93SAbhi Singh
57*6fa56e93SAbhi Singh /*
58*6fa56e93SAbhi Singh * init GPIO pins for the Infineon slb9670 TPM
59*6fa56e93SAbhi Singh */
tpm2_slb9670_gpio_init(struct gpio_spi_data * tpm_gpio_data)60*6fa56e93SAbhi Singh void tpm2_slb9670_gpio_init(struct gpio_spi_data *tpm_gpio_data)
61*6fa56e93SAbhi Singh {
62*6fa56e93SAbhi Singh gpio_set_value(tpm_gpio_data->cs_gpio, 1);
63*6fa56e93SAbhi Singh gpio_set_direction(tpm_gpio_data->cs_gpio, GPIO_DIR_OUT);
64*6fa56e93SAbhi Singh
65*6fa56e93SAbhi Singh gpio_set_value(tpm_gpio_data->sclk_gpio, 0);
66*6fa56e93SAbhi Singh gpio_set_direction(tpm_gpio_data->sclk_gpio, GPIO_DIR_OUT);
67*6fa56e93SAbhi Singh
68*6fa56e93SAbhi Singh gpio_set_value(tpm_gpio_data->mosi_gpio, 1);
69*6fa56e93SAbhi Singh gpio_set_direction(tpm_gpio_data->mosi_gpio, GPIO_DIR_OUT);
70*6fa56e93SAbhi Singh
71*6fa56e93SAbhi Singh gpio_set_direction(tpm_gpio_data->miso_gpio, GPIO_DIR_IN);
72*6fa56e93SAbhi Singh
73*6fa56e93SAbhi Singh gpio_set_value(tpm_gpio_data->reset_gpio, 1);
74*6fa56e93SAbhi Singh gpio_set_direction(tpm_gpio_data->reset_gpio, GPIO_DIR_OUT);
75*6fa56e93SAbhi Singh }
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