1 /* 2 * Texas Instruments System Control Interface (TISCI) Protocol 3 * 4 * Communication protocol with TI SCI hardware 5 * The system works in a message response protocol 6 * See: http://processors.wiki.ti.com/index.php/TISCI for details 7 * 8 * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ 9 * 10 * SPDX-License-Identifier: BSD-3-Clause 11 */ 12 13 #ifndef TI_SCI_PROTOCOL_H 14 #define TI_SCI_PROTOCOL_H 15 16 #include <stdint.h> 17 18 /* Generic Messages */ 19 #define TI_SCI_MSG_ENABLE_WDT 0x0000 20 #define TI_SCI_MSG_WAKE_RESET 0x0001 21 #define TI_SCI_MSG_VERSION 0x0002 22 #define TI_SCI_MSG_WAKE_REASON 0x0003 23 #define TI_SCI_MSG_GOODBYE 0x0004 24 #define TI_SCI_MSG_SYS_RESET 0x0005 25 #define TI_SCI_MSG_BOOT_NOTIFICATION 0x000A 26 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 27 28 /* Device requests */ 29 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 30 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 31 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 32 33 /* Low Power Mode Requests */ 34 #define TI_SCI_MSG_ENTER_SLEEP 0x0301 35 #define TI_SCI_MSG_LPM_GET_NEXT_SYS_MODE 0x030d 36 #define TISCI_MSG_LPM_ENCRYPT_TFA 0x030F 37 38 /* Clock requests */ 39 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 40 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 41 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 42 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 43 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 44 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 45 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 46 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 47 48 /* Processor Control Messages */ 49 #define TISCI_MSG_PROC_REQUEST 0xc000 50 #define TISCI_MSG_PROC_RELEASE 0xc001 51 #define TISCI_MSG_PROC_HANDOVER 0xc005 52 #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100 53 #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101 54 #define TISCI_MSG_PROC_AUTH_BOOT_IMAGE 0xc120 55 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400 56 #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401 57 58 /** 59 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent 60 * via secure transport. 61 * @checksum: crc16 checksum for the entire message 62 * @reserved: Reserved for future use. 63 */ 64 struct ti_sci_secure_msg_hdr { 65 uint16_t checksum; 66 uint16_t reserved; 67 } __packed; 68 69 /** 70 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 71 * @type: Type of messages: One of TI_SCI_MSG* values 72 * @host: Host of the message 73 * @seq: Message identifier indicating a transfer sequence 74 * @flags: Flag for the message 75 */ 76 struct ti_sci_msg_hdr { 77 struct ti_sci_secure_msg_hdr sec_hdr; 78 uint16_t type; 79 uint8_t host; 80 uint8_t seq; 81 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 82 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 83 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 84 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 85 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 86 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 87 /* Additional Flags */ 88 uint32_t flags; 89 } __packed; 90 91 /** 92 * struct ti_sci_msg_version_req - Request for firmware version information 93 * @hdr: Generic header 94 * 95 * Request for TI_SCI_MSG_VERSION 96 */ 97 struct ti_sci_msg_req_version { 98 struct ti_sci_msg_hdr hdr; 99 } __packed; 100 101 /** 102 * struct ti_sci_msg_resp_version - Response for firmware version information 103 * @hdr: Generic header 104 * @firmware_description: String describing the firmware 105 * @firmware_revision: Firmware revision 106 * @abi_major: Major version of the ABI that firmware supports 107 * @abi_minor: Minor version of the ABI that firmware supports 108 * @sub_version: Sub-version number of the firmware 109 * @patch_version: Patch-version number of the firmware. 110 * 111 * In general, ABI version changes follow the rule that minor version increments 112 * are backward compatible. Major revision changes in ABI may not be 113 * backward compatible. 114 * 115 * Response to request TI_SCI_MSG_VERSION 116 */ 117 struct ti_sci_msg_resp_version { 118 struct ti_sci_msg_hdr hdr; 119 #define FIRMWARE_DESCRIPTION_LENGTH 32 120 char firmware_description[FIRMWARE_DESCRIPTION_LENGTH]; 121 uint16_t firmware_revision; 122 uint8_t abi_major; 123 uint8_t abi_minor; 124 uint8_t sub_version; 125 uint8_t patch_version; 126 } __packed; 127 128 /** 129 * struct ti_sci_msg_req_reboot - Reboot the SoC 130 * @hdr: Generic Header 131 * @domain: Domain to be reset, 0 for full SoC reboot 132 * 133 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 134 * ACK/NACK message. 135 */ 136 struct ti_sci_msg_req_reboot { 137 struct ti_sci_msg_hdr hdr; 138 #define TI_SCI_DOMAIN_FULL_SOC_RESET 0x0 139 uint8_t domain; 140 } __packed; 141 142 /** 143 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 144 * @hdr: Generic header 145 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 146 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 147 * MSG_FLAG_CAPS_LPM_DEEP_SLEEP: Deep Sleep LPM 148 * MSG_FLAG_CAPS_LPM_MCU_ONLY: MCU only LPM 149 * MSG_FLAG_CAPS_LPM_STANDBY: Standby LPM 150 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 151 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 152 * 153 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 154 * providing currently available SOC/firmware capabilities. SoC that don't 155 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 156 */ 157 struct ti_sci_msg_resp_query_fw_caps { 158 struct ti_sci_msg_hdr hdr; 159 #define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 160 #define MSG_FLAG_CAPS_LPM_DEEP_SLEEP TI_SCI_MSG_FLAG(1) 161 #define MSG_FLAG_CAPS_LPM_MCU_ONLY TI_SCI_MSG_FLAG(2) 162 #define MSG_FLAG_CAPS_LPM_STANDBY TI_SCI_MSG_FLAG(3) 163 #define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 164 #define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 165 #define MSG_FLAG_CAPS_LPM_ENCRYPT_IMAGE TI_SCI_MSG_FLAG(11) 166 #define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12) 167 uint64_t fw_caps; 168 } __packed; 169 170 /** 171 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 172 * @hdr: Generic header 173 * @id: Indicates which device to modify 174 * @reserved: Reserved space in message, must be 0 for backward compatibility 175 * @state: The desired state of the device. 176 * 177 * Certain flags can also be set to alter the device state: 178 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 179 * The meaning of this flag will vary slightly from device to device and from 180 * SoC to SoC but it generally allows the device to wake the SoC out of deep 181 * suspend states. 182 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 183 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 184 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 185 * If another host already has this device set to STATE_RETENTION or STATE_ON, 186 * the message will fail. Once successful, other hosts attempting to set 187 * STATE_RETENTION or STATE_ON will fail. 188 * 189 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 190 * ACK/NACK message. 191 */ 192 struct ti_sci_msg_req_set_device_state { 193 /* Additional hdr->flags options */ 194 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 195 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 196 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 197 struct ti_sci_msg_hdr hdr; 198 uint32_t id; 199 uint32_t reserved; 200 201 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 202 #define MSG_DEVICE_SW_STATE_RETENTION 1 203 #define MSG_DEVICE_SW_STATE_ON 2 204 uint8_t state; 205 } __packed; 206 207 /** 208 * struct ti_sci_msg_req_get_device_state - Request to get device. 209 * @hdr: Generic header 210 * @id: Device Identifier 211 * 212 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 213 * information 214 */ 215 struct ti_sci_msg_req_get_device_state { 216 struct ti_sci_msg_hdr hdr; 217 uint32_t id; 218 } __packed; 219 220 /** 221 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 222 * @hdr: Generic header 223 * @context_loss_count: Indicates how many times the device has lost context. A 224 * driver can use this monotonic counter to determine if the device has 225 * lost context since the last time this message was exchanged. 226 * @resets: Programmed state of the reset lines. 227 * @programmed_state: The state as programmed by set_device. 228 * - Uses the MSG_DEVICE_SW_* macros 229 * @current_state: The actual state of the hardware. 230 * 231 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 232 */ 233 struct ti_sci_msg_resp_get_device_state { 234 struct ti_sci_msg_hdr hdr; 235 uint32_t context_loss_count; 236 uint32_t resets; 237 uint8_t programmed_state; 238 #define MSG_DEVICE_HW_STATE_OFF 0 239 #define MSG_DEVICE_HW_STATE_ON 1 240 #define MSG_DEVICE_HW_STATE_TRANS 2 241 uint8_t current_state; 242 } __packed; 243 244 /** 245 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 246 * configuration of the device 247 * @hdr: Generic header 248 * @id: Indicates which device to modify 249 * @resets: A bit field of resets for the device. The meaning, behavior, 250 * and usage of the reset flags are device specific. 0 for a bit 251 * indicates releasing the reset represented by that bit while 1 252 * indicates keeping it held. 253 * 254 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 255 * ACK/NACK message. 256 */ 257 struct ti_sci_msg_req_set_device_resets { 258 struct ti_sci_msg_hdr hdr; 259 uint32_t id; 260 uint32_t resets; 261 } __packed; 262 263 /** 264 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 265 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 266 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 267 * via spread spectrum clocking. 268 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 269 * frequency to be changed while it is running so long as it 270 * is within the min/max limits. 271 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 272 * is only applicable to clock inputs on the SoC pseudo-device. 273 * @dev_id: Device identifier this request is for 274 * @clk_id: Clock identifier for the device for this request. 275 * Each device has it's own set of clock inputs. This indexes 276 * which clock input to modify. 277 * @request_state: Request the state for the clock to be set to. 278 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 279 * it can be disabled, regardless of the state of the device 280 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 281 * automatically manage the state of this clock. If the device 282 * is enabled, then the clock is enabled. If the device is set 283 * to off or retention, then the clock is internally set as not 284 * being required by the device.(default) 285 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 286 * regardless of the state of the device. 287 * 288 * Normally, all required clocks are managed by TISCI entity, this is used 289 * only for specific control *IF* required. Auto managed state is 290 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 291 * will explicitly control. 292 * 293 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 294 * ACK or NACK message. 295 */ 296 struct ti_sci_msg_req_set_clock_state { 297 /* Additional hdr->flags options */ 298 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 299 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 300 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 301 struct ti_sci_msg_hdr hdr; 302 uint32_t dev_id; 303 uint8_t clk_id; 304 #define MSG_CLOCK_SW_STATE_UNREQ 0 305 #define MSG_CLOCK_SW_STATE_AUTO 1 306 #define MSG_CLOCK_SW_STATE_REQ 2 307 uint8_t request_state; 308 } __packed; 309 310 /** 311 * struct ti_sci_msg_req_get_clock_state - Request for clock state 312 * @hdr: Generic Header 313 * @dev_id: Device identifier this request is for 314 * @clk_id: Clock identifier for the device for this request. 315 * Each device has it's own set of clock inputs. This indexes 316 * which clock input to get state of. 317 * 318 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 319 * of the clock 320 */ 321 struct ti_sci_msg_req_get_clock_state { 322 struct ti_sci_msg_hdr hdr; 323 uint32_t dev_id; 324 uint8_t clk_id; 325 } __packed; 326 327 /** 328 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 329 * @hdr: Generic Header 330 * @programmed_state: Any programmed state of the clock. This is one of 331 * MSG_CLOCK_SW_STATE* values. 332 * @current_state: Current state of the clock. This is one of: 333 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 334 * MSG_CLOCK_HW_STATE_READY: Clock is ready 335 * 336 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 337 */ 338 struct ti_sci_msg_resp_get_clock_state { 339 struct ti_sci_msg_hdr hdr; 340 uint8_t programmed_state; 341 #define MSG_CLOCK_HW_STATE_NOT_READY 0 342 #define MSG_CLOCK_HW_STATE_READY 1 343 uint8_t current_state; 344 } __packed; 345 346 /** 347 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 348 * @hdr: Generic Header 349 * @dev_id: Device identifier this request is for 350 * @clk_id: Clock identifier for the device for this request. 351 * Each device has it's own set of clock inputs. This indexes 352 * which clock input to modify. 353 * @parent_id: The new clock parent is selectable by an index via this 354 * parameter. 355 * 356 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 357 * ACK / NACK message. 358 */ 359 struct ti_sci_msg_req_set_clock_parent { 360 struct ti_sci_msg_hdr hdr; 361 uint32_t dev_id; 362 uint8_t clk_id; 363 uint8_t parent_id; 364 } __packed; 365 366 /** 367 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 368 * @hdr: Generic Header 369 * @dev_id: Device identifier this request is for 370 * @clk_id: Clock identifier for the device for this request. 371 * Each device has it's own set of clock inputs. This indexes 372 * which clock input to get the parent for. 373 * 374 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 375 */ 376 struct ti_sci_msg_req_get_clock_parent { 377 struct ti_sci_msg_hdr hdr; 378 uint32_t dev_id; 379 uint8_t clk_id; 380 } __packed; 381 382 /** 383 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 384 * @hdr: Generic Header 385 * @parent_id: The current clock parent 386 * 387 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 388 */ 389 struct ti_sci_msg_resp_get_clock_parent { 390 struct ti_sci_msg_hdr hdr; 391 uint8_t parent_id; 392 } __packed; 393 394 /** 395 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 396 * @hdr: Generic header 397 * @dev_id: Device identifier this request is for 398 * @clk_id: Clock identifier for the device for this request. 399 * 400 * This request provides information about how many clock parent options 401 * are available for a given clock to a device. This is typically used 402 * for input clocks. 403 * 404 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 405 * message, or NACK in case of inability to satisfy request. 406 */ 407 struct ti_sci_msg_req_get_clock_num_parents { 408 struct ti_sci_msg_hdr hdr; 409 uint32_t dev_id; 410 uint8_t clk_id; 411 } __packed; 412 413 /** 414 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 415 * @hdr: Generic header 416 * @num_parents: Number of clock parents 417 * 418 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 419 */ 420 struct ti_sci_msg_resp_get_clock_num_parents { 421 struct ti_sci_msg_hdr hdr; 422 uint8_t num_parents; 423 } __packed; 424 425 /** 426 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 427 * @hdr: Generic Header 428 * @dev_id: Device identifier this request is for 429 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 430 * allowable programmed frequency and does not account for clock 431 * tolerances and jitter. 432 * @target_freq_hz: The target clock frequency. A frequency will be found 433 * as close to this target frequency as possible. 434 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 435 * allowable programmed frequency and does not account for clock 436 * tolerances and jitter. 437 * @clk_id: Clock identifier for the device for this request. 438 * 439 * NOTE: Normally clock frequency management is automatically done by TISCI 440 * entity. In case of specific requests, TISCI evaluates capability to achieve 441 * requested frequency within provided range and responds with 442 * result message. 443 * 444 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 445 * or NACK in case of inability to satisfy request. 446 */ 447 struct ti_sci_msg_req_query_clock_freq { 448 struct ti_sci_msg_hdr hdr; 449 uint32_t dev_id; 450 uint64_t min_freq_hz; 451 uint64_t target_freq_hz; 452 uint64_t max_freq_hz; 453 uint8_t clk_id; 454 } __packed; 455 456 /** 457 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 458 * @hdr: Generic Header 459 * @freq_hz: Frequency that is the best match in Hz. 460 * 461 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 462 * cannot be satisfied, the message will be of type NACK. 463 */ 464 struct ti_sci_msg_resp_query_clock_freq { 465 struct ti_sci_msg_hdr hdr; 466 uint64_t freq_hz; 467 } __packed; 468 469 /** 470 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 471 * @hdr: Generic Header 472 * @dev_id: Device identifier this request is for 473 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 474 * allowable programmed frequency and does not account for clock 475 * tolerances and jitter. 476 * @target_freq_hz: The target clock frequency. The clock will be programmed 477 * at a rate as close to this target frequency as possible. 478 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 479 * allowable programmed frequency and does not account for clock 480 * tolerances and jitter. 481 * @clk_id: Clock identifier for the device for this request. 482 * 483 * NOTE: Normally clock frequency management is automatically done by TISCI 484 * entity. In case of specific requests, TISCI evaluates capability to achieve 485 * requested range and responds with success/failure message. 486 * 487 * This sets the desired frequency for a clock within an allowable 488 * range. This message will fail on an enabled clock unless 489 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 490 * if other clocks have their frequency modified due to this message, 491 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 492 * 493 * Calling set frequency on a clock input to the SoC pseudo-device will 494 * inform the PMMC of that clock's frequency. Setting a frequency of 495 * zero will indicate the clock is disabled. 496 * 497 * Calling set frequency on clock outputs from the SoC pseudo-device will 498 * function similarly to setting the clock frequency on a device. 499 * 500 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 501 * message. 502 */ 503 struct ti_sci_msg_req_set_clock_freq { 504 struct ti_sci_msg_hdr hdr; 505 uint32_t dev_id; 506 uint64_t min_freq_hz; 507 uint64_t target_freq_hz; 508 uint64_t max_freq_hz; 509 uint8_t clk_id; 510 } __packed; 511 512 /** 513 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 514 * @hdr: Generic Header 515 * @dev_id: Device identifier this request is for 516 * @clk_id: Clock identifier for the device for this request. 517 * 518 * NOTE: Normally clock frequency management is automatically done by TISCI 519 * entity. In some cases, clock frequencies are configured by host. 520 * 521 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 522 * that the clock is currently at. 523 */ 524 struct ti_sci_msg_req_get_clock_freq { 525 struct ti_sci_msg_hdr hdr; 526 uint32_t dev_id; 527 uint8_t clk_id; 528 } __packed; 529 530 /** 531 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 532 * @hdr: Generic Header 533 * @freq_hz: Frequency that the clock is currently on, in Hz. 534 * 535 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 536 */ 537 struct ti_sci_msg_resp_get_clock_freq { 538 struct ti_sci_msg_hdr hdr; 539 uint64_t freq_hz; 540 } __packed; 541 542 #define TISCI_ADDR_LOW_MASK 0x00000000ffffffff 543 #define TISCI_ADDR_HIGH_MASK 0xffffffff00000000 544 #define TISCI_ADDR_HIGH_SHIFT 32 545 546 /** 547 * struct ti_sci_msg_req_proc_request - Request a processor 548 * 549 * @hdr: Generic Header 550 * @processor_id: ID of processor 551 * 552 * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 553 * message. 554 */ 555 struct ti_sci_msg_req_proc_request { 556 struct ti_sci_msg_hdr hdr; 557 uint8_t processor_id; 558 } __packed; 559 560 /** 561 * struct ti_sci_msg_req_proc_release - Release a processor 562 * 563 * @hdr: Generic Header 564 * @processor_id: ID of processor 565 * 566 * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 567 * message. 568 */ 569 struct ti_sci_msg_req_proc_release { 570 struct ti_sci_msg_hdr hdr; 571 uint8_t processor_id; 572 } __packed; 573 574 /** 575 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 576 * 577 * @hdr: Generic Header 578 * @processor_id: ID of processor 579 * @host_id: New Host we want to give control to 580 * 581 * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 582 * message. 583 */ 584 struct ti_sci_msg_req_proc_handover { 585 struct ti_sci_msg_hdr hdr; 586 uint8_t processor_id; 587 uint8_t host_id; 588 } __packed; 589 590 /* A53 Config Flags */ 591 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001 592 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002 593 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004 594 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008 595 #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100 596 597 /* R5 Config Flags */ 598 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001 599 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002 600 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100 601 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200 602 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400 603 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800 604 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000 605 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000 606 607 /** 608 * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration 609 * @hdr: Generic Header 610 * @processor_id: ID of processor 611 * @bootvector_low: Lower 32bit (Little Endian) of boot vector 612 * @bootvector_high: Higher 32bit (Little Endian) of boot vector 613 * @config_flags_set: Optional Processor specific Config Flags to set. 614 * Setting a bit here implies required bit sets to 1. 615 * @config_flags_clear: Optional Processor specific Config Flags to clear. 616 * Setting a bit here implies required bit gets cleared. 617 * 618 * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic 619 * ACK/NACK message. 620 */ 621 struct ti_sci_msg_req_set_proc_boot_config { 622 struct ti_sci_msg_hdr hdr; 623 uint8_t processor_id; 624 uint32_t bootvector_low; 625 uint32_t bootvector_high; 626 uint32_t config_flags_set; 627 uint32_t config_flags_clear; 628 } __packed; 629 630 /* ARMV8 Control Flags */ 631 #define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM 0x00000001 632 #define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS 0x00000002 633 #define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ 0x00000100 634 635 /* R5 Control Flags */ 636 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 637 638 /** 639 * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags 640 * @hdr: Generic Header 641 * @processor_id: ID of processor 642 * @config_flags_set: Optional Processor specific Config Flags to set. 643 * Setting a bit here implies required bit sets to 1. 644 * @config_flags_clear: Optional Processor specific Config Flags to clear. 645 * Setting a bit here implies required bit gets cleared. 646 * 647 * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK 648 * message. 649 */ 650 struct ti_sci_msg_req_set_proc_boot_ctrl { 651 struct ti_sci_msg_hdr hdr; 652 uint8_t processor_id; 653 uint32_t control_flags_set; 654 uint32_t control_flags_clear; 655 } __packed; 656 657 /** 658 * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image 659 * @hdr: Generic Header 660 * @processor_id: ID of processor 661 * @cert_addr_low: Lower 32bit (Little Endian) of certificate 662 * @cert_addr_high: Higher 32bit (Little Endian) of certificate 663 * 664 * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic 665 * ACK/NACK message. 666 */ 667 struct ti_sci_msg_req_proc_auth_boot_image { 668 struct ti_sci_msg_hdr hdr; 669 uint8_t processor_id; 670 uint32_t cert_addr_low; 671 uint32_t cert_addr_high; 672 } __packed; 673 674 /** 675 * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status 676 * @hdr: Generic Header 677 * @processor_id: ID of processor 678 * 679 * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate 680 * message, or NACK in case of inability to satisfy request. 681 */ 682 struct ti_sci_msg_req_get_proc_boot_status { 683 struct ti_sci_msg_hdr hdr; 684 uint8_t processor_id; 685 } __packed; 686 687 /* ARMv8 Status Flags */ 688 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001 689 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002 690 #define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE 0x00000010 691 #define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 0x00000020 692 693 /* R5 Status Flags */ 694 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 695 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 696 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004 697 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100 698 699 /** 700 * \brief Processor Status Response 701 * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response 702 * @hdr: Generic Header 703 * @processor_id: ID of processor 704 * @bootvector_low: Lower 32bit (Little Endian) of boot vector 705 * @bootvector_high: Higher 32bit (Little Endian) of boot vector 706 * @config_flags: Optional Processor specific Config Flags set. 707 * @control_flags: Optional Processor specific Control Flags. 708 * @status_flags: Optional Processor specific Status Flags set. 709 * 710 * Response to TISCI_MSG_GET_PROC_BOOT_STATUS. 711 */ 712 struct ti_sci_msg_resp_get_proc_boot_status { 713 struct ti_sci_msg_hdr hdr; 714 uint8_t processor_id; 715 uint32_t bootvector_low; 716 uint32_t bootvector_high; 717 uint32_t config_flags; 718 uint32_t control_flags; 719 uint32_t status_flags; 720 } __packed; 721 722 /** 723 * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor boot status 724 * @hdr: Generic Header 725 * @processor_id: ID of processor 726 * @num_wait_iterations Total number of iterations we will check before 727 * we will timeout and give up 728 * @num_match_iterations How many iterations should we have continued 729 * status to account for status bits glitching. 730 * This is to make sure that match occurs for 731 * consecutive checks. This implies that the 732 * worst case should consider that the stable 733 * time should at the worst be num_wait_iterations 734 * num_match_iterations to prevent timeout. 735 * @delay_per_iteration_us Specifies how long to wait (in micro seconds) 736 * between each status checks. This is the minimum 737 * duration, and overhead of register reads and 738 * checks are on top of this and can vary based on 739 * varied conditions. 740 * @delay_before_iterations_us Specifies how long to wait (in micro seconds) 741 * before the very first check in the first 742 * iteration of status check loop. This is the 743 * minimum duration, and overhead of register 744 * reads and checks are. 745 * @status_flags_1_set_all_wait If non-zero, Specifies that all bits of the 746 * status matching this field requested MUST be 1. 747 * @status_flags_1_set_any_wait If non-zero, Specifies that at least one of the 748 * bits matching this field requested MUST be 1. 749 * @status_flags_1_clr_all_wait If non-zero, Specifies that all bits of the 750 * status matching this field requested MUST be 0. 751 * @status_flags_1_clr_any_wait If non-zero, Specifies that at least one of the 752 * bits matching this field requested MUST be 0. 753 * 754 * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate 755 * message, or NACK in case of inability to satisfy request. 756 */ 757 struct ti_sci_msg_req_wait_proc_boot_status { 758 struct ti_sci_msg_hdr hdr; 759 uint8_t processor_id; 760 uint8_t num_wait_iterations; 761 uint8_t num_match_iterations; 762 uint8_t delay_per_iteration_us; 763 uint8_t delay_before_iterations_us; 764 uint32_t status_flags_1_set_all_wait; 765 uint32_t status_flags_1_set_any_wait; 766 uint32_t status_flags_1_clr_all_wait; 767 uint32_t status_flags_1_clr_any_wait; 768 } __packed; 769 770 /** 771 * struct ti_sci_msg_req_enter_sleep - Request for TI_SCI_MSG_ENTER_SLEEP. 772 * 773 * @hdr Generic Header 774 * @mode Low power mode to enter. 775 * @proc_id Processor id to be restored. 776 * @core_resume_lo Low 32-bits of physical pointer to address for core 777 * to begin execution upon resume. 778 * @core_resume_hi High 32-bits of physical pointer to address for core 779 * to begin execution upon resume. 780 * 781 * This message is to be sent after TI_SCI_MSG_PREPARE_SLEEP is sent from OS 782 * and is what actually triggers entry into the specified low power mode. 783 */ 784 struct ti_sci_msg_req_enter_sleep { 785 struct ti_sci_msg_hdr hdr; 786 #define MSG_VALUE_SLEEP_MODE_DEEP_SLEEP 0x0 787 uint8_t mode; 788 uint8_t processor_id; 789 uint32_t core_resume_lo; 790 uint32_t core_resume_hi; 791 } __packed; 792 793 /** 794 * struct ti_sci_msg_req_lpm_get_next_sys_mode - Request for TI_SCI_MSG_LPM_GET_NEXT_SYS_MODE. 795 * 796 * @hdr Generic Header 797 * 798 * This message is used to enquire DM for selected system wide low power mode. 799 */ 800 struct ti_sci_msg_req_lpm_get_next_sys_mode { 801 struct ti_sci_msg_hdr hdr; 802 } __packed; 803 804 /** 805 * struct ti_sci_msg_resp_lpm_get_next_sys_mode - Response for TI_SCI_MSG_LPM_GET_NEXT_SYS_MODE. 806 * 807 * @hdr Generic Header 808 * @mode The selected system wide low power mode. 809 * 810 * Note: If the mode selection is not yet locked, this API returns "not selected" mode. 811 */ 812 struct ti_sci_msg_resp_lpm_get_next_sys_mode { 813 struct ti_sci_msg_hdr hdr; 814 uint8_t mode; 815 } __packed; 816 817 /** 818 * struct tisci_msg_boot_notification_msg - Response to TIFS boot notification 819 * 820 * This structure is used to consume the self initiated boot notification message 821 * from TIFS(TI Foundation Security) firmware which indicates that it is available. 822 * 823 * @hdr: Standard TISCI message header. 824 * @extboot_status: Status of extended boot. Applicable only for combined image 825 */ 826 struct tisci_msg_boot_notification_msg { 827 struct ti_sci_msg_hdr hdr; 828 uint32_t extboot_status; 829 } __packed; 830 831 /* 832 * struct ti_sci_msg_req_encrypt_tfa - Request for TISCI_MSG_LPM_ENCRYPT_TFA. 833 * 834 * @hdr: Standard TISCI message header. 835 * @src_tfa_addr: Address where the TFA lies unencrypted 836 * @src_tfa_len: Size of the TFA unencrypted 837 * 838 * This message is to be sent when the system is going in suspend, just before 839 * TI_SCI_MSG_ENTER_SLEEP. 840 * The TIFS will then encrypt the TFA and store it in RAM, along with a private 841 * header. 842 * Upon resume, the SPL will ask TIFS to decrypt it back. 843 */ 844 struct ti_sci_msg_req_encrypt_tfa { 845 struct ti_sci_msg_hdr hdr; 846 uint64_t src_tfa_addr; 847 uint32_t src_tfa_len; 848 } __packed; 849 850 /* 851 * struct ti_sci_msg_req_encrypt_tfa - Response for TISCI_MSG_LPM_ENCRYPT_TFA. 852 * 853 * @hdr: Standard TISCI message header. 854 */ 855 struct ti_sci_msg_resp_encrypt_tfa { 856 struct ti_sci_msg_hdr hdr; 857 } __packed; 858 859 #endif /* TI_SCI_PROTOCOL_H */ 860