xref: /rk3399_ARM-atf/drivers/ti/ipc/mailbox.c (revision a1032beb656d78d1cffc97fa64c961d098b23b48)
1 /*
2  * Texas Instruments Mailbox Driver
3  *
4  * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #include <assert.h>
10 #include <errno.h>
11 #include <stdlib.h>
12 
13 #include <arch_helpers.h>
14 #include <common/debug.h>
15 #include <drivers/delay_timer.h>
16 #include <lib/mmio.h>
17 #include <lib/utils.h>
18 #include <lib/utils_def.h>
19 #include <ti_sci_transport.h>
20 
21 #include <platform_def.h>
22 
23 /*
24  * TI_MAILBOX_RX/TX_BASE and the MAILBOX_MAX_MESSAGE_SIZE values are expected
25  * to come from platform specific header file ie. platform_def.h
26  */
27 
28 #define TI_MAILBOX_SYSC		UL(0x10)
29 #define TI_MAILBOX_MSG		UL(0x40)
30 #define TI_MAILBOX_FIFO_STATUS	UL(0x80)
31 #define TI_MAILBOX_MSG_STATUS		UL(0xc0)
32 
33 /*
34  * Function to poll for mailbox rx messages
35  * IRQ model is currently not in scope of this driver
36  */
37 static int8_t ti_mailbox_poll_rx_status(void)
38 {
39 	uint32_t num_messages_pending = 0U;
40 	uint32_t retry_count = 100U;
41 
42 	/*
43 	 * Keep polling till we get a message for 100 times
44 	 * with intervals of 10 milliseconds.
45 	 */
46 	while (num_messages_pending == 0U) {
47 		num_messages_pending = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS);
48 		if (retry_count-- == 0U) {
49 			return -ETIMEDOUT;
50 		}
51 		mdelay(10);
52 	}
53 	return 0;
54 }
55 
56 int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id)
57 {
58 	/* MSG_STATUS tells us how many pending messages */
59 	uint32_t try_count = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS);
60 
61 	/* Run the loop till the status register is cleared */
62 	while (mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS) != 0U) {
63 		WARN("Clearing message from mailbox FIFO\n");
64 		/* The act of reading the mailbox msg itself clears it */
65 		mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG);
66 		/*
67 		 * The try_count is kept independent of the value of the status register
68 		 * because if at any point a new mailbox message arrives while this loop
69 		 * is in progress, we would want to know that message arrived and not clear
70 		 * it. We would rather print the error than clear the message thus indicating
71 		 * that the system is probably in a bad/async state.
72 		 */
73 		if (!(try_count--)) {
74 			ERROR("Could not clear all messages from mailbox FIFO\n");
75 			return -ETIMEDOUT;
76 		}
77 	}
78 
79 	return 0;
80 }
81 
82 int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg)
83 {
84 	uint32_t num_bytes;
85 	void *dst_ptr = (void *)MAILBOX_TX_START_REGION;
86 
87 	assert(msg != NULL);
88 
89 	num_bytes = msg->len;
90 
91 	/*
92 	 * Only a simple check because even if there's 1 pending message
93 	 * we will be in a bad state if we try to send another message
94 	 * due to the absence of any interrupt or buffer mgmt model.
95 	 */
96 	if (mmio_read_32(TI_MAILBOX_TX_BASE + TI_MAILBOX_FIFO_STATUS)) {
97 		ERROR("Mailbox FIFO has pending messages!\n");
98 		return -EINVAL;
99 	}
100 
101 	if (num_bytes > MAILBOX_MAX_MESSAGE_SIZE) {
102 		ERROR("message length %lu > max msg size\n", msg->len);
103 		return -EINVAL;
104 	}
105 
106 	/*
107 	 * Move the buffer contents into the SRAM to be accessed by TIFS
108 	 */
109 	memmove(dst_ptr, msg->buf, num_bytes);
110 
111 	mmio_write_32(TI_MAILBOX_TX_BASE + TI_MAILBOX_MSG, (uint64_t)(void *)dst_ptr);
112 
113 	return 0;
114 }
115 
116 int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg)
117 {
118 	uint32_t num_bytes;
119 	uint64_t rcv_addr;
120 
121 	assert(msg != NULL);
122 
123 	num_bytes = msg->len;
124 
125 	if (ti_mailbox_poll_rx_status() == -ETIMEDOUT) {
126 		ERROR("Timeout waiting for receive\n");
127 		return -ETIMEDOUT;
128 	}
129 
130 	rcv_addr = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG);
131 
132 	/*
133 	 * According to the TI SCI mailbox IPC design, the received message will
134 	 * always lie in the fixed memory buffer region dedicated for IPC.
135 	 * There values are defined in board specific board_def.h
136 	 */
137 	if (rcv_addr < MAILBOX_RX_START_REGION ||
138 	    rcv_addr > (MAILBOX_RX_START_REGION +
139 	    MAILBOX_RX_SLOT_SZ * (MAILBOX_RX_NUM_SLOTS - 1))) {
140 		ERROR("message address %lu is not valid\n", rcv_addr);
141 		return -EFAULT;
142 	}
143 
144 	/* Ensure that the address is aligned as well */
145 	if ((rcv_addr - MAILBOX_RX_START_REGION) % MAILBOX_RX_SLOT_SZ != 0) {
146 		ERROR("message address %lu is not aligned\n", rcv_addr);
147 		return -EINVAL;
148 	}
149 
150 	if (num_bytes > MAILBOX_MAX_MESSAGE_SIZE) {
151 		ERROR("message length %lu > max msg size\n", msg->len);
152 		return -EINVAL;
153 	}
154 
155 	memmove(msg->buf, (uint8_t *)(rcv_addr), num_bytes);
156 
157 	return 0;
158 }
159