1*28c06333SKamlesh Gurudasani /* 2*28c06333SKamlesh Gurudasani * Copyright (c) 2025-2026 Texas Instruments Incorporated - https://www.ti.com 3*28c06333SKamlesh Gurudasani * 4*28c06333SKamlesh Gurudasani * SPDX-License-Identifier: BSD-3-Clause 5*28c06333SKamlesh Gurudasani */ 6*28c06333SKamlesh Gurudasani 7*28c06333SKamlesh Gurudasani /* 8*28c06333SKamlesh Gurudasani * TI PLL Control API Header 9*28c06333SKamlesh Gurudasani * 10*28c06333SKamlesh Gurudasani * This header defines the interface for PLL control driver operations, 11*28c06333SKamlesh Gurudasani * including the read-only PLL control mux driver for monitoring PLL lock 12*28c06333SKamlesh Gurudasani * state and managing PLL bypass/lock-based clock path selection. 13*28c06333SKamlesh Gurudasani */ 14*28c06333SKamlesh Gurudasani 15*28c06333SKamlesh Gurudasani #ifndef TI_CLK_PLLCTRL_H 16*28c06333SKamlesh Gurudasani #define TI_CLK_PLLCTRL_H 17*28c06333SKamlesh Gurudasani 18*28c06333SKamlesh Gurudasani #include <ti_clk_mux.h> 19*28c06333SKamlesh Gurudasani 20*28c06333SKamlesh Gurudasani /* 21*28c06333SKamlesh Gurudasani * Read-only PLL control mux driver 22*28c06333SKamlesh Gurudasani * 23*28c06333SKamlesh Gurudasani * Monitors PLL lock state and provides the current clock path selection 24*28c06333SKamlesh Gurudasani * between bypass and locked modes. Does not support dynamic mux switching, 25*28c06333SKamlesh Gurudasani * only reports the hardware-determined state based on PLL lock status. 26*28c06333SKamlesh Gurudasani */ 27*28c06333SKamlesh Gurudasani extern const struct ti_clk_drv_mux ti_clk_drv_pllctrl_mux_reg_ro; 28*28c06333SKamlesh Gurudasani 29*28c06333SKamlesh Gurudasani #endif /* TI_CLK_PLLCTRL_H */ 30