1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/delay_timer.h> 15 #include <drivers/mmc.h> 16 #include <drivers/synopsys/dw_mmc.h> 17 #include <lib/mmio.h> 18 19 #define DWMMC_CTRL (0x00) 20 #define CTRL_IDMAC_EN (1 << 25) 21 #define CTRL_DMA_EN (1 << 5) 22 #define CTRL_INT_EN (1 << 4) 23 #define CTRL_DMA_RESET (1 << 2) 24 #define CTRL_FIFO_RESET (1 << 1) 25 #define CTRL_RESET (1 << 0) 26 #define CTRL_RESET_ALL (CTRL_DMA_RESET | CTRL_FIFO_RESET | \ 27 CTRL_RESET) 28 29 #define DWMMC_PWREN (0x04) 30 #define DWMMC_CLKDIV (0x08) 31 #define DWMMC_CLKSRC (0x0c) 32 #define DWMMC_CLKENA (0x10) 33 #define DWMMC_TMOUT (0x14) 34 #define DWMMC_CTYPE (0x18) 35 #define CTYPE_8BIT (1 << 16) 36 #define CTYPE_4BIT (1) 37 #define CTYPE_1BIT (0) 38 39 #define DWMMC_BLKSIZ (0x1c) 40 #define DWMMC_BYTCNT (0x20) 41 #define DWMMC_INTMASK (0x24) 42 #define INT_EBE (1 << 15) 43 #define INT_SBE (1 << 13) 44 #define INT_HLE (1 << 12) 45 #define INT_FRUN (1 << 11) 46 #define INT_DRT (1 << 9) 47 #define INT_RTO (1 << 8) 48 #define INT_DCRC (1 << 7) 49 #define INT_RCRC (1 << 6) 50 #define INT_RXDR (1 << 5) 51 #define INT_TXDR (1 << 4) 52 #define INT_DTO (1 << 3) 53 #define INT_CMD_DONE (1 << 2) 54 #define INT_RE (1 << 1) 55 56 #define DWMMC_CMDARG (0x28) 57 #define DWMMC_CMD (0x2c) 58 #define CMD_START (1 << 31) 59 #define CMD_USE_HOLD_REG (1 << 29) /* 0 if SDR50/100 */ 60 #define CMD_UPDATE_CLK_ONLY (1 << 21) 61 #define CMD_SEND_INIT (1 << 15) 62 #define CMD_STOP_ABORT_CMD (1 << 14) 63 #define CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 64 #define CMD_WRITE (1 << 10) 65 #define CMD_DATA_TRANS_EXPECT (1 << 9) 66 #define CMD_CHECK_RESP_CRC (1 << 8) 67 #define CMD_RESP_LEN (1 << 7) 68 #define CMD_RESP_EXPECT (1 << 6) 69 #define CMD(x) (x & 0x3f) 70 71 #define DWMMC_RESP0 (0x30) 72 #define DWMMC_RESP1 (0x34) 73 #define DWMMC_RESP2 (0x38) 74 #define DWMMC_RESP3 (0x3c) 75 #define DWMMC_RINTSTS (0x44) 76 #define DWMMC_STATUS (0x48) 77 #define STATUS_DATA_BUSY (1 << 9) 78 79 #define DWMMC_FIFOTH (0x4c) 80 #define FIFOTH_TWMARK(x) (x & 0xfff) 81 #define FIFOTH_RWMARK(x) ((x & 0x1ff) << 16) 82 #define FIFOTH_DMA_BURST_SIZE(x) ((x & 0x7) << 28) 83 84 #define DWMMC_DEBNCE (0x64) 85 #define DWMMC_BMOD (0x80) 86 #define BMOD_ENABLE (1 << 7) 87 #define BMOD_FB (1 << 1) 88 #define BMOD_SWRESET (1 << 0) 89 90 #define DWMMC_DBADDR (0x88) 91 #define DWMMC_IDSTS (0x8c) 92 #define DWMMC_IDINTEN (0x90) 93 #define DWMMC_CARDTHRCTL (0x100) 94 #define CARDTHRCTL_RD_THR(x) ((x & 0xfff) << 16) 95 #define CARDTHRCTL_RD_THR_EN (1 << 0) 96 97 #define IDMAC_DES0_DIC (1 << 1) 98 #define IDMAC_DES0_LD (1 << 2) 99 #define IDMAC_DES0_FS (1 << 3) 100 #define IDMAC_DES0_CH (1 << 4) 101 #define IDMAC_DES0_ER (1 << 5) 102 #define IDMAC_DES0_CES (1 << 30) 103 #define IDMAC_DES0_OWN (1 << 31) 104 #define IDMAC_DES1_BS1(x) ((x) & 0x1fff) 105 #define IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) 106 107 #define DWMMC_DMA_MAX_BUFFER_SIZE (512 * 8) 108 109 #define DWMMC_8BIT_MODE (1 << 6) 110 111 #define DWMMC_ADDRESS_MASK U(0x0f) 112 113 #define TIMEOUT 100000 114 115 struct dw_idmac_desc { 116 unsigned int des0; 117 unsigned int des1; 118 unsigned int des2; 119 unsigned int des3; 120 }; 121 122 static void dw_init(void); 123 static int dw_send_cmd(struct mmc_cmd *cmd); 124 static int dw_set_ios(unsigned int clk, unsigned int width); 125 static int dw_prepare(int lba, uintptr_t buf, size_t size); 126 static int dw_read(int lba, uintptr_t buf, size_t size); 127 static int dw_write(int lba, uintptr_t buf, size_t size); 128 129 static const struct mmc_ops dw_mmc_ops = { 130 .init = dw_init, 131 .send_cmd = dw_send_cmd, 132 .set_ios = dw_set_ios, 133 .prepare = dw_prepare, 134 .read = dw_read, 135 .write = dw_write, 136 }; 137 138 static dw_mmc_params_t dw_params; 139 140 static void dw_update_clk(void) 141 { 142 unsigned int data; 143 144 mmio_write_32(dw_params.reg_base + DWMMC_CMD, 145 CMD_WAIT_PRVDATA_COMPLETE | CMD_UPDATE_CLK_ONLY | 146 CMD_START); 147 while (1) { 148 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); 149 if ((data & CMD_START) == 0) 150 break; 151 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); 152 assert((data & INT_HLE) == 0); 153 } 154 } 155 156 static void dw_set_clk(int clk) 157 { 158 unsigned int data; 159 int div; 160 161 assert(clk > 0); 162 163 for (div = 1; div < 256; div++) { 164 if ((dw_params.clk_rate / (2 * div)) <= clk) { 165 break; 166 } 167 } 168 assert(div < 256); 169 170 /* wait until controller is idle */ 171 do { 172 data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS); 173 } while (data & STATUS_DATA_BUSY); 174 175 /* disable clock before change clock rate */ 176 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); 177 dw_update_clk(); 178 179 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); 180 dw_update_clk(); 181 182 /* enable clock */ 183 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); 184 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); 185 dw_update_clk(); 186 } 187 188 static void dw_init(void) 189 { 190 unsigned int data; 191 uintptr_t base; 192 193 assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0); 194 195 base = dw_params.reg_base; 196 mmio_write_32(base + DWMMC_PWREN, 1); 197 mmio_write_32(base + DWMMC_CTRL, CTRL_RESET_ALL); 198 do { 199 data = mmio_read_32(base + DWMMC_CTRL); 200 } while (data); 201 202 /* enable DMA in CTRL */ 203 data = CTRL_INT_EN | CTRL_DMA_EN | CTRL_IDMAC_EN; 204 mmio_write_32(base + DWMMC_CTRL, data); 205 mmio_write_32(base + DWMMC_RINTSTS, ~0); 206 mmio_write_32(base + DWMMC_INTMASK, 0); 207 mmio_write_32(base + DWMMC_TMOUT, ~0); 208 mmio_write_32(base + DWMMC_IDINTEN, ~0); 209 mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE); 210 mmio_write_32(base + DWMMC_BYTCNT, 256 * 1024); 211 mmio_write_32(base + DWMMC_DEBNCE, 0x00ffffff); 212 mmio_write_32(base + DWMMC_BMOD, BMOD_SWRESET); 213 do { 214 data = mmio_read_32(base + DWMMC_BMOD); 215 } while (data & BMOD_SWRESET); 216 /* enable DMA in BMOD */ 217 data |= BMOD_ENABLE | BMOD_FB; 218 mmio_write_32(base + DWMMC_BMOD, data); 219 220 udelay(100); 221 dw_set_clk(MMC_BOOT_CLK_RATE); 222 udelay(100); 223 } 224 225 static int dw_send_cmd(struct mmc_cmd *cmd) 226 { 227 unsigned int op, data, err_mask; 228 uintptr_t base; 229 int timeout; 230 231 assert(cmd); 232 233 base = dw_params.reg_base; 234 235 switch (cmd->cmd_idx) { 236 case 0: 237 op = CMD_SEND_INIT; 238 break; 239 case 12: 240 op = CMD_STOP_ABORT_CMD; 241 break; 242 case 13: 243 op = CMD_WAIT_PRVDATA_COMPLETE; 244 break; 245 case 8: 246 if (dw_params.mmc_dev_type == MMC_IS_EMMC) 247 op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE; 248 else 249 op = CMD_WAIT_PRVDATA_COMPLETE; 250 break; 251 case 17: 252 case 18: 253 op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE; 254 break; 255 case 24: 256 case 25: 257 op = CMD_WRITE | CMD_DATA_TRANS_EXPECT | 258 CMD_WAIT_PRVDATA_COMPLETE; 259 break; 260 case 51: 261 op = CMD_DATA_TRANS_EXPECT; 262 break; 263 default: 264 op = 0; 265 break; 266 } 267 op |= CMD_USE_HOLD_REG | CMD_START; 268 switch (cmd->resp_type) { 269 case 0: 270 break; 271 case MMC_RESPONSE_R2: 272 op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC | 273 CMD_RESP_LEN; 274 break; 275 case MMC_RESPONSE_R3: 276 op |= CMD_RESP_EXPECT; 277 break; 278 default: 279 op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC; 280 break; 281 } 282 timeout = TIMEOUT; 283 do { 284 data = mmio_read_32(base + DWMMC_STATUS); 285 if (--timeout <= 0) 286 panic(); 287 } while (data & STATUS_DATA_BUSY); 288 289 mmio_write_32(base + DWMMC_RINTSTS, ~0); 290 mmio_write_32(base + DWMMC_CMDARG, cmd->cmd_arg); 291 mmio_write_32(base + DWMMC_CMD, op | cmd->cmd_idx); 292 293 err_mask = INT_EBE | INT_HLE | INT_RTO | INT_RCRC | INT_RE | 294 INT_DCRC | INT_DRT | INT_SBE; 295 timeout = TIMEOUT; 296 do { 297 udelay(500); 298 data = mmio_read_32(base + DWMMC_RINTSTS); 299 300 if (data & err_mask) 301 return -EIO; 302 if (data & INT_DTO) 303 break; 304 if (--timeout == 0) { 305 ERROR("%s, RINTSTS:0x%x\n", __func__, data); 306 panic(); 307 } 308 } while (!(data & INT_CMD_DONE)); 309 310 if (op & CMD_RESP_EXPECT) { 311 cmd->resp_data[0] = mmio_read_32(base + DWMMC_RESP0); 312 if (op & CMD_RESP_LEN) { 313 cmd->resp_data[1] = mmio_read_32(base + DWMMC_RESP1); 314 cmd->resp_data[2] = mmio_read_32(base + DWMMC_RESP2); 315 cmd->resp_data[3] = mmio_read_32(base + DWMMC_RESP3); 316 } 317 } 318 return 0; 319 } 320 321 static int dw_set_ios(unsigned int clk, unsigned int width) 322 { 323 switch (width) { 324 case MMC_BUS_WIDTH_1: 325 mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_1BIT); 326 break; 327 case MMC_BUS_WIDTH_4: 328 mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_4BIT); 329 break; 330 case MMC_BUS_WIDTH_8: 331 mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_8BIT); 332 break; 333 default: 334 assert(0); 335 break; 336 } 337 dw_set_clk(clk); 338 return 0; 339 } 340 341 static int dw_prepare(int lba, uintptr_t buf, size_t size) 342 { 343 struct dw_idmac_desc *desc; 344 int desc_cnt, i, last; 345 uintptr_t base; 346 347 assert(((buf & DWMMC_ADDRESS_MASK) == 0) && 348 (dw_params.desc_size > 0) && 349 ((dw_params.reg_base & MMC_BLOCK_MASK) == 0) && 350 ((dw_params.desc_base & MMC_BLOCK_MASK) == 0) && 351 ((dw_params.desc_size & MMC_BLOCK_MASK) == 0)); 352 353 flush_dcache_range(buf, size); 354 355 desc_cnt = (size + DWMMC_DMA_MAX_BUFFER_SIZE - 1) / 356 DWMMC_DMA_MAX_BUFFER_SIZE; 357 assert(desc_cnt * sizeof(struct dw_idmac_desc) < dw_params.desc_size); 358 359 base = dw_params.reg_base; 360 desc = (struct dw_idmac_desc *)dw_params.desc_base; 361 mmio_write_32(base + DWMMC_BYTCNT, size); 362 363 if (size < MMC_BLOCK_SIZE) 364 mmio_write_32(base + DWMMC_BLKSIZ, size); 365 else 366 mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE); 367 368 mmio_write_32(base + DWMMC_RINTSTS, ~0); 369 for (i = 0; i < desc_cnt; i++) { 370 desc[i].des0 = IDMAC_DES0_OWN | IDMAC_DES0_CH | IDMAC_DES0_DIC; 371 desc[i].des1 = IDMAC_DES1_BS1(DWMMC_DMA_MAX_BUFFER_SIZE); 372 desc[i].des2 = buf + DWMMC_DMA_MAX_BUFFER_SIZE * i; 373 desc[i].des3 = dw_params.desc_base + 374 (sizeof(struct dw_idmac_desc)) * (i + 1); 375 } 376 /* first descriptor */ 377 desc->des0 |= IDMAC_DES0_FS; 378 /* last descriptor */ 379 last = desc_cnt - 1; 380 (desc + last)->des0 |= IDMAC_DES0_LD; 381 (desc + last)->des0 &= ~(IDMAC_DES0_DIC | IDMAC_DES0_CH); 382 (desc + last)->des1 = IDMAC_DES1_BS1(size - (last * 383 DWMMC_DMA_MAX_BUFFER_SIZE)); 384 /* set next descriptor address as 0 */ 385 (desc + last)->des3 = 0; 386 387 mmio_write_32(base + DWMMC_DBADDR, dw_params.desc_base); 388 flush_dcache_range(dw_params.desc_base, 389 desc_cnt * DWMMC_DMA_MAX_BUFFER_SIZE); 390 391 392 return 0; 393 } 394 395 static int dw_read(int lba, uintptr_t buf, size_t size) 396 { 397 uint32_t data = 0; 398 int timeout = TIMEOUT; 399 400 do { 401 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); 402 udelay(50); 403 } while (!(data & INT_DTO) && timeout-- > 0); 404 405 inv_dcache_range(buf, size); 406 407 return 0; 408 } 409 410 static int dw_write(int lba, uintptr_t buf, size_t size) 411 { 412 return 0; 413 } 414 415 void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info) 416 { 417 assert((params != 0) && 418 ((params->reg_base & MMC_BLOCK_MASK) == 0) && 419 ((params->desc_base & MMC_BLOCK_MASK) == 0) && 420 ((params->desc_size & MMC_BLOCK_MASK) == 0) && 421 (params->desc_size > 0) && 422 (params->clk_rate > 0) && 423 ((params->bus_width == MMC_BUS_WIDTH_1) || 424 (params->bus_width == MMC_BUS_WIDTH_4) || 425 (params->bus_width == MMC_BUS_WIDTH_8))); 426 427 memcpy(&dw_params, params, sizeof(dw_mmc_params_t)); 428 mmio_write_32(dw_params.reg_base + DWMMC_FIFOTH, 0x103ff); 429 dw_params.mmc_dev_type = info->mmc_dev_type; 430 mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width, 431 params->flags, info); 432 } 433