xref: /rk3399_ARM-atf/drivers/st/reset/stm32mp1_reset.c (revision 7839a050909944bd3ee6a70245a2bcc5471b3507)
1*7839a050SYann Gautier /*
2*7839a050SYann Gautier  * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
3*7839a050SYann Gautier  *
4*7839a050SYann Gautier  * SPDX-License-Identifier: BSD-3-Clause
5*7839a050SYann Gautier  */
6*7839a050SYann Gautier 
7*7839a050SYann Gautier #include <bl_common.h>
8*7839a050SYann Gautier #include <debug.h>
9*7839a050SYann Gautier #include <limits.h>
10*7839a050SYann Gautier #include <mmio.h>
11*7839a050SYann Gautier #include <platform_def.h>
12*7839a050SYann Gautier #include <stm32mp1_rcc.h>
13*7839a050SYann Gautier #include <stm32mp1_reset.h>
14*7839a050SYann Gautier #include <utils_def.h>
15*7839a050SYann Gautier 
16*7839a050SYann Gautier #define RST_CLR_OFFSET	4U
17*7839a050SYann Gautier 
18*7839a050SYann Gautier void stm32mp1_reset_assert(uint32_t id)
19*7839a050SYann Gautier {
20*7839a050SYann Gautier 	uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
21*7839a050SYann Gautier 	uint32_t bit = id % (uint32_t)__LONG_BIT;
22*7839a050SYann Gautier 
23*7839a050SYann Gautier 	mmio_write_32(RCC_BASE + offset, BIT(bit));
24*7839a050SYann Gautier 	while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) == 0U) {
25*7839a050SYann Gautier 		;
26*7839a050SYann Gautier 	}
27*7839a050SYann Gautier }
28*7839a050SYann Gautier 
29*7839a050SYann Gautier void stm32mp1_reset_deassert(uint32_t id)
30*7839a050SYann Gautier {
31*7839a050SYann Gautier 	uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
32*7839a050SYann Gautier 			  RST_CLR_OFFSET;
33*7839a050SYann Gautier 	uint32_t bit = id % (uint32_t)__LONG_BIT;
34*7839a050SYann Gautier 
35*7839a050SYann Gautier 	mmio_write_32(RCC_BASE + offset, BIT(bit));
36*7839a050SYann Gautier 	while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) != 0U) {
37*7839a050SYann Gautier 		;
38*7839a050SYann Gautier 	}
39*7839a050SYann Gautier }
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