1 /* 2 * Copyright (c) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/delay_timer.h> 15 #include <drivers/mmc.h> 16 #include <drivers/st/stm32_sdmmc2.h> 17 #include <drivers/st/stm32mp1_clk.h> 18 #include <drivers/st/stm32mp1_rcc.h> 19 #include <drivers/st/stm32mp1_reset.h> 20 #include <dt-bindings/clock/stm32mp1-clks.h> 21 #include <dt-bindings/reset/stm32mp1-resets.h> 22 #include <libfdt.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 27 #include <stm32mp1_dt.h> 28 29 /* Registers offsets */ 30 #define SDMMC_POWER 0x00U 31 #define SDMMC_CLKCR 0x04U 32 #define SDMMC_ARGR 0x08U 33 #define SDMMC_CMDR 0x0CU 34 #define SDMMC_RESPCMDR 0x10U 35 #define SDMMC_RESP1R 0x14U 36 #define SDMMC_RESP2R 0x18U 37 #define SDMMC_RESP3R 0x1CU 38 #define SDMMC_RESP4R 0x20U 39 #define SDMMC_DTIMER 0x24U 40 #define SDMMC_DLENR 0x28U 41 #define SDMMC_DCTRLR 0x2CU 42 #define SDMMC_DCNTR 0x30U 43 #define SDMMC_STAR 0x34U 44 #define SDMMC_ICR 0x38U 45 #define SDMMC_MASKR 0x3CU 46 #define SDMMC_ACKTIMER 0x40U 47 #define SDMMC_IDMACTRLR 0x50U 48 #define SDMMC_IDMABSIZER 0x54U 49 #define SDMMC_IDMABASE0R 0x58U 50 #define SDMMC_IDMABASE1R 0x5CU 51 #define SDMMC_FIFOR 0x80U 52 53 /* SDMMC power control register */ 54 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 55 #define SDMMC_POWER_DIRPOL BIT(4) 56 57 /* SDMMC clock control register */ 58 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 59 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 60 #define SDMMC_CLKCR_NEGEDGE BIT(16) 61 #define SDMMC_CLKCR_HWFC_EN BIT(17) 62 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 63 64 /* SDMMC command register */ 65 #define SDMMC_CMDR_CMDTRANS BIT(6) 66 #define SDMMC_CMDR_CMDSTOP BIT(7) 67 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 68 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 69 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 70 #define SDMMC_CMDR_CPSMEN BIT(12) 71 72 /* SDMMC data control register */ 73 #define SDMMC_DCTRLR_DTEN BIT(0) 74 #define SDMMC_DCTRLR_DTDIR BIT(1) 75 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4) 77 #define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5) 78 #define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7) 79 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 80 #define SDMMC_DCTRLR_FIFORST BIT(13) 81 82 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 83 SDMMC_DCTRLR_DTDIR | \ 84 SDMMC_DCTRLR_DTMODE | \ 85 SDMMC_DCTRLR_DBLOCKSIZE) 86 #define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 87 SDMMC_DCTRLR_DBLOCKSIZE_1) 88 #define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 89 SDMMC_DCTRLR_DBLOCKSIZE_3) 90 91 /* SDMMC status register */ 92 #define SDMMC_STAR_CCRCFAIL BIT(0) 93 #define SDMMC_STAR_DCRCFAIL BIT(1) 94 #define SDMMC_STAR_CTIMEOUT BIT(2) 95 #define SDMMC_STAR_DTIMEOUT BIT(3) 96 #define SDMMC_STAR_TXUNDERR BIT(4) 97 #define SDMMC_STAR_RXOVERR BIT(5) 98 #define SDMMC_STAR_CMDREND BIT(6) 99 #define SDMMC_STAR_CMDSENT BIT(7) 100 #define SDMMC_STAR_DATAEND BIT(8) 101 #define SDMMC_STAR_DBCKEND BIT(10) 102 #define SDMMC_STAR_DPSMACT BIT(12) 103 #define SDMMC_STAR_RXFIFOHF BIT(15) 104 #define SDMMC_STAR_RXFIFOE BIT(19) 105 #define SDMMC_STAR_IDMATE BIT(27) 106 #define SDMMC_STAR_IDMABTC BIT(28) 107 108 /* SDMMC DMA control register */ 109 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 110 111 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 112 SDMMC_STAR_DCRCFAIL | \ 113 SDMMC_STAR_CTIMEOUT | \ 114 SDMMC_STAR_DTIMEOUT | \ 115 SDMMC_STAR_TXUNDERR | \ 116 SDMMC_STAR_RXOVERR | \ 117 SDMMC_STAR_CMDREND | \ 118 SDMMC_STAR_CMDSENT | \ 119 SDMMC_STAR_DATAEND | \ 120 SDMMC_STAR_DBCKEND | \ 121 SDMMC_STAR_IDMATE | \ 122 SDMMC_STAR_IDMABTC) 123 124 #define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U) 125 #define TIMEOUT_1_S plat_get_syscnt_freq2() 126 127 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 128 129 static void stm32_sdmmc2_init(void); 130 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 131 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 132 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 133 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 134 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 135 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 136 137 static const struct mmc_ops stm32_sdmmc2_ops = { 138 .init = stm32_sdmmc2_init, 139 .send_cmd = stm32_sdmmc2_send_cmd, 140 .set_ios = stm32_sdmmc2_set_ios, 141 .prepare = stm32_sdmmc2_prepare, 142 .read = stm32_sdmmc2_read, 143 .write = stm32_sdmmc2_write, 144 }; 145 146 static struct stm32_sdmmc2_params sdmmc2_params; 147 148 #pragma weak plat_sdmmc2_use_dma 149 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 150 { 151 return false; 152 } 153 154 static void stm32_sdmmc2_init(void) 155 { 156 uint32_t clock_div; 157 uintptr_t base = sdmmc2_params.reg_base; 158 159 clock_div = div_round_up(sdmmc2_params.clk_rate, 160 STM32MP1_MMC_INIT_FREQ * 2); 161 162 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 163 sdmmc2_params.negedge | 164 sdmmc2_params.pin_ckin); 165 166 mmio_write_32(base + SDMMC_POWER, 167 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 168 169 mdelay(1); 170 } 171 172 static int stm32_sdmmc2_stop_transfer(void) 173 { 174 struct mmc_cmd cmd_stop; 175 176 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 177 178 cmd_stop.cmd_idx = MMC_CMD(12); 179 cmd_stop.resp_type = MMC_RESPONSE_R1B; 180 181 return stm32_sdmmc2_send_cmd(&cmd_stop); 182 } 183 184 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 185 { 186 uint32_t flags_cmd, status; 187 uint32_t flags_data = 0; 188 int err = 0; 189 uintptr_t base = sdmmc2_params.reg_base; 190 unsigned int cmd_reg, arg_reg, start; 191 192 if (cmd == NULL) { 193 return -EINVAL; 194 } 195 196 flags_cmd = SDMMC_STAR_CTIMEOUT; 197 arg_reg = cmd->cmd_arg; 198 199 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 200 mmio_write_32(base + SDMMC_CMDR, 0); 201 } 202 203 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 204 205 if (cmd->resp_type == 0U) { 206 flags_cmd |= SDMMC_STAR_CMDSENT; 207 } 208 209 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 210 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 211 flags_cmd |= SDMMC_STAR_CMDREND; 212 cmd_reg |= SDMMC_CMDR_WAITRESP; 213 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 214 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 215 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 216 } else { 217 flags_cmd |= SDMMC_STAR_CMDREND; 218 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 219 } 220 } 221 222 switch (cmd->cmd_idx) { 223 case MMC_CMD(1): 224 arg_reg |= OCR_POWERUP; 225 break; 226 case MMC_CMD(8): 227 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 228 cmd_reg |= SDMMC_CMDR_CMDTRANS; 229 } 230 break; 231 case MMC_CMD(12): 232 cmd_reg |= SDMMC_CMDR_CMDSTOP; 233 break; 234 case MMC_CMD(17): 235 case MMC_CMD(18): 236 cmd_reg |= SDMMC_CMDR_CMDTRANS; 237 if (sdmmc2_params.use_dma) { 238 flags_data |= SDMMC_STAR_DCRCFAIL | 239 SDMMC_STAR_DTIMEOUT | 240 SDMMC_STAR_DATAEND | 241 SDMMC_STAR_RXOVERR | 242 SDMMC_STAR_IDMATE; 243 } 244 break; 245 case MMC_ACMD(41): 246 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 247 break; 248 case MMC_ACMD(51): 249 cmd_reg |= SDMMC_CMDR_CMDTRANS; 250 if (sdmmc2_params.use_dma) { 251 flags_data |= SDMMC_STAR_DCRCFAIL | 252 SDMMC_STAR_DTIMEOUT | 253 SDMMC_STAR_DATAEND | 254 SDMMC_STAR_RXOVERR | 255 SDMMC_STAR_IDMATE | 256 SDMMC_STAR_DBCKEND; 257 } 258 break; 259 default: 260 break; 261 } 262 263 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 264 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 265 } 266 267 mmio_write_32(base + SDMMC_ARGR, arg_reg); 268 269 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 270 271 status = mmio_read_32(base + SDMMC_STAR); 272 273 start = get_timer(0); 274 275 while ((status & flags_cmd) == 0U) { 276 if (get_timer(start) > TIMEOUT_10_MS) { 277 err = -ETIMEDOUT; 278 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 279 __func__, cmd->cmd_idx, status); 280 goto err_exit; 281 } 282 283 status = mmio_read_32(base + SDMMC_STAR); 284 } 285 286 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 287 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 288 err = -ETIMEDOUT; 289 /* 290 * Those timeouts can occur, and framework will handle 291 * the retries. CMD8 is expected to return this timeout 292 * for eMMC 293 */ 294 if (!((cmd->cmd_idx == MMC_CMD(1)) || 295 (cmd->cmd_idx == MMC_CMD(13)) || 296 ((cmd->cmd_idx == MMC_CMD(8)) && 297 (cmd->resp_type == MMC_RESPONSE_R7)))) { 298 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 299 __func__, cmd->cmd_idx, status); 300 } 301 } else { 302 err = -EIO; 303 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 304 __func__, cmd->cmd_idx, status); 305 } 306 307 goto err_exit; 308 } 309 310 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 311 if ((cmd->cmd_idx == MMC_CMD(9)) && 312 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 313 /* Need to invert response to match CSD structure */ 314 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 315 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 316 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 317 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 318 } else { 319 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 320 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 321 SDMMC_CMDR_WAITRESP) { 322 cmd->resp_data[1] = mmio_read_32(base + 323 SDMMC_RESP2R); 324 cmd->resp_data[2] = mmio_read_32(base + 325 SDMMC_RESP3R); 326 cmd->resp_data[3] = mmio_read_32(base + 327 SDMMC_RESP4R); 328 } 329 } 330 } 331 332 if (flags_data == 0U) { 333 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 334 335 return 0; 336 } 337 338 status = mmio_read_32(base + SDMMC_STAR); 339 340 start = get_timer(0); 341 342 while ((status & flags_data) == 0U) { 343 if (get_timer(start) > TIMEOUT_10_MS) { 344 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 345 __func__, cmd->cmd_idx, status); 346 err = -ETIMEDOUT; 347 goto err_exit; 348 } 349 350 status = mmio_read_32(base + SDMMC_STAR); 351 }; 352 353 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 354 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 355 SDMMC_STAR_IDMATE)) != 0U) { 356 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 357 cmd->cmd_idx, status); 358 err = -EIO; 359 } 360 361 err_exit: 362 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 363 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 364 365 if (err != 0) { 366 int ret_stop = stm32_sdmmc2_stop_transfer(); 367 368 if (ret_stop != 0) { 369 return ret_stop; 370 } 371 } 372 373 return err; 374 } 375 376 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 377 { 378 int8_t retry; 379 int err = 0; 380 381 assert(cmd != NULL); 382 383 for (retry = 0; retry <= 3; retry++) { 384 err = stm32_sdmmc2_send_cmd_req(cmd); 385 if (err == 0) { 386 return err; 387 } 388 389 if ((cmd->cmd_idx == MMC_CMD(1)) || 390 (cmd->cmd_idx == MMC_CMD(13))) { 391 return 0; /* Retry managed by framework */ 392 } 393 394 /* Command 8 is expected to fail for eMMC */ 395 if (!(cmd->cmd_idx == MMC_CMD(8))) { 396 WARN(" CMD%d, Retry: %d, Error: %d\n", 397 cmd->cmd_idx, retry, err); 398 } 399 400 udelay(10); 401 } 402 403 return err; 404 } 405 406 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 407 { 408 uintptr_t base = sdmmc2_params.reg_base; 409 uint32_t bus_cfg = 0; 410 uint32_t clock_div, max_freq; 411 uint32_t clk_rate = sdmmc2_params.clk_rate; 412 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 413 414 switch (width) { 415 case MMC_BUS_WIDTH_1: 416 break; 417 case MMC_BUS_WIDTH_4: 418 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 419 break; 420 case MMC_BUS_WIDTH_8: 421 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 422 break; 423 default: 424 panic(); 425 break; 426 } 427 428 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 429 if (max_bus_freq >= 52000000U) { 430 max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ; 431 } else { 432 max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ; 433 } 434 } else { 435 if (max_bus_freq >= 50000000U) { 436 max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ; 437 } else { 438 max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ; 439 } 440 } 441 442 clock_div = div_round_up(clk_rate, max_freq * 2); 443 444 mmio_write_32(base + SDMMC_CLKCR, 445 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 446 sdmmc2_params.negedge | 447 sdmmc2_params.pin_ckin); 448 449 return 0; 450 } 451 452 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 453 { 454 struct mmc_cmd cmd; 455 int ret; 456 uintptr_t base = sdmmc2_params.reg_base; 457 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 458 459 if (size == 8U) { 460 data_ctrl |= SDMMC_DBLOCKSIZE_8; 461 } else { 462 data_ctrl |= SDMMC_DBLOCKSIZE_512; 463 } 464 465 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 466 467 if (sdmmc2_params.use_dma) { 468 inv_dcache_range(buf, size); 469 } 470 471 /* Prepare CMD 16*/ 472 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 473 474 mmio_write_32(base + SDMMC_DLENR, 0); 475 476 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 477 SDMMC_DCTRLR_CLEAR_MASK, SDMMC_DCTRLR_DTDIR); 478 479 zeromem(&cmd, sizeof(struct mmc_cmd)); 480 481 cmd.cmd_idx = MMC_CMD(16); 482 if (size > MMC_BLOCK_SIZE) { 483 cmd.cmd_arg = MMC_BLOCK_SIZE; 484 } else { 485 cmd.cmd_arg = size; 486 } 487 488 cmd.resp_type = MMC_RESPONSE_R1; 489 490 ret = stm32_sdmmc2_send_cmd(&cmd); 491 if (ret != 0) { 492 ERROR("CMD16 failed\n"); 493 return ret; 494 } 495 496 /* Prepare data command */ 497 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 498 499 mmio_write_32(base + SDMMC_DLENR, size); 500 501 if (sdmmc2_params.use_dma) { 502 mmio_write_32(base + SDMMC_IDMACTRLR, 503 SDMMC_IDMACTRLR_IDMAEN); 504 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 505 506 flush_dcache_range(buf, size); 507 } 508 509 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 510 SDMMC_DCTRLR_CLEAR_MASK, 511 data_ctrl); 512 513 return 0; 514 } 515 516 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 517 { 518 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 519 SDMMC_STAR_DTIMEOUT; 520 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 521 uint32_t status; 522 uint32_t *buffer; 523 uintptr_t base = sdmmc2_params.reg_base; 524 uintptr_t fifo_reg = base + SDMMC_FIFOR; 525 unsigned int start; 526 int ret; 527 528 /* Assert buf is 4 bytes aligned */ 529 assert((buf & GENMASK(1, 0)) == 0U); 530 531 buffer = (uint32_t *)buf; 532 533 if (sdmmc2_params.use_dma) { 534 inv_dcache_range(buf, size); 535 536 return 0; 537 } 538 539 if (size <= MMC_BLOCK_SIZE) { 540 flags |= SDMMC_STAR_DBCKEND; 541 } 542 543 start = get_timer(0); 544 545 do { 546 status = mmio_read_32(base + SDMMC_STAR); 547 548 if ((status & error_flags) != 0U) { 549 ERROR("%s: Read error (status = %x)\n", __func__, 550 status); 551 mmio_write_32(base + SDMMC_DCTRLR, 552 SDMMC_DCTRLR_FIFORST); 553 554 mmio_write_32(base + SDMMC_ICR, 555 SDMMC_STATIC_FLAGS); 556 557 ret = stm32_sdmmc2_stop_transfer(); 558 if (ret != 0) { 559 return ret; 560 } 561 562 return -EIO; 563 } 564 565 if (get_timer(start) > TIMEOUT_1_S) { 566 ERROR("%s: timeout 1s (status = %x)\n", 567 __func__, status); 568 mmio_write_32(base + SDMMC_ICR, 569 SDMMC_STATIC_FLAGS); 570 571 ret = stm32_sdmmc2_stop_transfer(); 572 if (ret != 0) { 573 return ret; 574 } 575 576 return -ETIMEDOUT; 577 } 578 579 if (size < (8U * sizeof(uint32_t))) { 580 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 581 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 582 *buffer = mmio_read_32(fifo_reg); 583 buffer++; 584 } 585 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 586 uint32_t count; 587 588 /* Read data from SDMMC Rx FIFO */ 589 for (count = 0; count < 8U; count++) { 590 *buffer = mmio_read_32(fifo_reg); 591 buffer++; 592 } 593 } 594 } while ((status & flags) == 0U); 595 596 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 597 598 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 599 WARN("%s: DPSMACT=1, send stop\n", __func__); 600 return stm32_sdmmc2_stop_transfer(); 601 } 602 603 return 0; 604 } 605 606 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 607 { 608 return 0; 609 } 610 611 static int stm32_sdmmc2_dt_get_config(void) 612 { 613 int sdmmc_node; 614 void *fdt = NULL; 615 const fdt32_t *cuint; 616 617 if (fdt_get_address(&fdt) == 0) { 618 return -FDT_ERR_NOTFOUND; 619 } 620 621 if (fdt == NULL) { 622 return -FDT_ERR_NOTFOUND; 623 } 624 625 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 626 627 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 628 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 629 if (cuint == NULL) { 630 continue; 631 } 632 633 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 634 break; 635 } 636 637 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 638 DT_SDMMC2_COMPAT); 639 } 640 641 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 642 return -FDT_ERR_NOTFOUND; 643 } 644 645 if (fdt_check_status(sdmmc_node) == 0) { 646 return -FDT_ERR_NOTFOUND; 647 } 648 649 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 650 return -FDT_ERR_BADVALUE; 651 } 652 653 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 654 if (cuint == NULL) { 655 return -FDT_ERR_NOTFOUND; 656 } 657 658 cuint++; 659 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 660 661 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 662 if (cuint == NULL) { 663 return -FDT_ERR_NOTFOUND; 664 } 665 666 cuint++; 667 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 668 669 if ((fdt_getprop(fdt, sdmmc_node, "st,pin-ckin", NULL)) != NULL) { 670 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 671 } 672 673 if ((fdt_getprop(fdt, sdmmc_node, "st,dirpol", NULL)) != NULL) { 674 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 675 } 676 677 if ((fdt_getprop(fdt, sdmmc_node, "st,negedge", NULL)) != NULL) { 678 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 679 } 680 681 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 682 if (cuint != NULL) { 683 switch (fdt32_to_cpu(*cuint)) { 684 case 4: 685 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 686 break; 687 688 case 8: 689 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 690 break; 691 692 default: 693 break; 694 } 695 } 696 697 return 0; 698 } 699 700 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 701 { 702 return sdmmc2_params.device_info->device_size; 703 } 704 705 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 706 { 707 int ret; 708 709 assert((params != NULL) && 710 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 711 ((params->bus_width == MMC_BUS_WIDTH_1) || 712 (params->bus_width == MMC_BUS_WIDTH_4) || 713 (params->bus_width == MMC_BUS_WIDTH_8))); 714 715 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 716 717 if (stm32_sdmmc2_dt_get_config() != 0) { 718 ERROR("%s: DT error\n", __func__); 719 return -ENOMEM; 720 } 721 722 ret = stm32mp1_clk_enable(sdmmc2_params.clock_id); 723 if (ret != 0) { 724 ERROR("%s: clock %d failed\n", __func__, 725 sdmmc2_params.clock_id); 726 return ret; 727 } 728 729 stm32mp1_reset_assert(sdmmc2_params.reset_id); 730 udelay(2); 731 stm32mp1_reset_deassert(sdmmc2_params.reset_id); 732 mdelay(1); 733 734 sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id); 735 736 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 737 sdmmc2_params.bus_width, sdmmc2_params.flags, 738 sdmmc2_params.device_info); 739 } 740