1 /* 2 * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_sdmmc2.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 /* Power cycle delays in ms */ 122 #define VCC_POWER_OFF_DELAY 2 123 #define VCC_POWER_ON_DELAY 2 124 #define POWER_CYCLE_DELAY 2 125 #define POWER_OFF_DELAY 2 126 #define POWER_ON_DELAY 1 127 128 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 129 130 static void stm32_sdmmc2_init(void); 131 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 132 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 133 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 134 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 135 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 136 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 137 138 static const struct mmc_ops stm32_sdmmc2_ops = { 139 .init = stm32_sdmmc2_init, 140 .send_cmd = stm32_sdmmc2_send_cmd, 141 .set_ios = stm32_sdmmc2_set_ios, 142 .prepare = stm32_sdmmc2_prepare, 143 .read = stm32_sdmmc2_read, 144 .write = stm32_sdmmc2_write, 145 }; 146 147 static struct stm32_sdmmc2_params sdmmc2_params; 148 149 #pragma weak plat_sdmmc2_use_dma 150 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 151 { 152 return false; 153 } 154 155 static void stm32_sdmmc2_init(void) 156 { 157 uint32_t clock_div; 158 uint32_t freq = STM32MP_MMC_INIT_FREQ; 159 uintptr_t base = sdmmc2_params.reg_base; 160 161 if (sdmmc2_params.max_freq != 0U) { 162 freq = MIN(sdmmc2_params.max_freq, freq); 163 } 164 165 if (sdmmc2_params.vmmc_regu != NULL) { 166 regulator_disable(sdmmc2_params.vmmc_regu); 167 } 168 169 mdelay(VCC_POWER_OFF_DELAY); 170 171 mmio_write_32(base + SDMMC_POWER, 172 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); 173 mdelay(POWER_CYCLE_DELAY); 174 175 if (sdmmc2_params.vmmc_regu != NULL) { 176 regulator_enable(sdmmc2_params.vmmc_regu); 177 } 178 179 mdelay(VCC_POWER_ON_DELAY); 180 181 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); 182 mdelay(POWER_OFF_DELAY); 183 184 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 185 186 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 187 sdmmc2_params.negedge | 188 sdmmc2_params.pin_ckin); 189 190 mmio_write_32(base + SDMMC_POWER, 191 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 192 193 mdelay(POWER_ON_DELAY); 194 } 195 196 static int stm32_sdmmc2_stop_transfer(void) 197 { 198 struct mmc_cmd cmd_stop; 199 200 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 201 202 cmd_stop.cmd_idx = MMC_CMD(12); 203 cmd_stop.resp_type = MMC_RESPONSE_R1B; 204 205 return stm32_sdmmc2_send_cmd(&cmd_stop); 206 } 207 208 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 209 { 210 uint64_t timeout; 211 uint32_t flags_cmd, status; 212 uint32_t flags_data = 0; 213 int err = 0; 214 uintptr_t base = sdmmc2_params.reg_base; 215 unsigned int cmd_reg, arg_reg; 216 217 if (cmd == NULL) { 218 return -EINVAL; 219 } 220 221 flags_cmd = SDMMC_STAR_CTIMEOUT; 222 arg_reg = cmd->cmd_arg; 223 224 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 225 mmio_write_32(base + SDMMC_CMDR, 0); 226 } 227 228 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 229 230 if (cmd->resp_type == 0U) { 231 flags_cmd |= SDMMC_STAR_CMDSENT; 232 } 233 234 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 235 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 236 flags_cmd |= SDMMC_STAR_CMDREND; 237 cmd_reg |= SDMMC_CMDR_WAITRESP; 238 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 239 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 240 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 241 } else { 242 flags_cmd |= SDMMC_STAR_CMDREND; 243 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 244 } 245 } 246 247 switch (cmd->cmd_idx) { 248 case MMC_CMD(1): 249 arg_reg |= OCR_POWERUP; 250 break; 251 case MMC_CMD(8): 252 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 253 cmd_reg |= SDMMC_CMDR_CMDTRANS; 254 } 255 break; 256 case MMC_CMD(12): 257 cmd_reg |= SDMMC_CMDR_CMDSTOP; 258 break; 259 case MMC_CMD(17): 260 case MMC_CMD(18): 261 cmd_reg |= SDMMC_CMDR_CMDTRANS; 262 if (sdmmc2_params.use_dma) { 263 flags_data |= SDMMC_STAR_DCRCFAIL | 264 SDMMC_STAR_DTIMEOUT | 265 SDMMC_STAR_DATAEND | 266 SDMMC_STAR_RXOVERR | 267 SDMMC_STAR_IDMATE; 268 } 269 break; 270 case MMC_ACMD(41): 271 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 272 break; 273 case MMC_ACMD(51): 274 cmd_reg |= SDMMC_CMDR_CMDTRANS; 275 if (sdmmc2_params.use_dma) { 276 flags_data |= SDMMC_STAR_DCRCFAIL | 277 SDMMC_STAR_DTIMEOUT | 278 SDMMC_STAR_DATAEND | 279 SDMMC_STAR_RXOVERR | 280 SDMMC_STAR_IDMATE | 281 SDMMC_STAR_DBCKEND; 282 } 283 break; 284 default: 285 break; 286 } 287 288 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 289 290 /* 291 * Clear the SDMMC_DCTRLR if the command does not await data. 292 * Skip CMD55 as the next command could be data related, and 293 * the register could have been set in prepare function. 294 */ 295 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && 296 (cmd->cmd_idx != MMC_CMD(55))) { 297 mmio_write_32(base + SDMMC_DCTRLR, 0U); 298 } 299 300 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 301 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 302 } 303 304 mmio_write_32(base + SDMMC_ARGR, arg_reg); 305 306 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 307 308 status = mmio_read_32(base + SDMMC_STAR); 309 310 timeout = timeout_init_us(TIMEOUT_US_10_MS); 311 312 while ((status & flags_cmd) == 0U) { 313 if (timeout_elapsed(timeout)) { 314 err = -ETIMEDOUT; 315 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 316 __func__, cmd->cmd_idx, status); 317 goto err_exit; 318 } 319 320 status = mmio_read_32(base + SDMMC_STAR); 321 } 322 323 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 324 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 325 err = -ETIMEDOUT; 326 /* 327 * Those timeouts can occur, and framework will handle 328 * the retries. CMD8 is expected to return this timeout 329 * for eMMC 330 */ 331 if (!((cmd->cmd_idx == MMC_CMD(1)) || 332 (cmd->cmd_idx == MMC_CMD(13)) || 333 ((cmd->cmd_idx == MMC_CMD(8)) && 334 (cmd->resp_type == MMC_RESPONSE_R7)))) { 335 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 336 __func__, cmd->cmd_idx, status); 337 } 338 } else { 339 err = -EIO; 340 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 341 __func__, cmd->cmd_idx, status); 342 } 343 344 goto err_exit; 345 } 346 347 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 348 if ((cmd->cmd_idx == MMC_CMD(9)) && 349 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 350 /* Need to invert response to match CSD structure */ 351 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 352 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 353 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 354 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 355 } else { 356 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 357 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 358 SDMMC_CMDR_WAITRESP) { 359 cmd->resp_data[1] = mmio_read_32(base + 360 SDMMC_RESP2R); 361 cmd->resp_data[2] = mmio_read_32(base + 362 SDMMC_RESP3R); 363 cmd->resp_data[3] = mmio_read_32(base + 364 SDMMC_RESP4R); 365 } 366 } 367 } 368 369 if (flags_data == 0U) { 370 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 371 372 return 0; 373 } 374 375 status = mmio_read_32(base + SDMMC_STAR); 376 377 timeout = timeout_init_us(TIMEOUT_US_10_MS); 378 379 while ((status & flags_data) == 0U) { 380 if (timeout_elapsed(timeout)) { 381 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 382 __func__, cmd->cmd_idx, status); 383 err = -ETIMEDOUT; 384 goto err_exit; 385 } 386 387 status = mmio_read_32(base + SDMMC_STAR); 388 }; 389 390 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 391 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 392 SDMMC_STAR_IDMATE)) != 0U) { 393 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 394 cmd->cmd_idx, status); 395 err = -EIO; 396 } 397 398 err_exit: 399 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 400 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 401 402 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 403 int ret_stop = stm32_sdmmc2_stop_transfer(); 404 405 if (ret_stop != 0) { 406 return ret_stop; 407 } 408 } 409 410 return err; 411 } 412 413 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 414 { 415 uint8_t retry; 416 int err; 417 418 assert(cmd != NULL); 419 420 for (retry = 0U; retry < 3U; retry++) { 421 err = stm32_sdmmc2_send_cmd_req(cmd); 422 if (err == 0) { 423 return 0; 424 } 425 426 if ((cmd->cmd_idx == MMC_CMD(1)) || 427 (cmd->cmd_idx == MMC_CMD(13))) { 428 return 0; /* Retry managed by framework */ 429 } 430 431 /* Command 8 is expected to fail for eMMC */ 432 if (cmd->cmd_idx != MMC_CMD(8)) { 433 WARN(" CMD%u, Retry: %u, Error: %d\n", 434 cmd->cmd_idx, retry + 1U, err); 435 } 436 437 udelay(10U); 438 } 439 440 return err; 441 } 442 443 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 444 { 445 uintptr_t base = sdmmc2_params.reg_base; 446 uint32_t bus_cfg = 0; 447 uint32_t clock_div, max_freq, freq; 448 uint32_t clk_rate = sdmmc2_params.clk_rate; 449 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 450 451 switch (width) { 452 case MMC_BUS_WIDTH_1: 453 break; 454 case MMC_BUS_WIDTH_4: 455 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 456 break; 457 case MMC_BUS_WIDTH_8: 458 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 459 break; 460 default: 461 panic(); 462 break; 463 } 464 465 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 466 if (max_bus_freq >= 52000000U) { 467 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 468 } else { 469 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 470 } 471 } else { 472 if (max_bus_freq >= 50000000U) { 473 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 474 } else { 475 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 476 } 477 } 478 479 if (sdmmc2_params.max_freq != 0U) { 480 freq = MIN(sdmmc2_params.max_freq, max_freq); 481 } else { 482 freq = max_freq; 483 } 484 485 clock_div = div_round_up(clk_rate, freq * 2U); 486 487 mmio_write_32(base + SDMMC_CLKCR, 488 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 489 sdmmc2_params.negedge | 490 sdmmc2_params.pin_ckin); 491 492 return 0; 493 } 494 495 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 496 { 497 struct mmc_cmd cmd; 498 int ret; 499 uintptr_t base = sdmmc2_params.reg_base; 500 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 501 uint32_t arg_size; 502 503 assert(size != 0U); 504 505 if (size > MMC_BLOCK_SIZE) { 506 arg_size = MMC_BLOCK_SIZE; 507 } else { 508 arg_size = size; 509 } 510 511 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 512 513 if (sdmmc2_params.use_dma) { 514 inv_dcache_range(buf, size); 515 } 516 517 /* Prepare CMD 16*/ 518 mmio_write_32(base + SDMMC_DTIMER, 0); 519 520 mmio_write_32(base + SDMMC_DLENR, 0); 521 522 mmio_write_32(base + SDMMC_DCTRLR, 0); 523 524 zeromem(&cmd, sizeof(struct mmc_cmd)); 525 526 cmd.cmd_idx = MMC_CMD(16); 527 cmd.cmd_arg = arg_size; 528 cmd.resp_type = MMC_RESPONSE_R1; 529 530 ret = stm32_sdmmc2_send_cmd(&cmd); 531 if (ret != 0) { 532 ERROR("CMD16 failed\n"); 533 return ret; 534 } 535 536 /* Prepare data command */ 537 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 538 539 mmio_write_32(base + SDMMC_DLENR, size); 540 541 if (sdmmc2_params.use_dma) { 542 mmio_write_32(base + SDMMC_IDMACTRLR, 543 SDMMC_IDMACTRLR_IDMAEN); 544 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 545 546 flush_dcache_range(buf, size); 547 } 548 549 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 550 551 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 552 SDMMC_DCTRLR_CLEAR_MASK, 553 data_ctrl); 554 555 return 0; 556 } 557 558 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 559 { 560 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 561 SDMMC_STAR_DTIMEOUT; 562 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 563 uint32_t status; 564 uint32_t *buffer; 565 uintptr_t base = sdmmc2_params.reg_base; 566 uintptr_t fifo_reg = base + SDMMC_FIFOR; 567 uint64_t timeout; 568 int ret; 569 570 /* Assert buf is 4 bytes aligned */ 571 assert((buf & GENMASK(1, 0)) == 0U); 572 573 buffer = (uint32_t *)buf; 574 575 if (sdmmc2_params.use_dma) { 576 inv_dcache_range(buf, size); 577 578 return 0; 579 } 580 581 if (size <= MMC_BLOCK_SIZE) { 582 flags |= SDMMC_STAR_DBCKEND; 583 } 584 585 timeout = timeout_init_us(TIMEOUT_US_1_S); 586 587 do { 588 status = mmio_read_32(base + SDMMC_STAR); 589 590 if ((status & error_flags) != 0U) { 591 ERROR("%s: Read error (status = %x)\n", __func__, 592 status); 593 mmio_write_32(base + SDMMC_DCTRLR, 594 SDMMC_DCTRLR_FIFORST); 595 596 mmio_write_32(base + SDMMC_ICR, 597 SDMMC_STATIC_FLAGS); 598 599 ret = stm32_sdmmc2_stop_transfer(); 600 if (ret != 0) { 601 return ret; 602 } 603 604 return -EIO; 605 } 606 607 if (timeout_elapsed(timeout)) { 608 ERROR("%s: timeout 1s (status = %x)\n", 609 __func__, status); 610 mmio_write_32(base + SDMMC_ICR, 611 SDMMC_STATIC_FLAGS); 612 613 ret = stm32_sdmmc2_stop_transfer(); 614 if (ret != 0) { 615 return ret; 616 } 617 618 return -ETIMEDOUT; 619 } 620 621 if (size < (8U * sizeof(uint32_t))) { 622 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 623 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 624 *buffer = mmio_read_32(fifo_reg); 625 buffer++; 626 } 627 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 628 uint32_t count; 629 630 /* Read data from SDMMC Rx FIFO */ 631 for (count = 0; count < 8U; count++) { 632 *buffer = mmio_read_32(fifo_reg); 633 buffer++; 634 } 635 } 636 } while ((status & flags) == 0U); 637 638 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 639 640 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 641 WARN("%s: DPSMACT=1, send stop\n", __func__); 642 return stm32_sdmmc2_stop_transfer(); 643 } 644 645 return 0; 646 } 647 648 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 649 { 650 return 0; 651 } 652 653 static int stm32_sdmmc2_dt_get_config(void) 654 { 655 int sdmmc_node; 656 void *fdt = NULL; 657 const fdt32_t *cuint; 658 struct dt_node_info dt_info; 659 660 if (fdt_get_address(&fdt) == 0) { 661 return -FDT_ERR_NOTFOUND; 662 } 663 664 if (fdt == NULL) { 665 return -FDT_ERR_NOTFOUND; 666 } 667 668 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 669 sdmmc2_params.reg_base); 670 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 671 return -FDT_ERR_NOTFOUND; 672 } 673 674 dt_fill_device_info(&dt_info, sdmmc_node); 675 if (dt_info.status == DT_DISABLED) { 676 return -FDT_ERR_NOTFOUND; 677 } 678 679 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 680 return -FDT_ERR_BADVALUE; 681 } 682 683 sdmmc2_params.clock_id = dt_info.clock; 684 sdmmc2_params.reset_id = dt_info.reset; 685 686 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 687 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 688 } 689 690 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 691 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 692 } 693 694 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 695 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 696 } 697 698 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 699 if (cuint != NULL) { 700 switch (fdt32_to_cpu(*cuint)) { 701 case 4: 702 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 703 break; 704 705 case 8: 706 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 707 break; 708 709 default: 710 break; 711 } 712 } 713 714 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 715 if (cuint != NULL) { 716 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 717 } 718 719 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); 720 721 return 0; 722 } 723 724 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 725 { 726 return sdmmc2_params.device_info->device_size; 727 } 728 729 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 730 { 731 int rc; 732 733 assert((params != NULL) && 734 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 735 ((params->bus_width == MMC_BUS_WIDTH_1) || 736 (params->bus_width == MMC_BUS_WIDTH_4) || 737 (params->bus_width == MMC_BUS_WIDTH_8))); 738 739 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 740 741 sdmmc2_params.vmmc_regu = NULL; 742 743 if (stm32_sdmmc2_dt_get_config() != 0) { 744 ERROR("%s: DT error\n", __func__); 745 return -ENOMEM; 746 } 747 748 clk_enable(sdmmc2_params.clock_id); 749 750 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 751 if (rc != 0) { 752 panic(); 753 } 754 udelay(2); 755 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 756 if (rc != 0) { 757 panic(); 758 } 759 mdelay(1); 760 761 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 762 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 763 764 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 765 sdmmc2_params.bus_width, sdmmc2_params.flags, 766 sdmmc2_params.device_info); 767 } 768