1 /* 2 * Copyright (c) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <errno.h> 15 #include <libfdt.h> 16 #include <mmc.h> 17 #include <mmio.h> 18 #include <platform.h> 19 #include <stm32_sdmmc2.h> 20 #include <stm32mp1_clk.h> 21 #include <stm32mp1_dt.h> 22 #include <stm32mp1_rcc.h> 23 #include <stm32mp1_reset.h> 24 #include <string.h> 25 #include <utils.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_DIRPOL BIT(4) 54 55 /* SDMMC clock control register */ 56 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 57 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 58 #define SDMMC_CLKCR_NEGEDGE BIT(16) 59 #define SDMMC_CLKCR_HWFC_EN BIT(17) 60 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 61 62 /* SDMMC command register */ 63 #define SDMMC_CMDR_CMDTRANS BIT(6) 64 #define SDMMC_CMDR_CMDSTOP BIT(7) 65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 66 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 67 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 68 #define SDMMC_CMDR_CPSMEN BIT(12) 69 70 /* SDMMC data control register */ 71 #define SDMMC_DCTRLR_DTEN BIT(0) 72 #define SDMMC_DCTRLR_DTDIR BIT(1) 73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 74 #define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4) 75 #define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7) 77 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 78 #define SDMMC_DCTRLR_FIFORST BIT(13) 79 80 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 81 SDMMC_DCTRLR_DTDIR | \ 82 SDMMC_DCTRLR_DTMODE | \ 83 SDMMC_DCTRLR_DBLOCKSIZE) 84 #define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 85 SDMMC_DCTRLR_DBLOCKSIZE_1) 86 #define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 87 SDMMC_DCTRLR_DBLOCKSIZE_3) 88 89 /* SDMMC status register */ 90 #define SDMMC_STAR_CCRCFAIL BIT(0) 91 #define SDMMC_STAR_DCRCFAIL BIT(1) 92 #define SDMMC_STAR_CTIMEOUT BIT(2) 93 #define SDMMC_STAR_DTIMEOUT BIT(3) 94 #define SDMMC_STAR_TXUNDERR BIT(4) 95 #define SDMMC_STAR_RXOVERR BIT(5) 96 #define SDMMC_STAR_CMDREND BIT(6) 97 #define SDMMC_STAR_CMDSENT BIT(7) 98 #define SDMMC_STAR_DATAEND BIT(8) 99 #define SDMMC_STAR_DBCKEND BIT(10) 100 #define SDMMC_STAR_DPSMACT BIT(12) 101 #define SDMMC_STAR_RXFIFOHF BIT(15) 102 #define SDMMC_STAR_RXFIFOE BIT(19) 103 #define SDMMC_STAR_IDMATE BIT(27) 104 #define SDMMC_STAR_IDMABTC BIT(28) 105 106 /* SDMMC DMA control register */ 107 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 108 109 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 110 SDMMC_STAR_DCRCFAIL | \ 111 SDMMC_STAR_CTIMEOUT | \ 112 SDMMC_STAR_DTIMEOUT | \ 113 SDMMC_STAR_TXUNDERR | \ 114 SDMMC_STAR_RXOVERR | \ 115 SDMMC_STAR_CMDREND | \ 116 SDMMC_STAR_CMDSENT | \ 117 SDMMC_STAR_DATAEND | \ 118 SDMMC_STAR_DBCKEND | \ 119 SDMMC_STAR_IDMATE | \ 120 SDMMC_STAR_IDMABTC) 121 122 #define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U) 123 #define TIMEOUT_1_S plat_get_syscnt_freq2() 124 125 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 126 127 static void stm32_sdmmc2_init(void); 128 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 129 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 130 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 131 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 132 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 133 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 134 135 static const struct mmc_ops stm32_sdmmc2_ops = { 136 .init = stm32_sdmmc2_init, 137 .send_cmd = stm32_sdmmc2_send_cmd, 138 .set_ios = stm32_sdmmc2_set_ios, 139 .prepare = stm32_sdmmc2_prepare, 140 .read = stm32_sdmmc2_read, 141 .write = stm32_sdmmc2_write, 142 }; 143 144 static struct stm32_sdmmc2_params sdmmc2_params; 145 146 #pragma weak plat_sdmmc2_use_dma 147 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 148 { 149 return false; 150 } 151 152 static void stm32_sdmmc2_init(void) 153 { 154 uint32_t clock_div; 155 uintptr_t base = sdmmc2_params.reg_base; 156 157 clock_div = div_round_up(sdmmc2_params.clk_rate, 158 STM32MP1_MMC_INIT_FREQ * 2); 159 160 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 161 sdmmc2_params.negedge | 162 sdmmc2_params.pin_ckin); 163 164 mmio_write_32(base + SDMMC_POWER, 165 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 166 167 mdelay(1); 168 } 169 170 static int stm32_sdmmc2_stop_transfer(void) 171 { 172 struct mmc_cmd cmd_stop; 173 174 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 175 176 cmd_stop.cmd_idx = MMC_CMD(12); 177 cmd_stop.resp_type = MMC_RESPONSE_R1B; 178 179 return stm32_sdmmc2_send_cmd(&cmd_stop); 180 } 181 182 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 183 { 184 uint32_t flags_cmd, status; 185 uint32_t flags_data = 0; 186 int err = 0; 187 uintptr_t base = sdmmc2_params.reg_base; 188 unsigned int cmd_reg, arg_reg, start; 189 190 if (cmd == NULL) { 191 return -EINVAL; 192 } 193 194 flags_cmd = SDMMC_STAR_CTIMEOUT; 195 arg_reg = cmd->cmd_arg; 196 197 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 198 mmio_write_32(base + SDMMC_CMDR, 0); 199 } 200 201 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 202 203 if (cmd->resp_type == 0U) { 204 flags_cmd |= SDMMC_STAR_CMDSENT; 205 } 206 207 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 208 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 209 flags_cmd |= SDMMC_STAR_CMDREND; 210 cmd_reg |= SDMMC_CMDR_WAITRESP; 211 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 212 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 213 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 214 } else { 215 flags_cmd |= SDMMC_STAR_CMDREND; 216 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 217 } 218 } 219 220 switch (cmd->cmd_idx) { 221 case MMC_CMD(1): 222 arg_reg |= OCR_POWERUP; 223 break; 224 case MMC_CMD(8): 225 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 226 cmd_reg |= SDMMC_CMDR_CMDTRANS; 227 } 228 break; 229 case MMC_CMD(12): 230 cmd_reg |= SDMMC_CMDR_CMDSTOP; 231 break; 232 case MMC_CMD(17): 233 case MMC_CMD(18): 234 cmd_reg |= SDMMC_CMDR_CMDTRANS; 235 if (sdmmc2_params.use_dma) { 236 flags_data |= SDMMC_STAR_DCRCFAIL | 237 SDMMC_STAR_DTIMEOUT | 238 SDMMC_STAR_DATAEND | 239 SDMMC_STAR_RXOVERR | 240 SDMMC_STAR_IDMATE; 241 } 242 break; 243 case MMC_ACMD(41): 244 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 245 break; 246 case MMC_ACMD(51): 247 cmd_reg |= SDMMC_CMDR_CMDTRANS; 248 if (sdmmc2_params.use_dma) { 249 flags_data |= SDMMC_STAR_DCRCFAIL | 250 SDMMC_STAR_DTIMEOUT | 251 SDMMC_STAR_DATAEND | 252 SDMMC_STAR_RXOVERR | 253 SDMMC_STAR_IDMATE | 254 SDMMC_STAR_DBCKEND; 255 } 256 break; 257 default: 258 break; 259 } 260 261 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 262 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 263 } 264 265 mmio_write_32(base + SDMMC_ARGR, arg_reg); 266 267 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 268 269 status = mmio_read_32(base + SDMMC_STAR); 270 271 start = get_timer(0); 272 273 while ((status & flags_cmd) == 0U) { 274 if (get_timer(start) > TIMEOUT_10_MS) { 275 err = -ETIMEDOUT; 276 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 277 __func__, cmd->cmd_idx, status); 278 goto err_exit; 279 } 280 281 status = mmio_read_32(base + SDMMC_STAR); 282 } 283 284 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 285 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 286 err = -ETIMEDOUT; 287 /* 288 * Those timeouts can occur, and framework will handle 289 * the retries. CMD8 is expected to return this timeout 290 * for eMMC 291 */ 292 if (!((cmd->cmd_idx == MMC_CMD(1)) || 293 (cmd->cmd_idx == MMC_CMD(13)) || 294 ((cmd->cmd_idx == MMC_CMD(8)) && 295 (cmd->resp_type == MMC_RESPONSE_R7)))) { 296 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 297 __func__, cmd->cmd_idx, status); 298 } 299 } else { 300 err = -EIO; 301 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 302 __func__, cmd->cmd_idx, status); 303 } 304 305 goto err_exit; 306 } 307 308 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 309 if ((cmd->cmd_idx == MMC_CMD(9)) && 310 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 311 /* Need to invert response to match CSD structure */ 312 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 313 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 314 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 315 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 316 } else { 317 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 318 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 319 SDMMC_CMDR_WAITRESP) { 320 cmd->resp_data[1] = mmio_read_32(base + 321 SDMMC_RESP2R); 322 cmd->resp_data[2] = mmio_read_32(base + 323 SDMMC_RESP3R); 324 cmd->resp_data[3] = mmio_read_32(base + 325 SDMMC_RESP4R); 326 } 327 } 328 } 329 330 if (flags_data == 0U) { 331 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 332 333 return 0; 334 } 335 336 status = mmio_read_32(base + SDMMC_STAR); 337 338 start = get_timer(0); 339 340 while ((status & flags_data) == 0U) { 341 if (get_timer(start) > TIMEOUT_10_MS) { 342 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 343 __func__, cmd->cmd_idx, status); 344 err = -ETIMEDOUT; 345 goto err_exit; 346 } 347 348 status = mmio_read_32(base + SDMMC_STAR); 349 }; 350 351 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 352 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 353 SDMMC_STAR_IDMATE)) != 0U) { 354 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 355 cmd->cmd_idx, status); 356 err = -EIO; 357 } 358 359 err_exit: 360 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 361 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 362 363 if (err != 0) { 364 int ret_stop = stm32_sdmmc2_stop_transfer(); 365 366 if (ret_stop != 0) { 367 return ret_stop; 368 } 369 } 370 371 return err; 372 } 373 374 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 375 { 376 int8_t retry; 377 int err = 0; 378 379 assert(cmd != NULL); 380 381 for (retry = 0; retry <= 3; retry++) { 382 err = stm32_sdmmc2_send_cmd_req(cmd); 383 if (err == 0) { 384 return err; 385 } 386 387 if ((cmd->cmd_idx == MMC_CMD(1)) || 388 (cmd->cmd_idx == MMC_CMD(13))) { 389 return 0; /* Retry managed by framework */ 390 } 391 392 /* Command 8 is expected to fail for eMMC */ 393 if (!(cmd->cmd_idx == MMC_CMD(8))) { 394 WARN(" CMD%d, Retry: %d, Error: %d\n", 395 cmd->cmd_idx, retry, err); 396 } 397 398 udelay(10); 399 } 400 401 return err; 402 } 403 404 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 405 { 406 uintptr_t base = sdmmc2_params.reg_base; 407 uint32_t bus_cfg = 0; 408 uint32_t clock_div, max_freq; 409 uint32_t clk_rate = sdmmc2_params.clk_rate; 410 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 411 412 switch (width) { 413 case MMC_BUS_WIDTH_1: 414 break; 415 case MMC_BUS_WIDTH_4: 416 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 417 break; 418 case MMC_BUS_WIDTH_8: 419 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 420 break; 421 default: 422 panic(); 423 break; 424 } 425 426 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 427 if (max_bus_freq >= 52000000U) { 428 max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ; 429 } else { 430 max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ; 431 } 432 } else { 433 if (max_bus_freq >= 50000000U) { 434 max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ; 435 } else { 436 max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ; 437 } 438 } 439 440 clock_div = div_round_up(clk_rate, max_freq * 2); 441 442 mmio_write_32(base + SDMMC_CLKCR, 443 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 444 sdmmc2_params.negedge | 445 sdmmc2_params.pin_ckin); 446 447 return 0; 448 } 449 450 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 451 { 452 struct mmc_cmd cmd; 453 int ret; 454 uintptr_t base = sdmmc2_params.reg_base; 455 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 456 457 if (size == 8U) { 458 data_ctrl |= SDMMC_DBLOCKSIZE_8; 459 } else { 460 data_ctrl |= SDMMC_DBLOCKSIZE_512; 461 } 462 463 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 464 465 if (sdmmc2_params.use_dma) { 466 inv_dcache_range(buf, size); 467 } 468 469 /* Prepare CMD 16*/ 470 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 471 472 mmio_write_32(base + SDMMC_DLENR, 0); 473 474 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 475 SDMMC_DCTRLR_CLEAR_MASK, SDMMC_DCTRLR_DTDIR); 476 477 zeromem(&cmd, sizeof(struct mmc_cmd)); 478 479 cmd.cmd_idx = MMC_CMD(16); 480 if (size > MMC_BLOCK_SIZE) { 481 cmd.cmd_arg = MMC_BLOCK_SIZE; 482 } else { 483 cmd.cmd_arg = size; 484 } 485 486 cmd.resp_type = MMC_RESPONSE_R1; 487 488 ret = stm32_sdmmc2_send_cmd(&cmd); 489 if (ret != 0) { 490 ERROR("CMD16 failed\n"); 491 return ret; 492 } 493 494 /* Prepare data command */ 495 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 496 497 mmio_write_32(base + SDMMC_DLENR, size); 498 499 if (sdmmc2_params.use_dma) { 500 mmio_write_32(base + SDMMC_IDMACTRLR, 501 SDMMC_IDMACTRLR_IDMAEN); 502 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 503 504 flush_dcache_range(buf, size); 505 } 506 507 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 508 SDMMC_DCTRLR_CLEAR_MASK, 509 data_ctrl); 510 511 return 0; 512 } 513 514 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 515 { 516 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 517 SDMMC_STAR_DTIMEOUT; 518 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 519 uint32_t status; 520 uint32_t *buffer; 521 uintptr_t base = sdmmc2_params.reg_base; 522 uintptr_t fifo_reg = base + SDMMC_FIFOR; 523 unsigned int start; 524 int ret; 525 526 /* Assert buf is 4 bytes aligned */ 527 assert((buf & GENMASK(1, 0)) == 0U); 528 529 buffer = (uint32_t *)buf; 530 531 if (sdmmc2_params.use_dma) { 532 inv_dcache_range(buf, size); 533 534 return 0; 535 } 536 537 if (size <= MMC_BLOCK_SIZE) { 538 flags |= SDMMC_STAR_DBCKEND; 539 } 540 541 start = get_timer(0); 542 543 do { 544 status = mmio_read_32(base + SDMMC_STAR); 545 546 if ((status & error_flags) != 0U) { 547 ERROR("%s: Read error (status = %x)\n", __func__, 548 status); 549 mmio_write_32(base + SDMMC_DCTRLR, 550 SDMMC_DCTRLR_FIFORST); 551 552 mmio_write_32(base + SDMMC_ICR, 553 SDMMC_STATIC_FLAGS); 554 555 ret = stm32_sdmmc2_stop_transfer(); 556 if (ret != 0) { 557 return ret; 558 } 559 560 return -EIO; 561 } 562 563 if (get_timer(start) > TIMEOUT_1_S) { 564 ERROR("%s: timeout 1s (status = %x)\n", 565 __func__, status); 566 mmio_write_32(base + SDMMC_ICR, 567 SDMMC_STATIC_FLAGS); 568 569 ret = stm32_sdmmc2_stop_transfer(); 570 if (ret != 0) { 571 return ret; 572 } 573 574 return -ETIMEDOUT; 575 } 576 577 if (size < (8U * sizeof(uint32_t))) { 578 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 579 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 580 *buffer = mmio_read_32(fifo_reg); 581 buffer++; 582 } 583 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 584 uint32_t count; 585 586 /* Read data from SDMMC Rx FIFO */ 587 for (count = 0; count < 8U; count++) { 588 *buffer = mmio_read_32(fifo_reg); 589 buffer++; 590 } 591 } 592 } while ((status & flags) == 0U); 593 594 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 595 596 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 597 WARN("%s: DPSMACT=1, send stop\n", __func__); 598 return stm32_sdmmc2_stop_transfer(); 599 } 600 601 return 0; 602 } 603 604 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 605 { 606 return 0; 607 } 608 609 static int stm32_sdmmc2_dt_get_config(void) 610 { 611 int sdmmc_node; 612 void *fdt = NULL; 613 const fdt32_t *cuint; 614 615 if (fdt_get_address(&fdt) == 0) { 616 return -FDT_ERR_NOTFOUND; 617 } 618 619 if (fdt == NULL) { 620 return -FDT_ERR_NOTFOUND; 621 } 622 623 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 624 625 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 626 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 627 if (cuint == NULL) { 628 continue; 629 } 630 631 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 632 break; 633 } 634 635 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 636 DT_SDMMC2_COMPAT); 637 } 638 639 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 640 return -FDT_ERR_NOTFOUND; 641 } 642 643 if (fdt_check_status(sdmmc_node) == 0) { 644 return -FDT_ERR_NOTFOUND; 645 } 646 647 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 648 return -FDT_ERR_BADVALUE; 649 } 650 651 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 652 if (cuint == NULL) { 653 return -FDT_ERR_NOTFOUND; 654 } 655 656 cuint++; 657 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 658 659 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 660 if (cuint == NULL) { 661 return -FDT_ERR_NOTFOUND; 662 } 663 664 cuint++; 665 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 666 667 if ((fdt_getprop(fdt, sdmmc_node, "st,pin-ckin", NULL)) != NULL) { 668 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 669 } 670 671 if ((fdt_getprop(fdt, sdmmc_node, "st,dirpol", NULL)) != NULL) { 672 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 673 } 674 675 if ((fdt_getprop(fdt, sdmmc_node, "st,negedge", NULL)) != NULL) { 676 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 677 } 678 679 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 680 if (cuint != NULL) { 681 switch (fdt32_to_cpu(*cuint)) { 682 case 4: 683 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 684 break; 685 686 case 8: 687 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 688 break; 689 690 default: 691 break; 692 } 693 } 694 695 return 0; 696 } 697 698 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 699 { 700 return sdmmc2_params.device_info->device_size; 701 } 702 703 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 704 { 705 int ret; 706 707 assert((params != NULL) && 708 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 709 ((params->bus_width == MMC_BUS_WIDTH_1) || 710 (params->bus_width == MMC_BUS_WIDTH_4) || 711 (params->bus_width == MMC_BUS_WIDTH_8))); 712 713 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 714 715 if (stm32_sdmmc2_dt_get_config() != 0) { 716 ERROR("%s: DT error\n", __func__); 717 return -ENOMEM; 718 } 719 720 ret = stm32mp1_clk_enable(sdmmc2_params.clock_id); 721 if (ret != 0) { 722 ERROR("%s: clock %d failed\n", __func__, 723 sdmmc2_params.clock_id); 724 return ret; 725 } 726 727 stm32mp1_reset_assert(sdmmc2_params.reset_id); 728 udelay(2); 729 stm32mp1_reset_deassert(sdmmc2_params.reset_id); 730 mdelay(1); 731 732 sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id); 733 734 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 735 sdmmc2_params.bus_width, sdmmc2_params.flags, 736 sdmmc2_params.device_info); 737 } 738