1 /* 2 * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <common/debug.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32_sdmmc2.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_rcc.h> 24 #include <drivers/st/stm32mp1_reset.h> 25 #include <dt-bindings/clock/stm32mp1-clks.h> 26 #include <dt-bindings/reset/stm32mp1-resets.h> 27 #include <lib/mmio.h> 28 #include <lib/utils.h> 29 #include <plat/common/platform.h> 30 31 /* Registers offsets */ 32 #define SDMMC_POWER 0x00U 33 #define SDMMC_CLKCR 0x04U 34 #define SDMMC_ARGR 0x08U 35 #define SDMMC_CMDR 0x0CU 36 #define SDMMC_RESPCMDR 0x10U 37 #define SDMMC_RESP1R 0x14U 38 #define SDMMC_RESP2R 0x18U 39 #define SDMMC_RESP3R 0x1CU 40 #define SDMMC_RESP4R 0x20U 41 #define SDMMC_DTIMER 0x24U 42 #define SDMMC_DLENR 0x28U 43 #define SDMMC_DCTRLR 0x2CU 44 #define SDMMC_DCNTR 0x30U 45 #define SDMMC_STAR 0x34U 46 #define SDMMC_ICR 0x38U 47 #define SDMMC_MASKR 0x3CU 48 #define SDMMC_ACKTIMER 0x40U 49 #define SDMMC_IDMACTRLR 0x50U 50 #define SDMMC_IDMABSIZER 0x54U 51 #define SDMMC_IDMABASE0R 0x58U 52 #define SDMMC_IDMABASE1R 0x5CU 53 #define SDMMC_FIFOR 0x80U 54 55 /* SDMMC power control register */ 56 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 57 #define SDMMC_POWER_DIRPOL BIT(4) 58 59 /* SDMMC clock control register */ 60 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 61 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 62 #define SDMMC_CLKCR_NEGEDGE BIT(16) 63 #define SDMMC_CLKCR_HWFC_EN BIT(17) 64 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 65 66 /* SDMMC command register */ 67 #define SDMMC_CMDR_CMDTRANS BIT(6) 68 #define SDMMC_CMDR_CMDSTOP BIT(7) 69 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 70 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 71 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 72 #define SDMMC_CMDR_CPSMEN BIT(12) 73 74 /* SDMMC data control register */ 75 #define SDMMC_DCTRLR_DTEN BIT(0) 76 #define SDMMC_DCTRLR_DTDIR BIT(1) 77 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 78 #define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4) 79 #define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5) 80 #define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7) 81 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 82 #define SDMMC_DCTRLR_FIFORST BIT(13) 83 84 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 85 SDMMC_DCTRLR_DTDIR | \ 86 SDMMC_DCTRLR_DTMODE | \ 87 SDMMC_DCTRLR_DBLOCKSIZE) 88 #define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 89 SDMMC_DCTRLR_DBLOCKSIZE_1) 90 #define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 91 SDMMC_DCTRLR_DBLOCKSIZE_3) 92 93 /* SDMMC status register */ 94 #define SDMMC_STAR_CCRCFAIL BIT(0) 95 #define SDMMC_STAR_DCRCFAIL BIT(1) 96 #define SDMMC_STAR_CTIMEOUT BIT(2) 97 #define SDMMC_STAR_DTIMEOUT BIT(3) 98 #define SDMMC_STAR_TXUNDERR BIT(4) 99 #define SDMMC_STAR_RXOVERR BIT(5) 100 #define SDMMC_STAR_CMDREND BIT(6) 101 #define SDMMC_STAR_CMDSENT BIT(7) 102 #define SDMMC_STAR_DATAEND BIT(8) 103 #define SDMMC_STAR_DBCKEND BIT(10) 104 #define SDMMC_STAR_DPSMACT BIT(12) 105 #define SDMMC_STAR_RXFIFOHF BIT(15) 106 #define SDMMC_STAR_RXFIFOE BIT(19) 107 #define SDMMC_STAR_IDMATE BIT(27) 108 #define SDMMC_STAR_IDMABTC BIT(28) 109 110 /* SDMMC DMA control register */ 111 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 112 113 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 114 SDMMC_STAR_DCRCFAIL | \ 115 SDMMC_STAR_CTIMEOUT | \ 116 SDMMC_STAR_DTIMEOUT | \ 117 SDMMC_STAR_TXUNDERR | \ 118 SDMMC_STAR_RXOVERR | \ 119 SDMMC_STAR_CMDREND | \ 120 SDMMC_STAR_CMDSENT | \ 121 SDMMC_STAR_DATAEND | \ 122 SDMMC_STAR_DBCKEND | \ 123 SDMMC_STAR_IDMATE | \ 124 SDMMC_STAR_IDMABTC) 125 126 #define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U) 127 #define TIMEOUT_1_S plat_get_syscnt_freq2() 128 129 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 130 131 static void stm32_sdmmc2_init(void); 132 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 133 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 134 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 135 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 136 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 137 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 138 139 static const struct mmc_ops stm32_sdmmc2_ops = { 140 .init = stm32_sdmmc2_init, 141 .send_cmd = stm32_sdmmc2_send_cmd, 142 .set_ios = stm32_sdmmc2_set_ios, 143 .prepare = stm32_sdmmc2_prepare, 144 .read = stm32_sdmmc2_read, 145 .write = stm32_sdmmc2_write, 146 }; 147 148 static struct stm32_sdmmc2_params sdmmc2_params; 149 150 #pragma weak plat_sdmmc2_use_dma 151 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 152 { 153 return false; 154 } 155 156 static void stm32_sdmmc2_init(void) 157 { 158 uint32_t clock_div; 159 uintptr_t base = sdmmc2_params.reg_base; 160 161 clock_div = div_round_up(sdmmc2_params.clk_rate, 162 STM32MP1_MMC_INIT_FREQ * 2); 163 164 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 165 sdmmc2_params.negedge | 166 sdmmc2_params.pin_ckin); 167 168 mmio_write_32(base + SDMMC_POWER, 169 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 170 171 mdelay(1); 172 } 173 174 static int stm32_sdmmc2_stop_transfer(void) 175 { 176 struct mmc_cmd cmd_stop; 177 178 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 179 180 cmd_stop.cmd_idx = MMC_CMD(12); 181 cmd_stop.resp_type = MMC_RESPONSE_R1B; 182 183 return stm32_sdmmc2_send_cmd(&cmd_stop); 184 } 185 186 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 187 { 188 uint32_t flags_cmd, status; 189 uint32_t flags_data = 0; 190 int err = 0; 191 uintptr_t base = sdmmc2_params.reg_base; 192 unsigned int cmd_reg, arg_reg, start; 193 194 if (cmd == NULL) { 195 return -EINVAL; 196 } 197 198 flags_cmd = SDMMC_STAR_CTIMEOUT; 199 arg_reg = cmd->cmd_arg; 200 201 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 202 mmio_write_32(base + SDMMC_CMDR, 0); 203 } 204 205 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 206 207 if (cmd->resp_type == 0U) { 208 flags_cmd |= SDMMC_STAR_CMDSENT; 209 } 210 211 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 212 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 213 flags_cmd |= SDMMC_STAR_CMDREND; 214 cmd_reg |= SDMMC_CMDR_WAITRESP; 215 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 216 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 217 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 218 } else { 219 flags_cmd |= SDMMC_STAR_CMDREND; 220 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 221 } 222 } 223 224 switch (cmd->cmd_idx) { 225 case MMC_CMD(1): 226 arg_reg |= OCR_POWERUP; 227 break; 228 case MMC_CMD(8): 229 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 230 cmd_reg |= SDMMC_CMDR_CMDTRANS; 231 } 232 break; 233 case MMC_CMD(12): 234 cmd_reg |= SDMMC_CMDR_CMDSTOP; 235 break; 236 case MMC_CMD(17): 237 case MMC_CMD(18): 238 cmd_reg |= SDMMC_CMDR_CMDTRANS; 239 if (sdmmc2_params.use_dma) { 240 flags_data |= SDMMC_STAR_DCRCFAIL | 241 SDMMC_STAR_DTIMEOUT | 242 SDMMC_STAR_DATAEND | 243 SDMMC_STAR_RXOVERR | 244 SDMMC_STAR_IDMATE; 245 } 246 break; 247 case MMC_ACMD(41): 248 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 249 break; 250 case MMC_ACMD(51): 251 cmd_reg |= SDMMC_CMDR_CMDTRANS; 252 if (sdmmc2_params.use_dma) { 253 flags_data |= SDMMC_STAR_DCRCFAIL | 254 SDMMC_STAR_DTIMEOUT | 255 SDMMC_STAR_DATAEND | 256 SDMMC_STAR_RXOVERR | 257 SDMMC_STAR_IDMATE | 258 SDMMC_STAR_DBCKEND; 259 } 260 break; 261 default: 262 break; 263 } 264 265 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 266 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 267 } 268 269 mmio_write_32(base + SDMMC_ARGR, arg_reg); 270 271 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 272 273 status = mmio_read_32(base + SDMMC_STAR); 274 275 start = get_timer(0); 276 277 while ((status & flags_cmd) == 0U) { 278 if (get_timer(start) > TIMEOUT_10_MS) { 279 err = -ETIMEDOUT; 280 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 281 __func__, cmd->cmd_idx, status); 282 goto err_exit; 283 } 284 285 status = mmio_read_32(base + SDMMC_STAR); 286 } 287 288 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 289 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 290 err = -ETIMEDOUT; 291 /* 292 * Those timeouts can occur, and framework will handle 293 * the retries. CMD8 is expected to return this timeout 294 * for eMMC 295 */ 296 if (!((cmd->cmd_idx == MMC_CMD(1)) || 297 (cmd->cmd_idx == MMC_CMD(13)) || 298 ((cmd->cmd_idx == MMC_CMD(8)) && 299 (cmd->resp_type == MMC_RESPONSE_R7)))) { 300 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 301 __func__, cmd->cmd_idx, status); 302 } 303 } else { 304 err = -EIO; 305 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 306 __func__, cmd->cmd_idx, status); 307 } 308 309 goto err_exit; 310 } 311 312 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 313 if ((cmd->cmd_idx == MMC_CMD(9)) && 314 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 315 /* Need to invert response to match CSD structure */ 316 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 317 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 318 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 319 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 320 } else { 321 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 322 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 323 SDMMC_CMDR_WAITRESP) { 324 cmd->resp_data[1] = mmio_read_32(base + 325 SDMMC_RESP2R); 326 cmd->resp_data[2] = mmio_read_32(base + 327 SDMMC_RESP3R); 328 cmd->resp_data[3] = mmio_read_32(base + 329 SDMMC_RESP4R); 330 } 331 } 332 } 333 334 if (flags_data == 0U) { 335 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 336 337 return 0; 338 } 339 340 status = mmio_read_32(base + SDMMC_STAR); 341 342 start = get_timer(0); 343 344 while ((status & flags_data) == 0U) { 345 if (get_timer(start) > TIMEOUT_10_MS) { 346 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 347 __func__, cmd->cmd_idx, status); 348 err = -ETIMEDOUT; 349 goto err_exit; 350 } 351 352 status = mmio_read_32(base + SDMMC_STAR); 353 }; 354 355 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 356 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 357 SDMMC_STAR_IDMATE)) != 0U) { 358 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 359 cmd->cmd_idx, status); 360 err = -EIO; 361 } 362 363 err_exit: 364 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 365 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 366 367 if (err != 0) { 368 int ret_stop = stm32_sdmmc2_stop_transfer(); 369 370 if (ret_stop != 0) { 371 return ret_stop; 372 } 373 } 374 375 return err; 376 } 377 378 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 379 { 380 int8_t retry; 381 int err = 0; 382 383 assert(cmd != NULL); 384 385 for (retry = 0; retry <= 3; retry++) { 386 err = stm32_sdmmc2_send_cmd_req(cmd); 387 if (err == 0) { 388 return err; 389 } 390 391 if ((cmd->cmd_idx == MMC_CMD(1)) || 392 (cmd->cmd_idx == MMC_CMD(13))) { 393 return 0; /* Retry managed by framework */ 394 } 395 396 /* Command 8 is expected to fail for eMMC */ 397 if (!(cmd->cmd_idx == MMC_CMD(8))) { 398 WARN(" CMD%d, Retry: %d, Error: %d\n", 399 cmd->cmd_idx, retry, err); 400 } 401 402 udelay(10); 403 } 404 405 return err; 406 } 407 408 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 409 { 410 uintptr_t base = sdmmc2_params.reg_base; 411 uint32_t bus_cfg = 0; 412 uint32_t clock_div, max_freq; 413 uint32_t clk_rate = sdmmc2_params.clk_rate; 414 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 415 416 switch (width) { 417 case MMC_BUS_WIDTH_1: 418 break; 419 case MMC_BUS_WIDTH_4: 420 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 421 break; 422 case MMC_BUS_WIDTH_8: 423 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 424 break; 425 default: 426 panic(); 427 break; 428 } 429 430 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 431 if (max_bus_freq >= 52000000U) { 432 max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ; 433 } else { 434 max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ; 435 } 436 } else { 437 if (max_bus_freq >= 50000000U) { 438 max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ; 439 } else { 440 max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ; 441 } 442 } 443 444 clock_div = div_round_up(clk_rate, max_freq * 2); 445 446 mmio_write_32(base + SDMMC_CLKCR, 447 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 448 sdmmc2_params.negedge | 449 sdmmc2_params.pin_ckin); 450 451 return 0; 452 } 453 454 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 455 { 456 struct mmc_cmd cmd; 457 int ret; 458 uintptr_t base = sdmmc2_params.reg_base; 459 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 460 461 if (size == 8U) { 462 data_ctrl |= SDMMC_DBLOCKSIZE_8; 463 } else { 464 data_ctrl |= SDMMC_DBLOCKSIZE_512; 465 } 466 467 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 468 469 if (sdmmc2_params.use_dma) { 470 inv_dcache_range(buf, size); 471 } 472 473 /* Prepare CMD 16*/ 474 mmio_write_32(base + SDMMC_DTIMER, 0); 475 476 mmio_write_32(base + SDMMC_DLENR, 0); 477 478 mmio_write_32(base + SDMMC_DCTRLR, 0); 479 480 zeromem(&cmd, sizeof(struct mmc_cmd)); 481 482 cmd.cmd_idx = MMC_CMD(16); 483 if (size > MMC_BLOCK_SIZE) { 484 cmd.cmd_arg = MMC_BLOCK_SIZE; 485 } else { 486 cmd.cmd_arg = size; 487 } 488 489 cmd.resp_type = MMC_RESPONSE_R1; 490 491 ret = stm32_sdmmc2_send_cmd(&cmd); 492 if (ret != 0) { 493 ERROR("CMD16 failed\n"); 494 return ret; 495 } 496 497 /* Prepare data command */ 498 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 499 500 mmio_write_32(base + SDMMC_DLENR, size); 501 502 if (sdmmc2_params.use_dma) { 503 mmio_write_32(base + SDMMC_IDMACTRLR, 504 SDMMC_IDMACTRLR_IDMAEN); 505 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 506 507 flush_dcache_range(buf, size); 508 } 509 510 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 511 SDMMC_DCTRLR_CLEAR_MASK, 512 data_ctrl); 513 514 return 0; 515 } 516 517 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 518 { 519 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 520 SDMMC_STAR_DTIMEOUT; 521 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 522 uint32_t status; 523 uint32_t *buffer; 524 uintptr_t base = sdmmc2_params.reg_base; 525 uintptr_t fifo_reg = base + SDMMC_FIFOR; 526 unsigned int start; 527 int ret; 528 529 /* Assert buf is 4 bytes aligned */ 530 assert((buf & GENMASK(1, 0)) == 0U); 531 532 buffer = (uint32_t *)buf; 533 534 if (sdmmc2_params.use_dma) { 535 inv_dcache_range(buf, size); 536 537 return 0; 538 } 539 540 if (size <= MMC_BLOCK_SIZE) { 541 flags |= SDMMC_STAR_DBCKEND; 542 } 543 544 start = get_timer(0); 545 546 do { 547 status = mmio_read_32(base + SDMMC_STAR); 548 549 if ((status & error_flags) != 0U) { 550 ERROR("%s: Read error (status = %x)\n", __func__, 551 status); 552 mmio_write_32(base + SDMMC_DCTRLR, 553 SDMMC_DCTRLR_FIFORST); 554 555 mmio_write_32(base + SDMMC_ICR, 556 SDMMC_STATIC_FLAGS); 557 558 ret = stm32_sdmmc2_stop_transfer(); 559 if (ret != 0) { 560 return ret; 561 } 562 563 return -EIO; 564 } 565 566 if (get_timer(start) > TIMEOUT_1_S) { 567 ERROR("%s: timeout 1s (status = %x)\n", 568 __func__, status); 569 mmio_write_32(base + SDMMC_ICR, 570 SDMMC_STATIC_FLAGS); 571 572 ret = stm32_sdmmc2_stop_transfer(); 573 if (ret != 0) { 574 return ret; 575 } 576 577 return -ETIMEDOUT; 578 } 579 580 if (size < (8U * sizeof(uint32_t))) { 581 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 582 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 583 *buffer = mmio_read_32(fifo_reg); 584 buffer++; 585 } 586 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 587 uint32_t count; 588 589 /* Read data from SDMMC Rx FIFO */ 590 for (count = 0; count < 8U; count++) { 591 *buffer = mmio_read_32(fifo_reg); 592 buffer++; 593 } 594 } 595 } while ((status & flags) == 0U); 596 597 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 598 599 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 600 WARN("%s: DPSMACT=1, send stop\n", __func__); 601 return stm32_sdmmc2_stop_transfer(); 602 } 603 604 return 0; 605 } 606 607 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 608 { 609 return 0; 610 } 611 612 static int stm32_sdmmc2_dt_get_config(void) 613 { 614 int sdmmc_node; 615 void *fdt = NULL; 616 const fdt32_t *cuint; 617 618 if (fdt_get_address(&fdt) == 0) { 619 return -FDT_ERR_NOTFOUND; 620 } 621 622 if (fdt == NULL) { 623 return -FDT_ERR_NOTFOUND; 624 } 625 626 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 627 628 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 629 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 630 if (cuint == NULL) { 631 continue; 632 } 633 634 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 635 break; 636 } 637 638 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 639 DT_SDMMC2_COMPAT); 640 } 641 642 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 643 return -FDT_ERR_NOTFOUND; 644 } 645 646 if (fdt_get_status(sdmmc_node) == DT_DISABLED) { 647 return -FDT_ERR_NOTFOUND; 648 } 649 650 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 651 return -FDT_ERR_BADVALUE; 652 } 653 654 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 655 if (cuint == NULL) { 656 return -FDT_ERR_NOTFOUND; 657 } 658 659 cuint++; 660 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 661 662 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 663 if (cuint == NULL) { 664 return -FDT_ERR_NOTFOUND; 665 } 666 667 cuint++; 668 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 669 670 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 671 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 672 } 673 674 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 675 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 676 } 677 678 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 679 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 680 } 681 682 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 683 if (cuint != NULL) { 684 switch (fdt32_to_cpu(*cuint)) { 685 case 4: 686 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 687 break; 688 689 case 8: 690 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 691 break; 692 693 default: 694 break; 695 } 696 } 697 698 return 0; 699 } 700 701 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 702 { 703 return sdmmc2_params.device_info->device_size; 704 } 705 706 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 707 { 708 int ret; 709 710 assert((params != NULL) && 711 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 712 ((params->bus_width == MMC_BUS_WIDTH_1) || 713 (params->bus_width == MMC_BUS_WIDTH_4) || 714 (params->bus_width == MMC_BUS_WIDTH_8))); 715 716 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 717 718 if (stm32_sdmmc2_dt_get_config() != 0) { 719 ERROR("%s: DT error\n", __func__); 720 return -ENOMEM; 721 } 722 723 ret = stm32mp1_clk_enable(sdmmc2_params.clock_id); 724 if (ret != 0) { 725 ERROR("%s: clock %d failed\n", __func__, 726 sdmmc2_params.clock_id); 727 return ret; 728 } 729 730 stm32mp1_reset_assert(sdmmc2_params.reset_id); 731 udelay(2); 732 stm32mp1_reset_deassert(sdmmc2_params.reset_id); 733 mdelay(1); 734 735 sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id); 736 737 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 738 sdmmc2_params.bus_width, sdmmc2_params.flags, 739 sdmmc2_params.device_info); 740 } 741