1 /* 2 * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <common/debug.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32_sdmmc2.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_DIRPOL BIT(4) 54 55 /* SDMMC clock control register */ 56 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 57 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 58 #define SDMMC_CLKCR_NEGEDGE BIT(16) 59 #define SDMMC_CLKCR_HWFC_EN BIT(17) 60 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 61 62 /* SDMMC command register */ 63 #define SDMMC_CMDR_CMDTRANS BIT(6) 64 #define SDMMC_CMDR_CMDSTOP BIT(7) 65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 66 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 67 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 68 #define SDMMC_CMDR_CPSMEN BIT(12) 69 70 /* SDMMC data control register */ 71 #define SDMMC_DCTRLR_DTEN BIT(0) 72 #define SDMMC_DCTRLR_DTDIR BIT(1) 73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 74 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 75 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 76 #define SDMMC_DCTRLR_FIFORST BIT(13) 77 78 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 79 SDMMC_DCTRLR_DTDIR | \ 80 SDMMC_DCTRLR_DTMODE | \ 81 SDMMC_DCTRLR_DBLOCKSIZE) 82 83 /* SDMMC status register */ 84 #define SDMMC_STAR_CCRCFAIL BIT(0) 85 #define SDMMC_STAR_DCRCFAIL BIT(1) 86 #define SDMMC_STAR_CTIMEOUT BIT(2) 87 #define SDMMC_STAR_DTIMEOUT BIT(3) 88 #define SDMMC_STAR_TXUNDERR BIT(4) 89 #define SDMMC_STAR_RXOVERR BIT(5) 90 #define SDMMC_STAR_CMDREND BIT(6) 91 #define SDMMC_STAR_CMDSENT BIT(7) 92 #define SDMMC_STAR_DATAEND BIT(8) 93 #define SDMMC_STAR_DBCKEND BIT(10) 94 #define SDMMC_STAR_DPSMACT BIT(12) 95 #define SDMMC_STAR_RXFIFOHF BIT(15) 96 #define SDMMC_STAR_RXFIFOE BIT(19) 97 #define SDMMC_STAR_IDMATE BIT(27) 98 #define SDMMC_STAR_IDMABTC BIT(28) 99 100 /* SDMMC DMA control register */ 101 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 102 103 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 104 SDMMC_STAR_DCRCFAIL | \ 105 SDMMC_STAR_CTIMEOUT | \ 106 SDMMC_STAR_DTIMEOUT | \ 107 SDMMC_STAR_TXUNDERR | \ 108 SDMMC_STAR_RXOVERR | \ 109 SDMMC_STAR_CMDREND | \ 110 SDMMC_STAR_CMDSENT | \ 111 SDMMC_STAR_DATAEND | \ 112 SDMMC_STAR_DBCKEND | \ 113 SDMMC_STAR_IDMATE | \ 114 SDMMC_STAR_IDMABTC) 115 116 #define TIMEOUT_US_10_MS 10000U 117 #define TIMEOUT_US_1_S 1000000U 118 119 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 120 121 static void stm32_sdmmc2_init(void); 122 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 123 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 124 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 125 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 126 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 127 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 128 129 static const struct mmc_ops stm32_sdmmc2_ops = { 130 .init = stm32_sdmmc2_init, 131 .send_cmd = stm32_sdmmc2_send_cmd, 132 .set_ios = stm32_sdmmc2_set_ios, 133 .prepare = stm32_sdmmc2_prepare, 134 .read = stm32_sdmmc2_read, 135 .write = stm32_sdmmc2_write, 136 }; 137 138 static struct stm32_sdmmc2_params sdmmc2_params; 139 140 #pragma weak plat_sdmmc2_use_dma 141 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 142 { 143 return false; 144 } 145 146 static void stm32_sdmmc2_init(void) 147 { 148 uint32_t clock_div; 149 uint32_t freq = STM32MP_MMC_INIT_FREQ; 150 uintptr_t base = sdmmc2_params.reg_base; 151 152 if (sdmmc2_params.max_freq != 0U) { 153 freq = MIN(sdmmc2_params.max_freq, freq); 154 } 155 156 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 157 158 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 159 sdmmc2_params.negedge | 160 sdmmc2_params.pin_ckin); 161 162 mmio_write_32(base + SDMMC_POWER, 163 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 164 165 mdelay(1); 166 } 167 168 static int stm32_sdmmc2_stop_transfer(void) 169 { 170 struct mmc_cmd cmd_stop; 171 172 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 173 174 cmd_stop.cmd_idx = MMC_CMD(12); 175 cmd_stop.resp_type = MMC_RESPONSE_R1B; 176 177 return stm32_sdmmc2_send_cmd(&cmd_stop); 178 } 179 180 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 181 { 182 uint64_t timeout; 183 uint32_t flags_cmd, status; 184 uint32_t flags_data = 0; 185 int err = 0; 186 uintptr_t base = sdmmc2_params.reg_base; 187 unsigned int cmd_reg, arg_reg; 188 189 if (cmd == NULL) { 190 return -EINVAL; 191 } 192 193 flags_cmd = SDMMC_STAR_CTIMEOUT; 194 arg_reg = cmd->cmd_arg; 195 196 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 197 mmio_write_32(base + SDMMC_CMDR, 0); 198 } 199 200 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 201 202 if (cmd->resp_type == 0U) { 203 flags_cmd |= SDMMC_STAR_CMDSENT; 204 } 205 206 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 207 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 208 flags_cmd |= SDMMC_STAR_CMDREND; 209 cmd_reg |= SDMMC_CMDR_WAITRESP; 210 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 211 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 212 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 213 } else { 214 flags_cmd |= SDMMC_STAR_CMDREND; 215 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 216 } 217 } 218 219 switch (cmd->cmd_idx) { 220 case MMC_CMD(1): 221 arg_reg |= OCR_POWERUP; 222 break; 223 case MMC_CMD(8): 224 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 225 cmd_reg |= SDMMC_CMDR_CMDTRANS; 226 } 227 break; 228 case MMC_CMD(12): 229 cmd_reg |= SDMMC_CMDR_CMDSTOP; 230 break; 231 case MMC_CMD(17): 232 case MMC_CMD(18): 233 cmd_reg |= SDMMC_CMDR_CMDTRANS; 234 if (sdmmc2_params.use_dma) { 235 flags_data |= SDMMC_STAR_DCRCFAIL | 236 SDMMC_STAR_DTIMEOUT | 237 SDMMC_STAR_DATAEND | 238 SDMMC_STAR_RXOVERR | 239 SDMMC_STAR_IDMATE; 240 } 241 break; 242 case MMC_ACMD(41): 243 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 244 break; 245 case MMC_ACMD(51): 246 cmd_reg |= SDMMC_CMDR_CMDTRANS; 247 if (sdmmc2_params.use_dma) { 248 flags_data |= SDMMC_STAR_DCRCFAIL | 249 SDMMC_STAR_DTIMEOUT | 250 SDMMC_STAR_DATAEND | 251 SDMMC_STAR_RXOVERR | 252 SDMMC_STAR_IDMATE | 253 SDMMC_STAR_DBCKEND; 254 } 255 break; 256 default: 257 break; 258 } 259 260 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 261 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 262 } 263 264 mmio_write_32(base + SDMMC_ARGR, arg_reg); 265 266 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 267 268 status = mmio_read_32(base + SDMMC_STAR); 269 270 timeout = timeout_init_us(TIMEOUT_US_10_MS); 271 272 while ((status & flags_cmd) == 0U) { 273 if (timeout_elapsed(timeout)) { 274 err = -ETIMEDOUT; 275 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 276 __func__, cmd->cmd_idx, status); 277 goto err_exit; 278 } 279 280 status = mmio_read_32(base + SDMMC_STAR); 281 } 282 283 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 284 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 285 err = -ETIMEDOUT; 286 /* 287 * Those timeouts can occur, and framework will handle 288 * the retries. CMD8 is expected to return this timeout 289 * for eMMC 290 */ 291 if (!((cmd->cmd_idx == MMC_CMD(1)) || 292 (cmd->cmd_idx == MMC_CMD(13)) || 293 ((cmd->cmd_idx == MMC_CMD(8)) && 294 (cmd->resp_type == MMC_RESPONSE_R7)))) { 295 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 296 __func__, cmd->cmd_idx, status); 297 } 298 } else { 299 err = -EIO; 300 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 301 __func__, cmd->cmd_idx, status); 302 } 303 304 goto err_exit; 305 } 306 307 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 308 if ((cmd->cmd_idx == MMC_CMD(9)) && 309 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 310 /* Need to invert response to match CSD structure */ 311 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 312 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 313 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 314 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 315 } else { 316 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 317 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 318 SDMMC_CMDR_WAITRESP) { 319 cmd->resp_data[1] = mmio_read_32(base + 320 SDMMC_RESP2R); 321 cmd->resp_data[2] = mmio_read_32(base + 322 SDMMC_RESP3R); 323 cmd->resp_data[3] = mmio_read_32(base + 324 SDMMC_RESP4R); 325 } 326 } 327 } 328 329 if (flags_data == 0U) { 330 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 331 332 return 0; 333 } 334 335 status = mmio_read_32(base + SDMMC_STAR); 336 337 timeout = timeout_init_us(TIMEOUT_US_10_MS); 338 339 while ((status & flags_data) == 0U) { 340 if (timeout_elapsed(timeout)) { 341 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 342 __func__, cmd->cmd_idx, status); 343 err = -ETIMEDOUT; 344 goto err_exit; 345 } 346 347 status = mmio_read_32(base + SDMMC_STAR); 348 }; 349 350 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 351 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 352 SDMMC_STAR_IDMATE)) != 0U) { 353 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 354 cmd->cmd_idx, status); 355 err = -EIO; 356 } 357 358 err_exit: 359 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 360 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 361 362 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 363 int ret_stop = stm32_sdmmc2_stop_transfer(); 364 365 if (ret_stop != 0) { 366 return ret_stop; 367 } 368 } 369 370 return err; 371 } 372 373 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 374 { 375 int8_t retry; 376 int err = 0; 377 378 assert(cmd != NULL); 379 380 for (retry = 0; retry <= 3; retry++) { 381 err = stm32_sdmmc2_send_cmd_req(cmd); 382 if (err == 0) { 383 return err; 384 } 385 386 if ((cmd->cmd_idx == MMC_CMD(1)) || 387 (cmd->cmd_idx == MMC_CMD(13))) { 388 return 0; /* Retry managed by framework */ 389 } 390 391 /* Command 8 is expected to fail for eMMC */ 392 if (!(cmd->cmd_idx == MMC_CMD(8))) { 393 WARN(" CMD%d, Retry: %d, Error: %d\n", 394 cmd->cmd_idx, retry, err); 395 } 396 397 udelay(10); 398 } 399 400 return err; 401 } 402 403 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 404 { 405 uintptr_t base = sdmmc2_params.reg_base; 406 uint32_t bus_cfg = 0; 407 uint32_t clock_div, max_freq, freq; 408 uint32_t clk_rate = sdmmc2_params.clk_rate; 409 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 410 411 switch (width) { 412 case MMC_BUS_WIDTH_1: 413 break; 414 case MMC_BUS_WIDTH_4: 415 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 416 break; 417 case MMC_BUS_WIDTH_8: 418 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 419 break; 420 default: 421 panic(); 422 break; 423 } 424 425 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 426 if (max_bus_freq >= 52000000U) { 427 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 428 } else { 429 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 430 } 431 } else { 432 if (max_bus_freq >= 50000000U) { 433 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 434 } else { 435 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 436 } 437 } 438 439 if (sdmmc2_params.max_freq != 0U) { 440 freq = MIN(sdmmc2_params.max_freq, max_freq); 441 } else { 442 freq = max_freq; 443 } 444 445 clock_div = div_round_up(clk_rate, freq * 2U); 446 447 mmio_write_32(base + SDMMC_CLKCR, 448 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 449 sdmmc2_params.negedge | 450 sdmmc2_params.pin_ckin); 451 452 return 0; 453 } 454 455 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 456 { 457 struct mmc_cmd cmd; 458 int ret; 459 uintptr_t base = sdmmc2_params.reg_base; 460 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 461 uint32_t arg_size; 462 463 assert(size != 0U); 464 465 if (size > MMC_BLOCK_SIZE) { 466 arg_size = MMC_BLOCK_SIZE; 467 } else { 468 arg_size = size; 469 } 470 471 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 472 473 if (sdmmc2_params.use_dma) { 474 inv_dcache_range(buf, size); 475 } 476 477 /* Prepare CMD 16*/ 478 mmio_write_32(base + SDMMC_DTIMER, 0); 479 480 mmio_write_32(base + SDMMC_DLENR, 0); 481 482 mmio_write_32(base + SDMMC_DCTRLR, 0); 483 484 zeromem(&cmd, sizeof(struct mmc_cmd)); 485 486 cmd.cmd_idx = MMC_CMD(16); 487 cmd.cmd_arg = arg_size; 488 cmd.resp_type = MMC_RESPONSE_R1; 489 490 ret = stm32_sdmmc2_send_cmd(&cmd); 491 if (ret != 0) { 492 ERROR("CMD16 failed\n"); 493 return ret; 494 } 495 496 /* Prepare data command */ 497 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 498 499 mmio_write_32(base + SDMMC_DLENR, size); 500 501 if (sdmmc2_params.use_dma) { 502 mmio_write_32(base + SDMMC_IDMACTRLR, 503 SDMMC_IDMACTRLR_IDMAEN); 504 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 505 506 flush_dcache_range(buf, size); 507 } 508 509 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 510 511 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 512 SDMMC_DCTRLR_CLEAR_MASK, 513 data_ctrl); 514 515 return 0; 516 } 517 518 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 519 { 520 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 521 SDMMC_STAR_DTIMEOUT; 522 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 523 uint32_t status; 524 uint32_t *buffer; 525 uintptr_t base = sdmmc2_params.reg_base; 526 uintptr_t fifo_reg = base + SDMMC_FIFOR; 527 uint64_t timeout; 528 int ret; 529 530 /* Assert buf is 4 bytes aligned */ 531 assert((buf & GENMASK(1, 0)) == 0U); 532 533 buffer = (uint32_t *)buf; 534 535 if (sdmmc2_params.use_dma) { 536 inv_dcache_range(buf, size); 537 538 return 0; 539 } 540 541 if (size <= MMC_BLOCK_SIZE) { 542 flags |= SDMMC_STAR_DBCKEND; 543 } 544 545 timeout = timeout_init_us(TIMEOUT_US_1_S); 546 547 do { 548 status = mmio_read_32(base + SDMMC_STAR); 549 550 if ((status & error_flags) != 0U) { 551 ERROR("%s: Read error (status = %x)\n", __func__, 552 status); 553 mmio_write_32(base + SDMMC_DCTRLR, 554 SDMMC_DCTRLR_FIFORST); 555 556 mmio_write_32(base + SDMMC_ICR, 557 SDMMC_STATIC_FLAGS); 558 559 ret = stm32_sdmmc2_stop_transfer(); 560 if (ret != 0) { 561 return ret; 562 } 563 564 return -EIO; 565 } 566 567 if (timeout_elapsed(timeout)) { 568 ERROR("%s: timeout 1s (status = %x)\n", 569 __func__, status); 570 mmio_write_32(base + SDMMC_ICR, 571 SDMMC_STATIC_FLAGS); 572 573 ret = stm32_sdmmc2_stop_transfer(); 574 if (ret != 0) { 575 return ret; 576 } 577 578 return -ETIMEDOUT; 579 } 580 581 if (size < (8U * sizeof(uint32_t))) { 582 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 583 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 584 *buffer = mmio_read_32(fifo_reg); 585 buffer++; 586 } 587 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 588 uint32_t count; 589 590 /* Read data from SDMMC Rx FIFO */ 591 for (count = 0; count < 8U; count++) { 592 *buffer = mmio_read_32(fifo_reg); 593 buffer++; 594 } 595 } 596 } while ((status & flags) == 0U); 597 598 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 599 600 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 601 WARN("%s: DPSMACT=1, send stop\n", __func__); 602 return stm32_sdmmc2_stop_transfer(); 603 } 604 605 return 0; 606 } 607 608 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 609 { 610 return 0; 611 } 612 613 static int stm32_sdmmc2_dt_get_config(void) 614 { 615 int sdmmc_node; 616 void *fdt = NULL; 617 const fdt32_t *cuint; 618 619 if (fdt_get_address(&fdt) == 0) { 620 return -FDT_ERR_NOTFOUND; 621 } 622 623 if (fdt == NULL) { 624 return -FDT_ERR_NOTFOUND; 625 } 626 627 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 628 629 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 630 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 631 if (cuint == NULL) { 632 continue; 633 } 634 635 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 636 break; 637 } 638 639 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 640 DT_SDMMC2_COMPAT); 641 } 642 643 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 644 return -FDT_ERR_NOTFOUND; 645 } 646 647 if (fdt_get_status(sdmmc_node) == DT_DISABLED) { 648 return -FDT_ERR_NOTFOUND; 649 } 650 651 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 652 return -FDT_ERR_BADVALUE; 653 } 654 655 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 656 if (cuint == NULL) { 657 return -FDT_ERR_NOTFOUND; 658 } 659 660 cuint++; 661 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 662 663 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 664 if (cuint == NULL) { 665 return -FDT_ERR_NOTFOUND; 666 } 667 668 cuint++; 669 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 670 671 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 672 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 673 } 674 675 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 676 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 677 } 678 679 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 680 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 681 } 682 683 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 684 if (cuint != NULL) { 685 switch (fdt32_to_cpu(*cuint)) { 686 case 4: 687 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 688 break; 689 690 case 8: 691 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 692 break; 693 694 default: 695 break; 696 } 697 } 698 699 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 700 if (cuint != NULL) { 701 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 702 } 703 704 return 0; 705 } 706 707 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 708 { 709 return sdmmc2_params.device_info->device_size; 710 } 711 712 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 713 { 714 assert((params != NULL) && 715 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 716 ((params->bus_width == MMC_BUS_WIDTH_1) || 717 (params->bus_width == MMC_BUS_WIDTH_4) || 718 (params->bus_width == MMC_BUS_WIDTH_8))); 719 720 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 721 722 if (stm32_sdmmc2_dt_get_config() != 0) { 723 ERROR("%s: DT error\n", __func__); 724 return -ENOMEM; 725 } 726 727 stm32mp_clk_enable(sdmmc2_params.clock_id); 728 729 stm32mp_reset_assert(sdmmc2_params.reset_id); 730 udelay(2); 731 stm32mp_reset_deassert(sdmmc2_params.reset_id); 732 mdelay(1); 733 734 sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id); 735 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 736 737 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 738 sdmmc2_params.bus_width, sdmmc2_params.flags, 739 sdmmc2_params.device_info); 740 } 741