1 /* 2 * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <common/debug.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32_sdmmc2.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_DIRPOL BIT(4) 54 55 /* SDMMC clock control register */ 56 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 57 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 58 #define SDMMC_CLKCR_NEGEDGE BIT(16) 59 #define SDMMC_CLKCR_HWFC_EN BIT(17) 60 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 61 62 /* SDMMC command register */ 63 #define SDMMC_CMDR_CMDTRANS BIT(6) 64 #define SDMMC_CMDR_CMDSTOP BIT(7) 65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 66 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 67 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 68 #define SDMMC_CMDR_CPSMEN BIT(12) 69 70 /* SDMMC data control register */ 71 #define SDMMC_DCTRLR_DTEN BIT(0) 72 #define SDMMC_DCTRLR_DTDIR BIT(1) 73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 74 #define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4) 75 #define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7) 77 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 78 #define SDMMC_DCTRLR_FIFORST BIT(13) 79 80 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 81 SDMMC_DCTRLR_DTDIR | \ 82 SDMMC_DCTRLR_DTMODE | \ 83 SDMMC_DCTRLR_DBLOCKSIZE) 84 #define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 85 SDMMC_DCTRLR_DBLOCKSIZE_1) 86 #define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 87 SDMMC_DCTRLR_DBLOCKSIZE_3) 88 89 /* SDMMC status register */ 90 #define SDMMC_STAR_CCRCFAIL BIT(0) 91 #define SDMMC_STAR_DCRCFAIL BIT(1) 92 #define SDMMC_STAR_CTIMEOUT BIT(2) 93 #define SDMMC_STAR_DTIMEOUT BIT(3) 94 #define SDMMC_STAR_TXUNDERR BIT(4) 95 #define SDMMC_STAR_RXOVERR BIT(5) 96 #define SDMMC_STAR_CMDREND BIT(6) 97 #define SDMMC_STAR_CMDSENT BIT(7) 98 #define SDMMC_STAR_DATAEND BIT(8) 99 #define SDMMC_STAR_DBCKEND BIT(10) 100 #define SDMMC_STAR_DPSMACT BIT(12) 101 #define SDMMC_STAR_RXFIFOHF BIT(15) 102 #define SDMMC_STAR_RXFIFOE BIT(19) 103 #define SDMMC_STAR_IDMATE BIT(27) 104 #define SDMMC_STAR_IDMABTC BIT(28) 105 106 /* SDMMC DMA control register */ 107 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 108 109 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 110 SDMMC_STAR_DCRCFAIL | \ 111 SDMMC_STAR_CTIMEOUT | \ 112 SDMMC_STAR_DTIMEOUT | \ 113 SDMMC_STAR_TXUNDERR | \ 114 SDMMC_STAR_RXOVERR | \ 115 SDMMC_STAR_CMDREND | \ 116 SDMMC_STAR_CMDSENT | \ 117 SDMMC_STAR_DATAEND | \ 118 SDMMC_STAR_DBCKEND | \ 119 SDMMC_STAR_IDMATE | \ 120 SDMMC_STAR_IDMABTC) 121 122 #define TIMEOUT_US_10_MS 10000U 123 #define TIMEOUT_US_1_S 1000000U 124 125 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 126 127 static void stm32_sdmmc2_init(void); 128 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 129 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 130 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 131 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 132 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 133 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 134 135 static const struct mmc_ops stm32_sdmmc2_ops = { 136 .init = stm32_sdmmc2_init, 137 .send_cmd = stm32_sdmmc2_send_cmd, 138 .set_ios = stm32_sdmmc2_set_ios, 139 .prepare = stm32_sdmmc2_prepare, 140 .read = stm32_sdmmc2_read, 141 .write = stm32_sdmmc2_write, 142 }; 143 144 static struct stm32_sdmmc2_params sdmmc2_params; 145 146 #pragma weak plat_sdmmc2_use_dma 147 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 148 { 149 return false; 150 } 151 152 static void stm32_sdmmc2_init(void) 153 { 154 uint32_t clock_div; 155 uint32_t freq = STM32MP_MMC_INIT_FREQ; 156 uintptr_t base = sdmmc2_params.reg_base; 157 158 if (sdmmc2_params.max_freq != 0U) { 159 freq = MIN(sdmmc2_params.max_freq, freq); 160 } 161 162 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 163 164 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 165 sdmmc2_params.negedge | 166 sdmmc2_params.pin_ckin); 167 168 mmio_write_32(base + SDMMC_POWER, 169 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 170 171 mdelay(1); 172 } 173 174 static int stm32_sdmmc2_stop_transfer(void) 175 { 176 struct mmc_cmd cmd_stop; 177 178 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 179 180 cmd_stop.cmd_idx = MMC_CMD(12); 181 cmd_stop.resp_type = MMC_RESPONSE_R1B; 182 183 return stm32_sdmmc2_send_cmd(&cmd_stop); 184 } 185 186 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 187 { 188 uint64_t timeout; 189 uint32_t flags_cmd, status; 190 uint32_t flags_data = 0; 191 int err = 0; 192 uintptr_t base = sdmmc2_params.reg_base; 193 unsigned int cmd_reg, arg_reg; 194 195 if (cmd == NULL) { 196 return -EINVAL; 197 } 198 199 flags_cmd = SDMMC_STAR_CTIMEOUT; 200 arg_reg = cmd->cmd_arg; 201 202 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 203 mmio_write_32(base + SDMMC_CMDR, 0); 204 } 205 206 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 207 208 if (cmd->resp_type == 0U) { 209 flags_cmd |= SDMMC_STAR_CMDSENT; 210 } 211 212 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 213 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 214 flags_cmd |= SDMMC_STAR_CMDREND; 215 cmd_reg |= SDMMC_CMDR_WAITRESP; 216 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 217 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 218 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 219 } else { 220 flags_cmd |= SDMMC_STAR_CMDREND; 221 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 222 } 223 } 224 225 switch (cmd->cmd_idx) { 226 case MMC_CMD(1): 227 arg_reg |= OCR_POWERUP; 228 break; 229 case MMC_CMD(8): 230 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 231 cmd_reg |= SDMMC_CMDR_CMDTRANS; 232 } 233 break; 234 case MMC_CMD(12): 235 cmd_reg |= SDMMC_CMDR_CMDSTOP; 236 break; 237 case MMC_CMD(17): 238 case MMC_CMD(18): 239 cmd_reg |= SDMMC_CMDR_CMDTRANS; 240 if (sdmmc2_params.use_dma) { 241 flags_data |= SDMMC_STAR_DCRCFAIL | 242 SDMMC_STAR_DTIMEOUT | 243 SDMMC_STAR_DATAEND | 244 SDMMC_STAR_RXOVERR | 245 SDMMC_STAR_IDMATE; 246 } 247 break; 248 case MMC_ACMD(41): 249 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 250 break; 251 case MMC_ACMD(51): 252 cmd_reg |= SDMMC_CMDR_CMDTRANS; 253 if (sdmmc2_params.use_dma) { 254 flags_data |= SDMMC_STAR_DCRCFAIL | 255 SDMMC_STAR_DTIMEOUT | 256 SDMMC_STAR_DATAEND | 257 SDMMC_STAR_RXOVERR | 258 SDMMC_STAR_IDMATE | 259 SDMMC_STAR_DBCKEND; 260 } 261 break; 262 default: 263 break; 264 } 265 266 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 267 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 268 } 269 270 mmio_write_32(base + SDMMC_ARGR, arg_reg); 271 272 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 273 274 status = mmio_read_32(base + SDMMC_STAR); 275 276 timeout = timeout_init_us(TIMEOUT_US_10_MS); 277 278 while ((status & flags_cmd) == 0U) { 279 if (timeout_elapsed(timeout)) { 280 err = -ETIMEDOUT; 281 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 282 __func__, cmd->cmd_idx, status); 283 goto err_exit; 284 } 285 286 status = mmio_read_32(base + SDMMC_STAR); 287 } 288 289 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 290 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 291 err = -ETIMEDOUT; 292 /* 293 * Those timeouts can occur, and framework will handle 294 * the retries. CMD8 is expected to return this timeout 295 * for eMMC 296 */ 297 if (!((cmd->cmd_idx == MMC_CMD(1)) || 298 (cmd->cmd_idx == MMC_CMD(13)) || 299 ((cmd->cmd_idx == MMC_CMD(8)) && 300 (cmd->resp_type == MMC_RESPONSE_R7)))) { 301 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 302 __func__, cmd->cmd_idx, status); 303 } 304 } else { 305 err = -EIO; 306 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 307 __func__, cmd->cmd_idx, status); 308 } 309 310 goto err_exit; 311 } 312 313 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 314 if ((cmd->cmd_idx == MMC_CMD(9)) && 315 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 316 /* Need to invert response to match CSD structure */ 317 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 318 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 319 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 320 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 321 } else { 322 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 323 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 324 SDMMC_CMDR_WAITRESP) { 325 cmd->resp_data[1] = mmio_read_32(base + 326 SDMMC_RESP2R); 327 cmd->resp_data[2] = mmio_read_32(base + 328 SDMMC_RESP3R); 329 cmd->resp_data[3] = mmio_read_32(base + 330 SDMMC_RESP4R); 331 } 332 } 333 } 334 335 if (flags_data == 0U) { 336 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 337 338 return 0; 339 } 340 341 status = mmio_read_32(base + SDMMC_STAR); 342 343 timeout = timeout_init_us(TIMEOUT_US_10_MS); 344 345 while ((status & flags_data) == 0U) { 346 if (timeout_elapsed(timeout)) { 347 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 348 __func__, cmd->cmd_idx, status); 349 err = -ETIMEDOUT; 350 goto err_exit; 351 } 352 353 status = mmio_read_32(base + SDMMC_STAR); 354 }; 355 356 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 357 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 358 SDMMC_STAR_IDMATE)) != 0U) { 359 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 360 cmd->cmd_idx, status); 361 err = -EIO; 362 } 363 364 err_exit: 365 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 366 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 367 368 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 369 int ret_stop = stm32_sdmmc2_stop_transfer(); 370 371 if (ret_stop != 0) { 372 return ret_stop; 373 } 374 } 375 376 return err; 377 } 378 379 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 380 { 381 int8_t retry; 382 int err = 0; 383 384 assert(cmd != NULL); 385 386 for (retry = 0; retry <= 3; retry++) { 387 err = stm32_sdmmc2_send_cmd_req(cmd); 388 if (err == 0) { 389 return err; 390 } 391 392 if ((cmd->cmd_idx == MMC_CMD(1)) || 393 (cmd->cmd_idx == MMC_CMD(13))) { 394 return 0; /* Retry managed by framework */ 395 } 396 397 /* Command 8 is expected to fail for eMMC */ 398 if (!(cmd->cmd_idx == MMC_CMD(8))) { 399 WARN(" CMD%d, Retry: %d, Error: %d\n", 400 cmd->cmd_idx, retry, err); 401 } 402 403 udelay(10); 404 } 405 406 return err; 407 } 408 409 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 410 { 411 uintptr_t base = sdmmc2_params.reg_base; 412 uint32_t bus_cfg = 0; 413 uint32_t clock_div, max_freq, freq; 414 uint32_t clk_rate = sdmmc2_params.clk_rate; 415 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 416 417 switch (width) { 418 case MMC_BUS_WIDTH_1: 419 break; 420 case MMC_BUS_WIDTH_4: 421 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 422 break; 423 case MMC_BUS_WIDTH_8: 424 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 425 break; 426 default: 427 panic(); 428 break; 429 } 430 431 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 432 if (max_bus_freq >= 52000000U) { 433 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 434 } else { 435 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 436 } 437 } else { 438 if (max_bus_freq >= 50000000U) { 439 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 440 } else { 441 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 442 } 443 } 444 445 if (sdmmc2_params.max_freq != 0U) { 446 freq = MIN(sdmmc2_params.max_freq, max_freq); 447 } else { 448 freq = max_freq; 449 } 450 451 clock_div = div_round_up(clk_rate, freq * 2U); 452 453 mmio_write_32(base + SDMMC_CLKCR, 454 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 455 sdmmc2_params.negedge | 456 sdmmc2_params.pin_ckin); 457 458 return 0; 459 } 460 461 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 462 { 463 struct mmc_cmd cmd; 464 int ret; 465 uintptr_t base = sdmmc2_params.reg_base; 466 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 467 468 if (size == 8U) { 469 data_ctrl |= SDMMC_DBLOCKSIZE_8; 470 } else { 471 data_ctrl |= SDMMC_DBLOCKSIZE_512; 472 } 473 474 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 475 476 if (sdmmc2_params.use_dma) { 477 inv_dcache_range(buf, size); 478 } 479 480 /* Prepare CMD 16*/ 481 mmio_write_32(base + SDMMC_DTIMER, 0); 482 483 mmio_write_32(base + SDMMC_DLENR, 0); 484 485 mmio_write_32(base + SDMMC_DCTRLR, 0); 486 487 zeromem(&cmd, sizeof(struct mmc_cmd)); 488 489 cmd.cmd_idx = MMC_CMD(16); 490 if (size > MMC_BLOCK_SIZE) { 491 cmd.cmd_arg = MMC_BLOCK_SIZE; 492 } else { 493 cmd.cmd_arg = size; 494 } 495 496 cmd.resp_type = MMC_RESPONSE_R1; 497 498 ret = stm32_sdmmc2_send_cmd(&cmd); 499 if (ret != 0) { 500 ERROR("CMD16 failed\n"); 501 return ret; 502 } 503 504 /* Prepare data command */ 505 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 506 507 mmio_write_32(base + SDMMC_DLENR, size); 508 509 if (sdmmc2_params.use_dma) { 510 mmio_write_32(base + SDMMC_IDMACTRLR, 511 SDMMC_IDMACTRLR_IDMAEN); 512 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 513 514 flush_dcache_range(buf, size); 515 } 516 517 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 518 SDMMC_DCTRLR_CLEAR_MASK, 519 data_ctrl); 520 521 return 0; 522 } 523 524 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 525 { 526 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 527 SDMMC_STAR_DTIMEOUT; 528 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 529 uint32_t status; 530 uint32_t *buffer; 531 uintptr_t base = sdmmc2_params.reg_base; 532 uintptr_t fifo_reg = base + SDMMC_FIFOR; 533 uint64_t timeout; 534 int ret; 535 536 /* Assert buf is 4 bytes aligned */ 537 assert((buf & GENMASK(1, 0)) == 0U); 538 539 buffer = (uint32_t *)buf; 540 541 if (sdmmc2_params.use_dma) { 542 inv_dcache_range(buf, size); 543 544 return 0; 545 } 546 547 if (size <= MMC_BLOCK_SIZE) { 548 flags |= SDMMC_STAR_DBCKEND; 549 } 550 551 timeout = timeout_init_us(TIMEOUT_US_1_S); 552 553 do { 554 status = mmio_read_32(base + SDMMC_STAR); 555 556 if ((status & error_flags) != 0U) { 557 ERROR("%s: Read error (status = %x)\n", __func__, 558 status); 559 mmio_write_32(base + SDMMC_DCTRLR, 560 SDMMC_DCTRLR_FIFORST); 561 562 mmio_write_32(base + SDMMC_ICR, 563 SDMMC_STATIC_FLAGS); 564 565 ret = stm32_sdmmc2_stop_transfer(); 566 if (ret != 0) { 567 return ret; 568 } 569 570 return -EIO; 571 } 572 573 if (timeout_elapsed(timeout)) { 574 ERROR("%s: timeout 1s (status = %x)\n", 575 __func__, status); 576 mmio_write_32(base + SDMMC_ICR, 577 SDMMC_STATIC_FLAGS); 578 579 ret = stm32_sdmmc2_stop_transfer(); 580 if (ret != 0) { 581 return ret; 582 } 583 584 return -ETIMEDOUT; 585 } 586 587 if (size < (8U * sizeof(uint32_t))) { 588 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 589 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 590 *buffer = mmio_read_32(fifo_reg); 591 buffer++; 592 } 593 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 594 uint32_t count; 595 596 /* Read data from SDMMC Rx FIFO */ 597 for (count = 0; count < 8U; count++) { 598 *buffer = mmio_read_32(fifo_reg); 599 buffer++; 600 } 601 } 602 } while ((status & flags) == 0U); 603 604 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 605 606 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 607 WARN("%s: DPSMACT=1, send stop\n", __func__); 608 return stm32_sdmmc2_stop_transfer(); 609 } 610 611 return 0; 612 } 613 614 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 615 { 616 return 0; 617 } 618 619 static int stm32_sdmmc2_dt_get_config(void) 620 { 621 int sdmmc_node; 622 void *fdt = NULL; 623 const fdt32_t *cuint; 624 625 if (fdt_get_address(&fdt) == 0) { 626 return -FDT_ERR_NOTFOUND; 627 } 628 629 if (fdt == NULL) { 630 return -FDT_ERR_NOTFOUND; 631 } 632 633 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 634 635 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 636 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 637 if (cuint == NULL) { 638 continue; 639 } 640 641 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 642 break; 643 } 644 645 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 646 DT_SDMMC2_COMPAT); 647 } 648 649 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 650 return -FDT_ERR_NOTFOUND; 651 } 652 653 if (fdt_get_status(sdmmc_node) == DT_DISABLED) { 654 return -FDT_ERR_NOTFOUND; 655 } 656 657 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 658 return -FDT_ERR_BADVALUE; 659 } 660 661 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 662 if (cuint == NULL) { 663 return -FDT_ERR_NOTFOUND; 664 } 665 666 cuint++; 667 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 668 669 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 670 if (cuint == NULL) { 671 return -FDT_ERR_NOTFOUND; 672 } 673 674 cuint++; 675 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 676 677 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 678 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 679 } 680 681 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 682 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 683 } 684 685 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 686 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 687 } 688 689 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 690 if (cuint != NULL) { 691 switch (fdt32_to_cpu(*cuint)) { 692 case 4: 693 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 694 break; 695 696 case 8: 697 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 698 break; 699 700 default: 701 break; 702 } 703 } 704 705 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 706 if (cuint != NULL) { 707 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 708 } 709 710 return 0; 711 } 712 713 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 714 { 715 return sdmmc2_params.device_info->device_size; 716 } 717 718 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 719 { 720 assert((params != NULL) && 721 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 722 ((params->bus_width == MMC_BUS_WIDTH_1) || 723 (params->bus_width == MMC_BUS_WIDTH_4) || 724 (params->bus_width == MMC_BUS_WIDTH_8))); 725 726 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 727 728 if (stm32_sdmmc2_dt_get_config() != 0) { 729 ERROR("%s: DT error\n", __func__); 730 return -ENOMEM; 731 } 732 733 stm32mp_clk_enable(sdmmc2_params.clock_id); 734 735 stm32mp_reset_assert(sdmmc2_params.reset_id); 736 udelay(2); 737 stm32mp_reset_deassert(sdmmc2_params.reset_id); 738 mdelay(1); 739 740 sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id); 741 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 742 743 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 744 sdmmc2_params.bus_width, sdmmc2_params.flags, 745 sdmmc2_params.device_info); 746 } 747