1 /* 2 * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <common/debug.h> 18 #include <drivers/clk.h> 19 #include <drivers/delay_timer.h> 20 #include <drivers/mmc.h> 21 #include <drivers/st/stm32_gpio.h> 22 #include <drivers/st/stm32_sdmmc2.h> 23 #include <drivers/st/stm32mp_reset.h> 24 #include <lib/mmio.h> 25 #include <lib/utils.h> 26 #include <plat/common/platform.h> 27 28 /* Registers offsets */ 29 #define SDMMC_POWER 0x00U 30 #define SDMMC_CLKCR 0x04U 31 #define SDMMC_ARGR 0x08U 32 #define SDMMC_CMDR 0x0CU 33 #define SDMMC_RESPCMDR 0x10U 34 #define SDMMC_RESP1R 0x14U 35 #define SDMMC_RESP2R 0x18U 36 #define SDMMC_RESP3R 0x1CU 37 #define SDMMC_RESP4R 0x20U 38 #define SDMMC_DTIMER 0x24U 39 #define SDMMC_DLENR 0x28U 40 #define SDMMC_DCTRLR 0x2CU 41 #define SDMMC_DCNTR 0x30U 42 #define SDMMC_STAR 0x34U 43 #define SDMMC_ICR 0x38U 44 #define SDMMC_MASKR 0x3CU 45 #define SDMMC_ACKTIMER 0x40U 46 #define SDMMC_IDMACTRLR 0x50U 47 #define SDMMC_IDMABSIZER 0x54U 48 #define SDMMC_IDMABASE0R 0x58U 49 #define SDMMC_IDMABASE1R 0x5CU 50 #define SDMMC_FIFOR 0x80U 51 52 /* SDMMC power control register */ 53 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 122 123 static void stm32_sdmmc2_init(void); 124 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 125 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 126 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 127 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 128 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 129 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 130 131 static const struct mmc_ops stm32_sdmmc2_ops = { 132 .init = stm32_sdmmc2_init, 133 .send_cmd = stm32_sdmmc2_send_cmd, 134 .set_ios = stm32_sdmmc2_set_ios, 135 .prepare = stm32_sdmmc2_prepare, 136 .read = stm32_sdmmc2_read, 137 .write = stm32_sdmmc2_write, 138 }; 139 140 static struct stm32_sdmmc2_params sdmmc2_params; 141 142 #pragma weak plat_sdmmc2_use_dma 143 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 144 { 145 return false; 146 } 147 148 static void stm32_sdmmc2_init(void) 149 { 150 uint32_t clock_div; 151 uint32_t freq = STM32MP_MMC_INIT_FREQ; 152 uintptr_t base = sdmmc2_params.reg_base; 153 154 if (sdmmc2_params.max_freq != 0U) { 155 freq = MIN(sdmmc2_params.max_freq, freq); 156 } 157 158 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 159 160 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 161 sdmmc2_params.negedge | 162 sdmmc2_params.pin_ckin); 163 164 mmio_write_32(base + SDMMC_POWER, 165 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 166 167 mdelay(1); 168 } 169 170 static int stm32_sdmmc2_stop_transfer(void) 171 { 172 struct mmc_cmd cmd_stop; 173 174 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 175 176 cmd_stop.cmd_idx = MMC_CMD(12); 177 cmd_stop.resp_type = MMC_RESPONSE_R1B; 178 179 return stm32_sdmmc2_send_cmd(&cmd_stop); 180 } 181 182 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 183 { 184 uint64_t timeout; 185 uint32_t flags_cmd, status; 186 uint32_t flags_data = 0; 187 int err = 0; 188 uintptr_t base = sdmmc2_params.reg_base; 189 unsigned int cmd_reg, arg_reg; 190 191 if (cmd == NULL) { 192 return -EINVAL; 193 } 194 195 flags_cmd = SDMMC_STAR_CTIMEOUT; 196 arg_reg = cmd->cmd_arg; 197 198 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 199 mmio_write_32(base + SDMMC_CMDR, 0); 200 } 201 202 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 203 204 if (cmd->resp_type == 0U) { 205 flags_cmd |= SDMMC_STAR_CMDSENT; 206 } 207 208 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 209 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 210 flags_cmd |= SDMMC_STAR_CMDREND; 211 cmd_reg |= SDMMC_CMDR_WAITRESP; 212 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 213 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 214 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 215 } else { 216 flags_cmd |= SDMMC_STAR_CMDREND; 217 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 218 } 219 } 220 221 switch (cmd->cmd_idx) { 222 case MMC_CMD(1): 223 arg_reg |= OCR_POWERUP; 224 break; 225 case MMC_CMD(8): 226 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 227 cmd_reg |= SDMMC_CMDR_CMDTRANS; 228 } 229 break; 230 case MMC_CMD(12): 231 cmd_reg |= SDMMC_CMDR_CMDSTOP; 232 break; 233 case MMC_CMD(17): 234 case MMC_CMD(18): 235 cmd_reg |= SDMMC_CMDR_CMDTRANS; 236 if (sdmmc2_params.use_dma) { 237 flags_data |= SDMMC_STAR_DCRCFAIL | 238 SDMMC_STAR_DTIMEOUT | 239 SDMMC_STAR_DATAEND | 240 SDMMC_STAR_RXOVERR | 241 SDMMC_STAR_IDMATE; 242 } 243 break; 244 case MMC_ACMD(41): 245 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 246 break; 247 case MMC_ACMD(51): 248 cmd_reg |= SDMMC_CMDR_CMDTRANS; 249 if (sdmmc2_params.use_dma) { 250 flags_data |= SDMMC_STAR_DCRCFAIL | 251 SDMMC_STAR_DTIMEOUT | 252 SDMMC_STAR_DATAEND | 253 SDMMC_STAR_RXOVERR | 254 SDMMC_STAR_IDMATE | 255 SDMMC_STAR_DBCKEND; 256 } 257 break; 258 default: 259 break; 260 } 261 262 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 263 264 /* 265 * Clear the SDMMC_DCTRLR if the command does not await data. 266 * Skip CMD55 as the next command could be data related, and 267 * the register could have been set in prepare function. 268 */ 269 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && 270 (cmd->cmd_idx != MMC_CMD(55))) { 271 mmio_write_32(base + SDMMC_DCTRLR, 0U); 272 } 273 274 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 275 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 276 } 277 278 mmio_write_32(base + SDMMC_ARGR, arg_reg); 279 280 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 281 282 status = mmio_read_32(base + SDMMC_STAR); 283 284 timeout = timeout_init_us(TIMEOUT_US_10_MS); 285 286 while ((status & flags_cmd) == 0U) { 287 if (timeout_elapsed(timeout)) { 288 err = -ETIMEDOUT; 289 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 290 __func__, cmd->cmd_idx, status); 291 goto err_exit; 292 } 293 294 status = mmio_read_32(base + SDMMC_STAR); 295 } 296 297 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 298 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 299 err = -ETIMEDOUT; 300 /* 301 * Those timeouts can occur, and framework will handle 302 * the retries. CMD8 is expected to return this timeout 303 * for eMMC 304 */ 305 if (!((cmd->cmd_idx == MMC_CMD(1)) || 306 (cmd->cmd_idx == MMC_CMD(13)) || 307 ((cmd->cmd_idx == MMC_CMD(8)) && 308 (cmd->resp_type == MMC_RESPONSE_R7)))) { 309 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 310 __func__, cmd->cmd_idx, status); 311 } 312 } else { 313 err = -EIO; 314 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 315 __func__, cmd->cmd_idx, status); 316 } 317 318 goto err_exit; 319 } 320 321 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 322 if ((cmd->cmd_idx == MMC_CMD(9)) && 323 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 324 /* Need to invert response to match CSD structure */ 325 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 326 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 327 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 328 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 329 } else { 330 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 331 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 332 SDMMC_CMDR_WAITRESP) { 333 cmd->resp_data[1] = mmio_read_32(base + 334 SDMMC_RESP2R); 335 cmd->resp_data[2] = mmio_read_32(base + 336 SDMMC_RESP3R); 337 cmd->resp_data[3] = mmio_read_32(base + 338 SDMMC_RESP4R); 339 } 340 } 341 } 342 343 if (flags_data == 0U) { 344 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 345 346 return 0; 347 } 348 349 status = mmio_read_32(base + SDMMC_STAR); 350 351 timeout = timeout_init_us(TIMEOUT_US_10_MS); 352 353 while ((status & flags_data) == 0U) { 354 if (timeout_elapsed(timeout)) { 355 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 356 __func__, cmd->cmd_idx, status); 357 err = -ETIMEDOUT; 358 goto err_exit; 359 } 360 361 status = mmio_read_32(base + SDMMC_STAR); 362 }; 363 364 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 365 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 366 SDMMC_STAR_IDMATE)) != 0U) { 367 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 368 cmd->cmd_idx, status); 369 err = -EIO; 370 } 371 372 err_exit: 373 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 374 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 375 376 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 377 int ret_stop = stm32_sdmmc2_stop_transfer(); 378 379 if (ret_stop != 0) { 380 return ret_stop; 381 } 382 } 383 384 return err; 385 } 386 387 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 388 { 389 uint8_t retry; 390 int err; 391 392 assert(cmd != NULL); 393 394 for (retry = 0U; retry < 3U; retry++) { 395 err = stm32_sdmmc2_send_cmd_req(cmd); 396 if (err == 0) { 397 return 0; 398 } 399 400 if ((cmd->cmd_idx == MMC_CMD(1)) || 401 (cmd->cmd_idx == MMC_CMD(13))) { 402 return 0; /* Retry managed by framework */ 403 } 404 405 /* Command 8 is expected to fail for eMMC */ 406 if (cmd->cmd_idx != MMC_CMD(8)) { 407 WARN(" CMD%u, Retry: %u, Error: %d\n", 408 cmd->cmd_idx, retry + 1U, err); 409 } 410 411 udelay(10U); 412 } 413 414 return err; 415 } 416 417 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 418 { 419 uintptr_t base = sdmmc2_params.reg_base; 420 uint32_t bus_cfg = 0; 421 uint32_t clock_div, max_freq, freq; 422 uint32_t clk_rate = sdmmc2_params.clk_rate; 423 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 424 425 switch (width) { 426 case MMC_BUS_WIDTH_1: 427 break; 428 case MMC_BUS_WIDTH_4: 429 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 430 break; 431 case MMC_BUS_WIDTH_8: 432 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 433 break; 434 default: 435 panic(); 436 break; 437 } 438 439 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 440 if (max_bus_freq >= 52000000U) { 441 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 442 } else { 443 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 444 } 445 } else { 446 if (max_bus_freq >= 50000000U) { 447 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 448 } else { 449 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 450 } 451 } 452 453 if (sdmmc2_params.max_freq != 0U) { 454 freq = MIN(sdmmc2_params.max_freq, max_freq); 455 } else { 456 freq = max_freq; 457 } 458 459 clock_div = div_round_up(clk_rate, freq * 2U); 460 461 mmio_write_32(base + SDMMC_CLKCR, 462 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 463 sdmmc2_params.negedge | 464 sdmmc2_params.pin_ckin); 465 466 return 0; 467 } 468 469 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 470 { 471 struct mmc_cmd cmd; 472 int ret; 473 uintptr_t base = sdmmc2_params.reg_base; 474 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 475 uint32_t arg_size; 476 477 assert(size != 0U); 478 479 if (size > MMC_BLOCK_SIZE) { 480 arg_size = MMC_BLOCK_SIZE; 481 } else { 482 arg_size = size; 483 } 484 485 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 486 487 if (sdmmc2_params.use_dma) { 488 inv_dcache_range(buf, size); 489 } 490 491 /* Prepare CMD 16*/ 492 mmio_write_32(base + SDMMC_DTIMER, 0); 493 494 mmio_write_32(base + SDMMC_DLENR, 0); 495 496 mmio_write_32(base + SDMMC_DCTRLR, 0); 497 498 zeromem(&cmd, sizeof(struct mmc_cmd)); 499 500 cmd.cmd_idx = MMC_CMD(16); 501 cmd.cmd_arg = arg_size; 502 cmd.resp_type = MMC_RESPONSE_R1; 503 504 ret = stm32_sdmmc2_send_cmd(&cmd); 505 if (ret != 0) { 506 ERROR("CMD16 failed\n"); 507 return ret; 508 } 509 510 /* Prepare data command */ 511 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 512 513 mmio_write_32(base + SDMMC_DLENR, size); 514 515 if (sdmmc2_params.use_dma) { 516 mmio_write_32(base + SDMMC_IDMACTRLR, 517 SDMMC_IDMACTRLR_IDMAEN); 518 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 519 520 flush_dcache_range(buf, size); 521 } 522 523 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 524 525 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 526 SDMMC_DCTRLR_CLEAR_MASK, 527 data_ctrl); 528 529 return 0; 530 } 531 532 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 533 { 534 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 535 SDMMC_STAR_DTIMEOUT; 536 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 537 uint32_t status; 538 uint32_t *buffer; 539 uintptr_t base = sdmmc2_params.reg_base; 540 uintptr_t fifo_reg = base + SDMMC_FIFOR; 541 uint64_t timeout; 542 int ret; 543 544 /* Assert buf is 4 bytes aligned */ 545 assert((buf & GENMASK(1, 0)) == 0U); 546 547 buffer = (uint32_t *)buf; 548 549 if (sdmmc2_params.use_dma) { 550 inv_dcache_range(buf, size); 551 552 return 0; 553 } 554 555 if (size <= MMC_BLOCK_SIZE) { 556 flags |= SDMMC_STAR_DBCKEND; 557 } 558 559 timeout = timeout_init_us(TIMEOUT_US_1_S); 560 561 do { 562 status = mmio_read_32(base + SDMMC_STAR); 563 564 if ((status & error_flags) != 0U) { 565 ERROR("%s: Read error (status = %x)\n", __func__, 566 status); 567 mmio_write_32(base + SDMMC_DCTRLR, 568 SDMMC_DCTRLR_FIFORST); 569 570 mmio_write_32(base + SDMMC_ICR, 571 SDMMC_STATIC_FLAGS); 572 573 ret = stm32_sdmmc2_stop_transfer(); 574 if (ret != 0) { 575 return ret; 576 } 577 578 return -EIO; 579 } 580 581 if (timeout_elapsed(timeout)) { 582 ERROR("%s: timeout 1s (status = %x)\n", 583 __func__, status); 584 mmio_write_32(base + SDMMC_ICR, 585 SDMMC_STATIC_FLAGS); 586 587 ret = stm32_sdmmc2_stop_transfer(); 588 if (ret != 0) { 589 return ret; 590 } 591 592 return -ETIMEDOUT; 593 } 594 595 if (size < (8U * sizeof(uint32_t))) { 596 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 597 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 598 *buffer = mmio_read_32(fifo_reg); 599 buffer++; 600 } 601 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 602 uint32_t count; 603 604 /* Read data from SDMMC Rx FIFO */ 605 for (count = 0; count < 8U; count++) { 606 *buffer = mmio_read_32(fifo_reg); 607 buffer++; 608 } 609 } 610 } while ((status & flags) == 0U); 611 612 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 613 614 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 615 WARN("%s: DPSMACT=1, send stop\n", __func__); 616 return stm32_sdmmc2_stop_transfer(); 617 } 618 619 return 0; 620 } 621 622 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 623 { 624 return 0; 625 } 626 627 static int stm32_sdmmc2_dt_get_config(void) 628 { 629 int sdmmc_node; 630 void *fdt = NULL; 631 const fdt32_t *cuint; 632 struct dt_node_info dt_info; 633 634 if (fdt_get_address(&fdt) == 0) { 635 return -FDT_ERR_NOTFOUND; 636 } 637 638 if (fdt == NULL) { 639 return -FDT_ERR_NOTFOUND; 640 } 641 642 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 643 sdmmc2_params.reg_base); 644 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 645 return -FDT_ERR_NOTFOUND; 646 } 647 648 dt_fill_device_info(&dt_info, sdmmc_node); 649 if (dt_info.status == DT_DISABLED) { 650 return -FDT_ERR_NOTFOUND; 651 } 652 653 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 654 return -FDT_ERR_BADVALUE; 655 } 656 657 sdmmc2_params.clock_id = dt_info.clock; 658 sdmmc2_params.reset_id = dt_info.reset; 659 660 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 661 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 662 } 663 664 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 665 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 666 } 667 668 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 669 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 670 } 671 672 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 673 if (cuint != NULL) { 674 switch (fdt32_to_cpu(*cuint)) { 675 case 4: 676 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 677 break; 678 679 case 8: 680 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 681 break; 682 683 default: 684 break; 685 } 686 } 687 688 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 689 if (cuint != NULL) { 690 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 691 } 692 693 return 0; 694 } 695 696 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 697 { 698 return sdmmc2_params.device_info->device_size; 699 } 700 701 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 702 { 703 int rc; 704 705 assert((params != NULL) && 706 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 707 ((params->bus_width == MMC_BUS_WIDTH_1) || 708 (params->bus_width == MMC_BUS_WIDTH_4) || 709 (params->bus_width == MMC_BUS_WIDTH_8))); 710 711 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 712 713 if (stm32_sdmmc2_dt_get_config() != 0) { 714 ERROR("%s: DT error\n", __func__); 715 return -ENOMEM; 716 } 717 718 clk_enable(sdmmc2_params.clock_id); 719 720 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 721 if (rc != 0) { 722 panic(); 723 } 724 udelay(2); 725 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 726 if (rc != 0) { 727 panic(); 728 } 729 mdelay(1); 730 731 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 732 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 733 734 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 735 sdmmc2_params.bus_width, sdmmc2_params.flags, 736 sdmmc2_params.device_info); 737 } 738