1 /* 2 * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <common/debug.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32_sdmmc2.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_DIRPOL BIT(4) 54 55 /* SDMMC clock control register */ 56 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 57 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 58 #define SDMMC_CLKCR_NEGEDGE BIT(16) 59 #define SDMMC_CLKCR_HWFC_EN BIT(17) 60 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 61 62 /* SDMMC command register */ 63 #define SDMMC_CMDR_CMDTRANS BIT(6) 64 #define SDMMC_CMDR_CMDSTOP BIT(7) 65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 66 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 67 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 68 #define SDMMC_CMDR_CPSMEN BIT(12) 69 70 /* SDMMC data control register */ 71 #define SDMMC_DCTRLR_DTEN BIT(0) 72 #define SDMMC_DCTRLR_DTDIR BIT(1) 73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 74 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 75 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 76 #define SDMMC_DCTRLR_FIFORST BIT(13) 77 78 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 79 SDMMC_DCTRLR_DTDIR | \ 80 SDMMC_DCTRLR_DTMODE | \ 81 SDMMC_DCTRLR_DBLOCKSIZE) 82 83 /* SDMMC status register */ 84 #define SDMMC_STAR_CCRCFAIL BIT(0) 85 #define SDMMC_STAR_DCRCFAIL BIT(1) 86 #define SDMMC_STAR_CTIMEOUT BIT(2) 87 #define SDMMC_STAR_DTIMEOUT BIT(3) 88 #define SDMMC_STAR_TXUNDERR BIT(4) 89 #define SDMMC_STAR_RXOVERR BIT(5) 90 #define SDMMC_STAR_CMDREND BIT(6) 91 #define SDMMC_STAR_CMDSENT BIT(7) 92 #define SDMMC_STAR_DATAEND BIT(8) 93 #define SDMMC_STAR_DBCKEND BIT(10) 94 #define SDMMC_STAR_DPSMACT BIT(12) 95 #define SDMMC_STAR_RXFIFOHF BIT(15) 96 #define SDMMC_STAR_RXFIFOE BIT(19) 97 #define SDMMC_STAR_IDMATE BIT(27) 98 #define SDMMC_STAR_IDMABTC BIT(28) 99 100 /* SDMMC DMA control register */ 101 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 102 103 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 104 SDMMC_STAR_DCRCFAIL | \ 105 SDMMC_STAR_CTIMEOUT | \ 106 SDMMC_STAR_DTIMEOUT | \ 107 SDMMC_STAR_TXUNDERR | \ 108 SDMMC_STAR_RXOVERR | \ 109 SDMMC_STAR_CMDREND | \ 110 SDMMC_STAR_CMDSENT | \ 111 SDMMC_STAR_DATAEND | \ 112 SDMMC_STAR_DBCKEND | \ 113 SDMMC_STAR_IDMATE | \ 114 SDMMC_STAR_IDMABTC) 115 116 #define TIMEOUT_US_1_MS 1000U 117 #define TIMEOUT_US_10_MS 10000U 118 #define TIMEOUT_US_1_S 1000000U 119 120 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 121 122 static void stm32_sdmmc2_init(void); 123 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 124 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 125 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 126 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 127 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 128 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 129 130 static const struct mmc_ops stm32_sdmmc2_ops = { 131 .init = stm32_sdmmc2_init, 132 .send_cmd = stm32_sdmmc2_send_cmd, 133 .set_ios = stm32_sdmmc2_set_ios, 134 .prepare = stm32_sdmmc2_prepare, 135 .read = stm32_sdmmc2_read, 136 .write = stm32_sdmmc2_write, 137 }; 138 139 static struct stm32_sdmmc2_params sdmmc2_params; 140 141 #pragma weak plat_sdmmc2_use_dma 142 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 143 { 144 return false; 145 } 146 147 static void stm32_sdmmc2_init(void) 148 { 149 uint32_t clock_div; 150 uint32_t freq = STM32MP_MMC_INIT_FREQ; 151 uintptr_t base = sdmmc2_params.reg_base; 152 153 if (sdmmc2_params.max_freq != 0U) { 154 freq = MIN(sdmmc2_params.max_freq, freq); 155 } 156 157 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 158 159 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 160 sdmmc2_params.negedge | 161 sdmmc2_params.pin_ckin); 162 163 mmio_write_32(base + SDMMC_POWER, 164 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 165 166 mdelay(1); 167 } 168 169 static int stm32_sdmmc2_stop_transfer(void) 170 { 171 struct mmc_cmd cmd_stop; 172 173 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 174 175 cmd_stop.cmd_idx = MMC_CMD(12); 176 cmd_stop.resp_type = MMC_RESPONSE_R1B; 177 178 return stm32_sdmmc2_send_cmd(&cmd_stop); 179 } 180 181 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 182 { 183 uint64_t timeout; 184 uint32_t flags_cmd, status; 185 uint32_t flags_data = 0; 186 int err = 0; 187 uintptr_t base = sdmmc2_params.reg_base; 188 unsigned int cmd_reg, arg_reg; 189 190 if (cmd == NULL) { 191 return -EINVAL; 192 } 193 194 flags_cmd = SDMMC_STAR_CTIMEOUT; 195 arg_reg = cmd->cmd_arg; 196 197 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 198 mmio_write_32(base + SDMMC_CMDR, 0); 199 } 200 201 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 202 203 if (cmd->resp_type == 0U) { 204 flags_cmd |= SDMMC_STAR_CMDSENT; 205 } 206 207 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 208 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 209 flags_cmd |= SDMMC_STAR_CMDREND; 210 cmd_reg |= SDMMC_CMDR_WAITRESP; 211 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 212 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 213 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 214 } else { 215 flags_cmd |= SDMMC_STAR_CMDREND; 216 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 217 } 218 } 219 220 switch (cmd->cmd_idx) { 221 case MMC_CMD(1): 222 arg_reg |= OCR_POWERUP; 223 break; 224 case MMC_CMD(8): 225 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 226 cmd_reg |= SDMMC_CMDR_CMDTRANS; 227 } 228 break; 229 case MMC_CMD(12): 230 cmd_reg |= SDMMC_CMDR_CMDSTOP; 231 break; 232 case MMC_CMD(17): 233 case MMC_CMD(18): 234 cmd_reg |= SDMMC_CMDR_CMDTRANS; 235 if (sdmmc2_params.use_dma) { 236 flags_data |= SDMMC_STAR_DCRCFAIL | 237 SDMMC_STAR_DTIMEOUT | 238 SDMMC_STAR_DATAEND | 239 SDMMC_STAR_RXOVERR | 240 SDMMC_STAR_IDMATE; 241 } 242 break; 243 case MMC_ACMD(41): 244 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 245 break; 246 case MMC_ACMD(51): 247 cmd_reg |= SDMMC_CMDR_CMDTRANS; 248 if (sdmmc2_params.use_dma) { 249 flags_data |= SDMMC_STAR_DCRCFAIL | 250 SDMMC_STAR_DTIMEOUT | 251 SDMMC_STAR_DATAEND | 252 SDMMC_STAR_RXOVERR | 253 SDMMC_STAR_IDMATE | 254 SDMMC_STAR_DBCKEND; 255 } 256 break; 257 default: 258 break; 259 } 260 261 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 262 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 263 } 264 265 mmio_write_32(base + SDMMC_ARGR, arg_reg); 266 267 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 268 269 status = mmio_read_32(base + SDMMC_STAR); 270 271 timeout = timeout_init_us(TIMEOUT_US_10_MS); 272 273 while ((status & flags_cmd) == 0U) { 274 if (timeout_elapsed(timeout)) { 275 err = -ETIMEDOUT; 276 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 277 __func__, cmd->cmd_idx, status); 278 goto err_exit; 279 } 280 281 status = mmio_read_32(base + SDMMC_STAR); 282 } 283 284 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 285 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 286 err = -ETIMEDOUT; 287 /* 288 * Those timeouts can occur, and framework will handle 289 * the retries. CMD8 is expected to return this timeout 290 * for eMMC 291 */ 292 if (!((cmd->cmd_idx == MMC_CMD(1)) || 293 (cmd->cmd_idx == MMC_CMD(13)) || 294 ((cmd->cmd_idx == MMC_CMD(8)) && 295 (cmd->resp_type == MMC_RESPONSE_R7)))) { 296 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 297 __func__, cmd->cmd_idx, status); 298 } 299 } else { 300 err = -EIO; 301 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 302 __func__, cmd->cmd_idx, status); 303 } 304 305 goto err_exit; 306 } 307 308 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 309 if ((cmd->cmd_idx == MMC_CMD(9)) && 310 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 311 /* Need to invert response to match CSD structure */ 312 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 313 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 314 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 315 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 316 } else { 317 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 318 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 319 SDMMC_CMDR_WAITRESP) { 320 cmd->resp_data[1] = mmio_read_32(base + 321 SDMMC_RESP2R); 322 cmd->resp_data[2] = mmio_read_32(base + 323 SDMMC_RESP3R); 324 cmd->resp_data[3] = mmio_read_32(base + 325 SDMMC_RESP4R); 326 } 327 } 328 } 329 330 if (flags_data == 0U) { 331 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 332 333 return 0; 334 } 335 336 status = mmio_read_32(base + SDMMC_STAR); 337 338 timeout = timeout_init_us(TIMEOUT_US_10_MS); 339 340 while ((status & flags_data) == 0U) { 341 if (timeout_elapsed(timeout)) { 342 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 343 __func__, cmd->cmd_idx, status); 344 err = -ETIMEDOUT; 345 goto err_exit; 346 } 347 348 status = mmio_read_32(base + SDMMC_STAR); 349 }; 350 351 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 352 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 353 SDMMC_STAR_IDMATE)) != 0U) { 354 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 355 cmd->cmd_idx, status); 356 err = -EIO; 357 } 358 359 err_exit: 360 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 361 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 362 363 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 364 int ret_stop = stm32_sdmmc2_stop_transfer(); 365 366 if (ret_stop != 0) { 367 return ret_stop; 368 } 369 } 370 371 return err; 372 } 373 374 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 375 { 376 int8_t retry; 377 int err = 0; 378 379 assert(cmd != NULL); 380 381 for (retry = 0; retry <= 3; retry++) { 382 err = stm32_sdmmc2_send_cmd_req(cmd); 383 if (err == 0) { 384 return err; 385 } 386 387 if ((cmd->cmd_idx == MMC_CMD(1)) || 388 (cmd->cmd_idx == MMC_CMD(13))) { 389 return 0; /* Retry managed by framework */ 390 } 391 392 /* Command 8 is expected to fail for eMMC */ 393 if (!(cmd->cmd_idx == MMC_CMD(8))) { 394 WARN(" CMD%d, Retry: %d, Error: %d\n", 395 cmd->cmd_idx, retry, err); 396 } 397 398 udelay(10); 399 } 400 401 return err; 402 } 403 404 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 405 { 406 uintptr_t base = sdmmc2_params.reg_base; 407 uint32_t bus_cfg = 0; 408 uint32_t clock_div, max_freq, freq; 409 uint32_t clk_rate = sdmmc2_params.clk_rate; 410 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 411 412 switch (width) { 413 case MMC_BUS_WIDTH_1: 414 break; 415 case MMC_BUS_WIDTH_4: 416 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 417 break; 418 case MMC_BUS_WIDTH_8: 419 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 420 break; 421 default: 422 panic(); 423 break; 424 } 425 426 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 427 if (max_bus_freq >= 52000000U) { 428 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 429 } else { 430 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 431 } 432 } else { 433 if (max_bus_freq >= 50000000U) { 434 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 435 } else { 436 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 437 } 438 } 439 440 if (sdmmc2_params.max_freq != 0U) { 441 freq = MIN(sdmmc2_params.max_freq, max_freq); 442 } else { 443 freq = max_freq; 444 } 445 446 clock_div = div_round_up(clk_rate, freq * 2U); 447 448 mmio_write_32(base + SDMMC_CLKCR, 449 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 450 sdmmc2_params.negedge | 451 sdmmc2_params.pin_ckin); 452 453 return 0; 454 } 455 456 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 457 { 458 struct mmc_cmd cmd; 459 int ret; 460 uintptr_t base = sdmmc2_params.reg_base; 461 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 462 uint32_t arg_size; 463 464 assert(size != 0U); 465 466 if (size > MMC_BLOCK_SIZE) { 467 arg_size = MMC_BLOCK_SIZE; 468 } else { 469 arg_size = size; 470 } 471 472 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 473 474 if (sdmmc2_params.use_dma) { 475 inv_dcache_range(buf, size); 476 } 477 478 /* Prepare CMD 16*/ 479 mmio_write_32(base + SDMMC_DTIMER, 0); 480 481 mmio_write_32(base + SDMMC_DLENR, 0); 482 483 mmio_write_32(base + SDMMC_DCTRLR, 0); 484 485 zeromem(&cmd, sizeof(struct mmc_cmd)); 486 487 cmd.cmd_idx = MMC_CMD(16); 488 cmd.cmd_arg = arg_size; 489 cmd.resp_type = MMC_RESPONSE_R1; 490 491 ret = stm32_sdmmc2_send_cmd(&cmd); 492 if (ret != 0) { 493 ERROR("CMD16 failed\n"); 494 return ret; 495 } 496 497 /* Prepare data command */ 498 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 499 500 mmio_write_32(base + SDMMC_DLENR, size); 501 502 if (sdmmc2_params.use_dma) { 503 mmio_write_32(base + SDMMC_IDMACTRLR, 504 SDMMC_IDMACTRLR_IDMAEN); 505 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 506 507 flush_dcache_range(buf, size); 508 } 509 510 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 511 512 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 513 SDMMC_DCTRLR_CLEAR_MASK, 514 data_ctrl); 515 516 return 0; 517 } 518 519 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 520 { 521 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 522 SDMMC_STAR_DTIMEOUT; 523 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 524 uint32_t status; 525 uint32_t *buffer; 526 uintptr_t base = sdmmc2_params.reg_base; 527 uintptr_t fifo_reg = base + SDMMC_FIFOR; 528 uint64_t timeout; 529 int ret; 530 531 /* Assert buf is 4 bytes aligned */ 532 assert((buf & GENMASK(1, 0)) == 0U); 533 534 buffer = (uint32_t *)buf; 535 536 if (sdmmc2_params.use_dma) { 537 inv_dcache_range(buf, size); 538 539 return 0; 540 } 541 542 if (size <= MMC_BLOCK_SIZE) { 543 flags |= SDMMC_STAR_DBCKEND; 544 } 545 546 timeout = timeout_init_us(TIMEOUT_US_1_S); 547 548 do { 549 status = mmio_read_32(base + SDMMC_STAR); 550 551 if ((status & error_flags) != 0U) { 552 ERROR("%s: Read error (status = %x)\n", __func__, 553 status); 554 mmio_write_32(base + SDMMC_DCTRLR, 555 SDMMC_DCTRLR_FIFORST); 556 557 mmio_write_32(base + SDMMC_ICR, 558 SDMMC_STATIC_FLAGS); 559 560 ret = stm32_sdmmc2_stop_transfer(); 561 if (ret != 0) { 562 return ret; 563 } 564 565 return -EIO; 566 } 567 568 if (timeout_elapsed(timeout)) { 569 ERROR("%s: timeout 1s (status = %x)\n", 570 __func__, status); 571 mmio_write_32(base + SDMMC_ICR, 572 SDMMC_STATIC_FLAGS); 573 574 ret = stm32_sdmmc2_stop_transfer(); 575 if (ret != 0) { 576 return ret; 577 } 578 579 return -ETIMEDOUT; 580 } 581 582 if (size < (8U * sizeof(uint32_t))) { 583 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 584 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 585 *buffer = mmio_read_32(fifo_reg); 586 buffer++; 587 } 588 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 589 uint32_t count; 590 591 /* Read data from SDMMC Rx FIFO */ 592 for (count = 0; count < 8U; count++) { 593 *buffer = mmio_read_32(fifo_reg); 594 buffer++; 595 } 596 } 597 } while ((status & flags) == 0U); 598 599 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 600 601 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 602 WARN("%s: DPSMACT=1, send stop\n", __func__); 603 return stm32_sdmmc2_stop_transfer(); 604 } 605 606 return 0; 607 } 608 609 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 610 { 611 return 0; 612 } 613 614 static int stm32_sdmmc2_dt_get_config(void) 615 { 616 int sdmmc_node; 617 void *fdt = NULL; 618 const fdt32_t *cuint; 619 620 if (fdt_get_address(&fdt) == 0) { 621 return -FDT_ERR_NOTFOUND; 622 } 623 624 if (fdt == NULL) { 625 return -FDT_ERR_NOTFOUND; 626 } 627 628 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 629 630 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 631 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 632 if (cuint == NULL) { 633 continue; 634 } 635 636 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 637 break; 638 } 639 640 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 641 DT_SDMMC2_COMPAT); 642 } 643 644 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 645 return -FDT_ERR_NOTFOUND; 646 } 647 648 if (fdt_get_status(sdmmc_node) == DT_DISABLED) { 649 return -FDT_ERR_NOTFOUND; 650 } 651 652 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 653 return -FDT_ERR_BADVALUE; 654 } 655 656 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 657 if (cuint == NULL) { 658 return -FDT_ERR_NOTFOUND; 659 } 660 661 cuint++; 662 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 663 664 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 665 if (cuint == NULL) { 666 return -FDT_ERR_NOTFOUND; 667 } 668 669 cuint++; 670 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 671 672 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 673 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 674 } 675 676 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 677 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 678 } 679 680 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 681 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 682 } 683 684 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 685 if (cuint != NULL) { 686 switch (fdt32_to_cpu(*cuint)) { 687 case 4: 688 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 689 break; 690 691 case 8: 692 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 693 break; 694 695 default: 696 break; 697 } 698 } 699 700 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 701 if (cuint != NULL) { 702 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 703 } 704 705 return 0; 706 } 707 708 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 709 { 710 return sdmmc2_params.device_info->device_size; 711 } 712 713 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 714 { 715 int rc; 716 717 assert((params != NULL) && 718 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 719 ((params->bus_width == MMC_BUS_WIDTH_1) || 720 (params->bus_width == MMC_BUS_WIDTH_4) || 721 (params->bus_width == MMC_BUS_WIDTH_8))); 722 723 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 724 725 if (stm32_sdmmc2_dt_get_config() != 0) { 726 ERROR("%s: DT error\n", __func__); 727 return -ENOMEM; 728 } 729 730 stm32mp_clk_enable(sdmmc2_params.clock_id); 731 732 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 733 if (rc != 0) { 734 panic(); 735 } 736 udelay(2); 737 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 738 if (rc != 0) { 739 panic(); 740 } 741 mdelay(1); 742 743 sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id); 744 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 745 746 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 747 sdmmc2_params.bus_width, sdmmc2_params.flags, 748 sdmmc2_params.device_info); 749 } 750