1 /* 2 * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/raw_nand.h> 19 #include <drivers/st/stm32_fmc2_nand.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32mp_reset.h> 22 #include <lib/mmio.h> 23 #include <lib/utils_def.h> 24 25 /* Timeout for device interface reset */ 26 #define TIMEOUT_US_1_MS 1000U 27 28 /* FMC2 Compatibility */ 29 #define DT_FMC2_COMPAT "st,stm32mp15-fmc2" 30 #define MAX_CS 2U 31 32 /* FMC2 Controller Registers */ 33 #define FMC2_BCR1 0x00U 34 #define FMC2_PCR 0x80U 35 #define FMC2_SR 0x84U 36 #define FMC2_PMEM 0x88U 37 #define FMC2_PATT 0x8CU 38 #define FMC2_HECCR 0x94U 39 #define FMC2_BCHISR 0x254U 40 #define FMC2_BCHICR 0x258U 41 #define FMC2_BCHDSR0 0x27CU 42 #define FMC2_BCHDSR1 0x280U 43 #define FMC2_BCHDSR2 0x284U 44 #define FMC2_BCHDSR3 0x288U 45 #define FMC2_BCHDSR4 0x28CU 46 47 /* FMC2_BCR1 register */ 48 #define FMC2_BCR1_FMC2EN BIT(31) 49 /* FMC2_PCR register */ 50 #define FMC2_PCR_PWAITEN BIT(1) 51 #define FMC2_PCR_PBKEN BIT(2) 52 #define FMC2_PCR_PWID_MASK GENMASK_32(5, 4) 53 #define FMC2_PCR_PWID(x) (((x) << 4) & FMC2_PCR_PWID_MASK) 54 #define FMC2_PCR_PWID_8 0x0U 55 #define FMC2_PCR_PWID_16 0x1U 56 #define FMC2_PCR_ECCEN BIT(6) 57 #define FMC2_PCR_ECCALG BIT(8) 58 #define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9) 59 #define FMC2_PCR_TCLR(x) (((x) << 9) & FMC2_PCR_TCLR_MASK) 60 #define FMC2_PCR_TCLR_DEFAULT 0xFU 61 #define FMC2_PCR_TAR_MASK GENMASK_32(16, 13) 62 #define FMC2_PCR_TAR(x) (((x) << 13) & FMC2_PCR_TAR_MASK) 63 #define FMC2_PCR_TAR_DEFAULT 0xFU 64 #define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17) 65 #define FMC2_PCR_ECCSS(x) (((x) << 17) & FMC2_PCR_ECCSS_MASK) 66 #define FMC2_PCR_ECCSS_512 0x1U 67 #define FMC2_PCR_ECCSS_2048 0x3U 68 #define FMC2_PCR_BCHECC BIT(24) 69 #define FMC2_PCR_WEN BIT(25) 70 /* FMC2_SR register */ 71 #define FMC2_SR_NWRF BIT(6) 72 /* FMC2_PMEM register*/ 73 #define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0) 74 #define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 75 #define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 76 #define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 77 #define FMC2_PMEM_DEFAULT 0x0A0A0A0AU 78 /* FMC2_PATT register */ 79 #define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0) 80 #define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 81 #define FMC2_PATT_ATTHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 82 #define FMC2_PATT_ATTHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 83 #define FMC2_PATT_DEFAULT 0x0A0A0A0AU 84 /* FMC2_BCHISR register */ 85 #define FMC2_BCHISR_DERF BIT(1) 86 /* FMC2_BCHICR register */ 87 #define FMC2_BCHICR_CLEAR_IRQ GENMASK_32(4, 0) 88 /* FMC2_BCHDSR0 register */ 89 #define FMC2_BCHDSR0_DUE BIT(0) 90 #define FMC2_BCHDSR0_DEF BIT(1) 91 #define FMC2_BCHDSR0_DEN_MASK GENMASK_32(7, 4) 92 #define FMC2_BCHDSR0_DEN_SHIFT 4U 93 /* FMC2_BCHDSR1 register */ 94 #define FMC2_BCHDSR1_EBP1_MASK GENMASK_32(12, 0) 95 #define FMC2_BCHDSR1_EBP2_MASK GENMASK_32(28, 16) 96 #define FMC2_BCHDSR1_EBP2_SHIFT 16U 97 /* FMC2_BCHDSR2 register */ 98 #define FMC2_BCHDSR2_EBP3_MASK GENMASK_32(12, 0) 99 #define FMC2_BCHDSR2_EBP4_MASK GENMASK_32(28, 16) 100 #define FMC2_BCHDSR2_EBP4_SHIFT 16U 101 /* FMC2_BCHDSR3 register */ 102 #define FMC2_BCHDSR3_EBP5_MASK GENMASK_32(12, 0) 103 #define FMC2_BCHDSR3_EBP6_MASK GENMASK_32(28, 16) 104 #define FMC2_BCHDSR3_EBP6_SHIFT 16U 105 /* FMC2_BCHDSR4 register */ 106 #define FMC2_BCHDSR4_EBP7_MASK GENMASK_32(12, 0) 107 #define FMC2_BCHDSR4_EBP8_MASK GENMASK_32(28, 16) 108 #define FMC2_BCHDSR4_EBP8_SHIFT 16U 109 110 /* Timings */ 111 #define FMC2_THIZ 0x01U 112 #define FMC2_TIO 8000U 113 #define FMC2_TSYNC 3000U 114 #define FMC2_PCR_TIMING_MASK GENMASK_32(3, 0) 115 #define FMC2_PMEM_PATT_TIMING_MASK GENMASK_32(7, 0) 116 117 #define FMC2_BBM_LEN 2U 118 #define FMC2_MAX_ECC_BYTES 14U 119 #define TIMEOUT_US_10_MS 10000U 120 #define FMC2_PSEC_PER_MSEC (1000UL * 1000UL * 1000UL) 121 122 enum stm32_fmc2_ecc { 123 FMC2_ECC_HAM = 1U, 124 FMC2_ECC_BCH4 = 4U, 125 FMC2_ECC_BCH8 = 8U 126 }; 127 128 struct stm32_fmc2_cs_reg { 129 uintptr_t data_base; 130 uintptr_t cmd_base; 131 uintptr_t addr_base; 132 }; 133 134 struct stm32_fmc2_nand_timings { 135 uint8_t tclr; 136 uint8_t tar; 137 uint8_t thiz; 138 uint8_t twait; 139 uint8_t thold_mem; 140 uint8_t tset_mem; 141 uint8_t thold_att; 142 uint8_t tset_att; 143 }; 144 145 struct stm32_fmc2_nfc { 146 uintptr_t reg_base; 147 struct stm32_fmc2_cs_reg cs[MAX_CS]; 148 unsigned long clock_id; 149 unsigned int reset_id; 150 uint8_t cs_sel; 151 }; 152 153 static struct stm32_fmc2_nfc stm32_fmc2; 154 155 static uintptr_t fmc2_base(void) 156 { 157 return stm32_fmc2.reg_base; 158 } 159 160 static void stm32_fmc2_nand_setup_timing(void) 161 { 162 struct stm32_fmc2_nand_timings tims; 163 unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id); 164 unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); 165 unsigned long timing, tar, tclr, thiz, twait; 166 unsigned long tset_mem, tset_att, thold_mem, thold_att; 167 uint32_t pcr, pmem, patt; 168 169 tar = MAX(hclkp, NAND_TAR_MIN); 170 timing = div_round_up(tar, hclkp) - 1U; 171 tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 172 173 tclr = MAX(hclkp, NAND_TCLR_MIN); 174 timing = div_round_up(tclr, hclkp) - 1U; 175 tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 176 177 tims.thiz = FMC2_THIZ; 178 thiz = (tims.thiz + 1U) * hclkp; 179 180 /* 181 * tWAIT > tRP 182 * tWAIT > tWP 183 * tWAIT > tREA + tIO 184 */ 185 twait = MAX(hclkp, NAND_TRP_MIN); 186 twait = MAX(twait, NAND_TWP_MIN); 187 twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO); 188 timing = div_round_up(twait, hclkp); 189 tims.twait = CLAMP(timing, 1UL, 190 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 191 192 /* 193 * tSETUP_MEM > tCS - tWAIT 194 * tSETUP_MEM > tALS - tWAIT 195 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 196 */ 197 tset_mem = hclkp; 198 if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) { 199 tset_mem = NAND_TCS_MIN - twait; 200 } 201 if ((twait < NAND_TALS_MIN) && (tset_mem < (NAND_TALS_MIN - twait))) { 202 tset_mem = NAND_TALS_MIN - twait; 203 } 204 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 205 (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) { 206 tset_mem = NAND_TDS_MIN - (twait - thiz); 207 } 208 timing = div_round_up(tset_mem, hclkp); 209 tims.tset_mem = CLAMP(timing, 1UL, 210 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 211 212 /* 213 * tHOLD_MEM > tCH 214 * tHOLD_MEM > tREH - tSETUP_MEM 215 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 216 */ 217 thold_mem = MAX(hclkp, NAND_TCH_MIN); 218 if ((tset_mem < NAND_TREH_MIN) && 219 (thold_mem < (NAND_TREH_MIN - tset_mem))) { 220 thold_mem = NAND_TREH_MIN - tset_mem; 221 } 222 if (((tset_mem + twait) < NAND_TRC_MIN) && 223 (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) { 224 thold_mem = NAND_TRC_MIN - (tset_mem + twait); 225 } 226 if (((tset_mem + twait) < NAND_TWC_MIN) && 227 (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) { 228 thold_mem = NAND_TWC_MIN - (tset_mem + twait); 229 } 230 timing = div_round_up(thold_mem, hclkp); 231 tims.thold_mem = CLAMP(timing, 1UL, 232 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 233 234 /* 235 * tSETUP_ATT > tCS - tWAIT 236 * tSETUP_ATT > tCLS - tWAIT 237 * tSETUP_ATT > tALS - tWAIT 238 * tSETUP_ATT > tRHW - tHOLD_MEM 239 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 240 */ 241 tset_att = hclkp; 242 if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) { 243 tset_att = NAND_TCS_MIN - twait; 244 } 245 if ((twait < NAND_TCLS_MIN) && (tset_att < (NAND_TCLS_MIN - twait))) { 246 tset_att = NAND_TCLS_MIN - twait; 247 } 248 if ((twait < NAND_TALS_MIN) && (tset_att < (NAND_TALS_MIN - twait))) { 249 tset_att = NAND_TALS_MIN - twait; 250 } 251 if ((thold_mem < NAND_TRHW_MIN) && 252 (tset_att < (NAND_TRHW_MIN - thold_mem))) { 253 tset_att = NAND_TRHW_MIN - thold_mem; 254 } 255 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 256 (tset_att < (NAND_TDS_MIN - (twait - thiz)))) { 257 tset_att = NAND_TDS_MIN - (twait - thiz); 258 } 259 timing = div_round_up(tset_att, hclkp); 260 tims.tset_att = CLAMP(timing, 1UL, 261 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 262 263 /* 264 * tHOLD_ATT > tALH 265 * tHOLD_ATT > tCH 266 * tHOLD_ATT > tCLH 267 * tHOLD_ATT > tCOH 268 * tHOLD_ATT > tDH 269 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 270 * tHOLD_ATT > tADL - tSETUP_MEM 271 * tHOLD_ATT > tWH - tSETUP_MEM 272 * tHOLD_ATT > tWHR - tSETUP_MEM 273 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 274 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 275 */ 276 thold_att = MAX(hclkp, NAND_TALH_MIN); 277 thold_att = MAX(thold_att, NAND_TCH_MIN); 278 thold_att = MAX(thold_att, NAND_TCLH_MIN); 279 thold_att = MAX(thold_att, NAND_TCOH_MIN); 280 thold_att = MAX(thold_att, NAND_TDH_MIN); 281 if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) && 282 (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) { 283 thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem; 284 } 285 if ((tset_mem < NAND_TADL_MIN) && 286 (thold_att < (NAND_TADL_MIN - tset_mem))) { 287 thold_att = NAND_TADL_MIN - tset_mem; 288 } 289 if ((tset_mem < NAND_TWH_MIN) && 290 (thold_att < (NAND_TWH_MIN - tset_mem))) { 291 thold_att = NAND_TWH_MIN - tset_mem; 292 } 293 if ((tset_mem < NAND_TWHR_MIN) && 294 (thold_att < (NAND_TWHR_MIN - tset_mem))) { 295 thold_att = NAND_TWHR_MIN - tset_mem; 296 } 297 if (((tset_att + twait) < NAND_TRC_MIN) && 298 (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) { 299 thold_att = NAND_TRC_MIN - (tset_att + twait); 300 } 301 if (((tset_att + twait) < NAND_TWC_MIN) && 302 (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) { 303 thold_att = NAND_TWC_MIN - (tset_att + twait); 304 } 305 timing = div_round_up(thold_att, hclkp); 306 tims.thold_att = CLAMP(timing, 1UL, 307 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 308 309 VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n", 310 tims.tclr, tims.tar, tims.thiz, tims.twait, 311 tims.thold_mem, tims.tset_mem, 312 tims.thold_att, tims.tset_att); 313 314 /* Set tclr/tar timings */ 315 pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 316 pcr &= ~FMC2_PCR_TCLR_MASK; 317 pcr |= FMC2_PCR_TCLR(tims.tclr); 318 pcr &= ~FMC2_PCR_TAR_MASK; 319 pcr |= FMC2_PCR_TAR(tims.tar); 320 321 /* Set tset/twait/thold/thiz timings in common bank */ 322 pmem = FMC2_PMEM_MEMSET(tims.tset_mem); 323 pmem |= FMC2_PMEM_MEMWAIT(tims.twait); 324 pmem |= FMC2_PMEM_MEMHOLD(tims.thold_mem); 325 pmem |= FMC2_PMEM_MEMHIZ(tims.thiz); 326 327 /* Set tset/twait/thold/thiz timings in attribute bank */ 328 patt = FMC2_PATT_ATTSET(tims.tset_att); 329 patt |= FMC2_PATT_ATTWAIT(tims.twait); 330 patt |= FMC2_PATT_ATTHOLD(tims.thold_att); 331 patt |= FMC2_PATT_ATTHIZ(tims.thiz); 332 333 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 334 mmio_write_32(fmc2_base() + FMC2_PMEM, pmem); 335 mmio_write_32(fmc2_base() + FMC2_PATT, patt); 336 } 337 338 static void stm32_fmc2_set_buswidth_16(bool set) 339 { 340 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK, 341 (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U)); 342 } 343 344 static void stm32_fmc2_set_ecc(bool enable) 345 { 346 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN, 347 (enable ? FMC2_PCR_ECCEN : 0U)); 348 } 349 350 static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer, 351 uint8_t *ecc) 352 { 353 uint8_t xor_ecc_ones; 354 uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b; 355 union { 356 uint32_t val; 357 uint8_t bytes[4]; 358 } xor_ecc; 359 360 /* Page size--------ECC_Code Size 361 * 256---------------22 bits LSB (ECC_CODE & 0x003FFFFF) 362 * 512---------------24 bits (ECC_CODE & 0x00FFFFFF) 363 * 1024--------------26 bits (ECC_CODE & 0x03FFFFFF) 364 * 2048--------------28 bits (ECC_CODE & 0x0FFFFFFF) 365 * 4096--------------30 bits (ECC_CODE & 0x3FFFFFFF) 366 * 8192--------------32 bits (ECC_CODE & 0xFFFFFFFF) 367 */ 368 369 /* For Page size 512, ECC_Code size 24 bits */ 370 xor_ecc_1b = ecc[0] ^ eccbuffer[0]; 371 xor_ecc_2b = ecc[1] ^ eccbuffer[1]; 372 xor_ecc_3b = ecc[2] ^ eccbuffer[2]; 373 374 xor_ecc.val = 0U; 375 xor_ecc.bytes[2] = xor_ecc_3b; 376 xor_ecc.bytes[1] = xor_ecc_2b; 377 xor_ecc.bytes[0] = xor_ecc_1b; 378 379 if (xor_ecc.val == 0U) { 380 return 0; /* No Error */ 381 } 382 383 xor_ecc_ones = __builtin_popcount(xor_ecc.val); 384 if (xor_ecc_ones < 23U) { 385 if (xor_ecc_ones == 12U) { 386 uint16_t bit_address, byte_address; 387 388 /* Correctable ERROR */ 389 bit_address = ((xor_ecc_1b >> 1) & BIT(0)) | 390 ((xor_ecc_1b >> 2) & BIT(1)) | 391 ((xor_ecc_1b >> 3) & BIT(2)); 392 393 byte_address = ((xor_ecc_1b >> 7) & BIT(0)) | 394 ((xor_ecc_2b) & BIT(1)) | 395 ((xor_ecc_2b >> 1) & BIT(2)) | 396 ((xor_ecc_2b >> 2) & BIT(3)) | 397 ((xor_ecc_2b >> 3) & BIT(4)) | 398 ((xor_ecc_3b << 4) & BIT(5)) | 399 ((xor_ecc_3b << 3) & BIT(6)) | 400 ((xor_ecc_3b << 2) & BIT(7)) | 401 ((xor_ecc_3b << 1) & BIT(8)); 402 403 /* Correct bit error in the data */ 404 buffer[byte_address] = 405 buffer[byte_address] ^ BIT(bit_address); 406 VERBOSE("Hamming: 1 ECC error corrected\n"); 407 408 return 0; 409 } 410 411 /* Non Correctable ERROR */ 412 ERROR("%s: Uncorrectable ECC Errors\n", __func__); 413 return -1; 414 } 415 416 /* ECC ERROR */ 417 ERROR("%s: Hamming correction error\n", __func__); 418 return -1; 419 } 420 421 422 static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc) 423 { 424 uint32_t heccr; 425 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 426 427 while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) { 428 if (timeout_elapsed(timeout)) { 429 return -ETIMEDOUT; 430 } 431 } 432 433 heccr = mmio_read_32(fmc2_base() + FMC2_HECCR); 434 435 ecc[0] = heccr; 436 ecc[1] = heccr >> 8; 437 ecc[2] = heccr >> 16; 438 439 /* Disable ECC */ 440 stm32_fmc2_set_ecc(false); 441 442 return 0; 443 } 444 445 static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize) 446 { 447 uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4; 448 uint16_t pos[8]; 449 int i, den; 450 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 451 452 while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) & 453 FMC2_BCHISR_DERF) == 0U) { 454 if (timeout_elapsed(timeout)) { 455 return -ETIMEDOUT; 456 } 457 } 458 459 bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0); 460 bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1); 461 bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2); 462 bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3); 463 bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4); 464 465 /* Disable ECC */ 466 stm32_fmc2_set_ecc(false); 467 468 /* No error found */ 469 if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) { 470 return 0; 471 } 472 473 /* Too many errors detected */ 474 if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) { 475 return -EBADMSG; 476 } 477 478 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; 479 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; 480 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; 481 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; 482 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; 483 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; 484 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; 485 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; 486 487 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; 488 for (i = 0; i < den; i++) { 489 if (pos[i] < (eccsize * 8U)) { 490 uint8_t bitmask = BIT(pos[i] % 8U); 491 uint32_t offset = pos[i] / 8U; 492 493 *(buffer + offset) ^= bitmask; 494 } 495 } 496 497 return 0; 498 } 499 500 static void stm32_fmc2_hwctl(struct nand_device *nand) 501 { 502 stm32_fmc2_set_ecc(false); 503 504 if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) { 505 mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN); 506 mmio_write_32(fmc2_base() + FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ); 507 } 508 509 stm32_fmc2_set_ecc(true); 510 } 511 512 static int stm32_fmc2_read_page(struct nand_device *nand, 513 unsigned int page, uintptr_t buffer) 514 { 515 unsigned int eccsize = nand->ecc.size; 516 unsigned int eccbytes = nand->ecc.bytes; 517 unsigned int eccsteps = nand->page_size / eccsize; 518 uint8_t ecc_corr[FMC2_MAX_ECC_BYTES]; 519 uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U}; 520 uint8_t *p; 521 unsigned int i; 522 unsigned int s; 523 int ret; 524 525 VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer); 526 527 ret = nand_read_page_cmd(page, 0U, 0U, 0U); 528 if (ret != 0) { 529 return ret; 530 } 531 532 for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer; 533 s < eccsteps; 534 s++, i += eccbytes, p += eccsize) { 535 stm32_fmc2_hwctl(nand); 536 537 /* Read the NAND page sector (512 bytes) */ 538 ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p, 539 eccsize); 540 if (ret != 0) { 541 return ret; 542 } 543 544 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 545 ret = stm32_fmc2_ham_calculate(p, ecc_cal); 546 if (ret != 0) { 547 return ret; 548 } 549 } 550 551 /* Read the corresponding ECC bytes */ 552 ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr, 553 eccbytes); 554 if (ret != 0) { 555 return ret; 556 } 557 558 /* Correct the data */ 559 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 560 ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal); 561 } else { 562 ret = stm32_fmc2_bch_correct(p, eccsize); 563 } 564 565 if (ret != 0) { 566 return ret; 567 } 568 } 569 570 return 0; 571 } 572 573 static void stm32_fmc2_read_data(struct nand_device *nand, 574 uint8_t *buff, unsigned int length, 575 bool use_bus8) 576 { 577 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 578 579 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 580 stm32_fmc2_set_buswidth_16(false); 581 } 582 583 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 584 *buff = mmio_read_8(data_base); 585 buff += sizeof(uint8_t); 586 length -= sizeof(uint8_t); 587 } 588 589 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 590 (length >= sizeof(uint16_t))) { 591 *(uint16_t *)buff = mmio_read_16(data_base); 592 buff += sizeof(uint16_t); 593 length -= sizeof(uint16_t); 594 } 595 596 /* 32bit aligned */ 597 while (length >= sizeof(uint32_t)) { 598 *(uint32_t *)buff = mmio_read_32(data_base); 599 buff += sizeof(uint32_t); 600 length -= sizeof(uint32_t); 601 } 602 603 /* Read remaining bytes */ 604 if (length >= sizeof(uint16_t)) { 605 *(uint16_t *)buff = mmio_read_16(data_base); 606 buff += sizeof(uint16_t); 607 length -= sizeof(uint16_t); 608 } 609 610 if (length != 0U) { 611 *buff = mmio_read_8(data_base); 612 } 613 614 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 615 /* Reconfigure bus width to 16-bit */ 616 stm32_fmc2_set_buswidth_16(true); 617 } 618 } 619 620 static void stm32_fmc2_write_data(struct nand_device *nand, 621 uint8_t *buff, unsigned int length, 622 bool use_bus8) 623 { 624 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 625 626 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 627 /* Reconfigure bus width to 8-bit */ 628 stm32_fmc2_set_buswidth_16(false); 629 } 630 631 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 632 mmio_write_8(data_base, *buff); 633 buff += sizeof(uint8_t); 634 length -= sizeof(uint8_t); 635 } 636 637 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 638 (length >= sizeof(uint16_t))) { 639 mmio_write_16(data_base, *(uint16_t *)buff); 640 buff += sizeof(uint16_t); 641 length -= sizeof(uint16_t); 642 } 643 644 /* 32bits aligned */ 645 while (length >= sizeof(uint32_t)) { 646 mmio_write_32(data_base, *(uint32_t *)buff); 647 buff += sizeof(uint32_t); 648 length -= sizeof(uint32_t); 649 } 650 651 /* Read remaining bytes */ 652 if (length >= sizeof(uint16_t)) { 653 mmio_write_16(data_base, *(uint16_t *)buff); 654 buff += sizeof(uint16_t); 655 length -= sizeof(uint16_t); 656 } 657 658 if (length != 0U) { 659 mmio_write_8(data_base, *buff); 660 } 661 662 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 663 /* Reconfigure bus width to 16-bit */ 664 stm32_fmc2_set_buswidth_16(true); 665 } 666 } 667 668 static void stm32_fmc2_ctrl_init(void) 669 { 670 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 671 uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1); 672 673 /* Enable wait feature and NAND flash memory bank */ 674 pcr |= FMC2_PCR_PWAITEN; 675 pcr |= FMC2_PCR_PBKEN; 676 677 /* Set buswidth to 8 bits mode for identification */ 678 pcr &= ~FMC2_PCR_PWID_MASK; 679 680 /* ECC logic is disabled */ 681 pcr &= ~FMC2_PCR_ECCEN; 682 683 /* Default mode */ 684 pcr &= ~FMC2_PCR_ECCALG; 685 pcr &= ~FMC2_PCR_BCHECC; 686 pcr &= ~FMC2_PCR_WEN; 687 688 /* Set default ECC sector size */ 689 pcr &= ~FMC2_PCR_ECCSS_MASK; 690 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); 691 692 /* Set default TCLR/TAR timings */ 693 pcr &= ~FMC2_PCR_TCLR_MASK; 694 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); 695 pcr &= ~FMC2_PCR_TAR_MASK; 696 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); 697 698 /* Enable FMC2 controller */ 699 bcr1 |= FMC2_BCR1_FMC2EN; 700 701 mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1); 702 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 703 mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT); 704 mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT); 705 } 706 707 static int stm32_fmc2_exec(struct nand_req *req) 708 { 709 int ret = 0; 710 711 switch (req->type & NAND_REQ_MASK) { 712 case NAND_REQ_CMD: 713 VERBOSE("Write CMD %x\n", (uint8_t)req->type); 714 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, 715 (uint8_t)req->type); 716 break; 717 case NAND_REQ_ADDR: 718 VERBOSE("Write ADDR %x\n", *(req->addr)); 719 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, 720 *(req->addr)); 721 break; 722 case NAND_REQ_DATAIN: 723 VERBOSE("Read data\n"); 724 stm32_fmc2_read_data(req->nand, req->addr, req->length, 725 ((req->type & NAND_REQ_BUS_WIDTH_8) != 726 0U)); 727 break; 728 case NAND_REQ_DATAOUT: 729 VERBOSE("Write data\n"); 730 stm32_fmc2_write_data(req->nand, req->addr, req->length, 731 ((req->type & NAND_REQ_BUS_WIDTH_8) != 732 0U)); 733 break; 734 case NAND_REQ_WAIT: 735 VERBOSE("WAIT Ready\n"); 736 ret = nand_wait_ready(req->delay_ms); 737 break; 738 default: 739 ret = -EINVAL; 740 break; 741 }; 742 743 return ret; 744 } 745 746 static void stm32_fmc2_setup(struct nand_device *nand) 747 { 748 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 749 750 /* Set buswidth */ 751 pcr &= ~FMC2_PCR_PWID_MASK; 752 if (nand->buswidth == NAND_BUS_WIDTH_16) { 753 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16); 754 } 755 756 if (nand->ecc.mode == NAND_ECC_HW) { 757 nand->mtd_read_page = stm32_fmc2_read_page; 758 759 pcr &= ~FMC2_PCR_ECCALG; 760 pcr &= ~FMC2_PCR_BCHECC; 761 762 pcr &= ~FMC2_PCR_ECCSS_MASK; 763 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); 764 765 switch (nand->ecc.max_bit_corr) { 766 case FMC2_ECC_HAM: 767 nand->ecc.bytes = 3; 768 break; 769 case FMC2_ECC_BCH8: 770 pcr |= FMC2_PCR_ECCALG; 771 pcr |= FMC2_PCR_BCHECC; 772 nand->ecc.bytes = 13; 773 break; 774 default: 775 /* Use FMC2 ECC BCH4 */ 776 pcr |= FMC2_PCR_ECCALG; 777 nand->ecc.bytes = 7; 778 break; 779 } 780 781 if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) { 782 nand->ecc.bytes++; 783 } 784 } 785 786 mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr); 787 } 788 789 static const struct nand_ctrl_ops ctrl_ops = { 790 .setup = stm32_fmc2_setup, 791 .exec = stm32_fmc2_exec 792 }; 793 794 int stm32_fmc2_init(void) 795 { 796 int fmc_node; 797 int fmc_subnode = 0; 798 int nchips = 0; 799 unsigned int i; 800 void *fdt = NULL; 801 const fdt32_t *cuint; 802 struct dt_node_info info; 803 int ret; 804 805 if (fdt_get_address(&fdt) == 0) { 806 return -FDT_ERR_NOTFOUND; 807 } 808 809 fmc_node = dt_get_node(&info, -1, DT_FMC2_COMPAT); 810 if (fmc_node == -FDT_ERR_NOTFOUND) { 811 WARN("No FMC2 node found\n"); 812 return fmc_node; 813 } 814 815 if (info.status == DT_DISABLED) { 816 return -FDT_ERR_NOTFOUND; 817 } 818 819 stm32_fmc2.reg_base = info.base; 820 821 if ((info.clock < 0) || (info.reset < 0)) { 822 return -FDT_ERR_BADVALUE; 823 } 824 825 stm32_fmc2.clock_id = (unsigned long)info.clock; 826 stm32_fmc2.reset_id = (unsigned int)info.reset; 827 828 cuint = fdt_getprop(fdt, fmc_node, "reg", NULL); 829 if (cuint == NULL) { 830 return -FDT_ERR_BADVALUE; 831 } 832 833 cuint += 2; 834 835 for (i = 0U; i < MAX_CS; i++) { 836 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*cuint); 837 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 2)); 838 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 4)); 839 cuint += 6; 840 } 841 842 /* Pinctrl initialization */ 843 if (dt_set_pinctrl_config(fmc_node) != 0) { 844 return -FDT_ERR_BADVALUE; 845 } 846 847 /* Parse flash nodes */ 848 fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { 849 nchips++; 850 } 851 852 if (nchips != 1) { 853 WARN("Only one SLC NAND device supported\n"); 854 return -FDT_ERR_BADVALUE; 855 } 856 857 fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { 858 /* Get chip select */ 859 cuint = fdt_getprop(fdt, fmc_subnode, "reg", NULL); 860 if (cuint == NULL) { 861 WARN("Chip select not well defined\n"); 862 return -FDT_ERR_BADVALUE; 863 } 864 stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint); 865 VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel); 866 } 867 868 /* Enable Clock */ 869 stm32mp_clk_enable(stm32_fmc2.clock_id); 870 871 /* Reset IP */ 872 ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); 873 if (ret != 0) { 874 panic(); 875 } 876 ret = stm32mp_reset_deassert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); 877 if (ret != 0) { 878 panic(); 879 } 880 881 /* Setup default IP registers */ 882 stm32_fmc2_ctrl_init(); 883 884 /* Setup default timings */ 885 stm32_fmc2_nand_setup_timing(); 886 887 /* Init NAND RAW framework */ 888 nand_raw_ctrl_init(&ctrl_ops); 889 890 return 0; 891 } 892