1 /* 2 * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/raw_nand.h> 19 #include <drivers/st/stm32_fmc2_nand.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32mp_reset.h> 22 #include <lib/mmio.h> 23 #include <lib/utils_def.h> 24 25 /* FMC2 Compatibility */ 26 #define DT_FMC2_COMPAT "st,stm32mp15-fmc2" 27 #define MAX_CS 2U 28 29 /* FMC2 Controller Registers */ 30 #define FMC2_BCR1 0x00U 31 #define FMC2_PCR 0x80U 32 #define FMC2_SR 0x84U 33 #define FMC2_PMEM 0x88U 34 #define FMC2_PATT 0x8CU 35 #define FMC2_HECCR 0x94U 36 #define FMC2_BCHISR 0x254U 37 #define FMC2_BCHDSR0 0x27CU 38 #define FMC2_BCHDSR1 0x280U 39 #define FMC2_BCHDSR2 0x284U 40 #define FMC2_BCHDSR3 0x288U 41 #define FMC2_BCHDSR4 0x28CU 42 43 /* FMC2_BCR1 register */ 44 #define FMC2_BCR1_FMC2EN BIT(31) 45 /* FMC2_PCR register */ 46 #define FMC2_PCR_PWAITEN BIT(1) 47 #define FMC2_PCR_PBKEN BIT(2) 48 #define FMC2_PCR_PWID_MASK GENMASK_32(5, 4) 49 #define FMC2_PCR_PWID(x) (((x) << 4) & FMC2_PCR_PWID_MASK) 50 #define FMC2_PCR_PWID_8 0x0U 51 #define FMC2_PCR_PWID_16 0x1U 52 #define FMC2_PCR_ECCEN BIT(6) 53 #define FMC2_PCR_ECCALG BIT(8) 54 #define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9) 55 #define FMC2_PCR_TCLR(x) (((x) << 9) & FMC2_PCR_TCLR_MASK) 56 #define FMC2_PCR_TCLR_DEFAULT 0xFU 57 #define FMC2_PCR_TAR_MASK GENMASK_32(16, 13) 58 #define FMC2_PCR_TAR(x) (((x) << 13) & FMC2_PCR_TAR_MASK) 59 #define FMC2_PCR_TAR_DEFAULT 0xFU 60 #define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17) 61 #define FMC2_PCR_ECCSS(x) (((x) << 17) & FMC2_PCR_ECCSS_MASK) 62 #define FMC2_PCR_ECCSS_512 0x1U 63 #define FMC2_PCR_ECCSS_2048 0x3U 64 #define FMC2_PCR_BCHECC BIT(24) 65 #define FMC2_PCR_WEN BIT(25) 66 /* FMC2_SR register */ 67 #define FMC2_SR_NWRF BIT(6) 68 /* FMC2_PMEM register*/ 69 #define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0) 70 #define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 71 #define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 72 #define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 73 #define FMC2_PMEM_DEFAULT 0x0A0A0A0AU 74 /* FMC2_PATT register */ 75 #define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0) 76 #define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 77 #define FMC2_PATT_ATTHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 78 #define FMC2_PATT_ATTHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 79 #define FMC2_PATT_DEFAULT 0x0A0A0A0AU 80 /* FMC2_BCHISR register */ 81 #define FMC2_BCHISR_DERF BIT(1) 82 /* FMC2_BCHDSR0 register */ 83 #define FMC2_BCHDSR0_DUE BIT(0) 84 #define FMC2_BCHDSR0_DEF BIT(1) 85 #define FMC2_BCHDSR0_DEN_MASK GENMASK_32(7, 4) 86 #define FMC2_BCHDSR0_DEN_SHIFT 4U 87 /* FMC2_BCHDSR1 register */ 88 #define FMC2_BCHDSR1_EBP1_MASK GENMASK_32(12, 0) 89 #define FMC2_BCHDSR1_EBP2_MASK GENMASK_32(28, 16) 90 #define FMC2_BCHDSR1_EBP2_SHIFT 16U 91 /* FMC2_BCHDSR2 register */ 92 #define FMC2_BCHDSR2_EBP3_MASK GENMASK_32(12, 0) 93 #define FMC2_BCHDSR2_EBP4_MASK GENMASK_32(28, 16) 94 #define FMC2_BCHDSR2_EBP4_SHIFT 16U 95 /* FMC2_BCHDSR3 register */ 96 #define FMC2_BCHDSR3_EBP5_MASK GENMASK_32(12, 0) 97 #define FMC2_BCHDSR3_EBP6_MASK GENMASK_32(28, 16) 98 #define FMC2_BCHDSR3_EBP6_SHIFT 16U 99 /* FMC2_BCHDSR4 register */ 100 #define FMC2_BCHDSR4_EBP7_MASK GENMASK_32(12, 0) 101 #define FMC2_BCHDSR4_EBP8_MASK GENMASK_32(28, 16) 102 #define FMC2_BCHDSR4_EBP8_SHIFT 16U 103 104 /* Timings */ 105 #define FMC2_THIZ 0x01U 106 #define FMC2_TIO 8000U 107 #define FMC2_TSYNC 3000U 108 #define FMC2_PCR_TIMING_MASK GENMASK_32(3, 0) 109 #define FMC2_PMEM_PATT_TIMING_MASK GENMASK_32(7, 0) 110 111 #define FMC2_BBM_LEN 2U 112 #define FMC2_MAX_ECC_BYTES 14U 113 #define TIMEOUT_US_10_MS 10000U 114 #define FMC2_PSEC_PER_MSEC (1000UL * 1000UL * 1000UL) 115 116 enum stm32_fmc2_ecc { 117 FMC2_ECC_HAM = 1U, 118 FMC2_ECC_BCH4 = 4U, 119 FMC2_ECC_BCH8 = 8U 120 }; 121 122 struct stm32_fmc2_cs_reg { 123 uintptr_t data_base; 124 uintptr_t cmd_base; 125 uintptr_t addr_base; 126 }; 127 128 struct stm32_fmc2_nand_timings { 129 uint8_t tclr; 130 uint8_t tar; 131 uint8_t thiz; 132 uint8_t twait; 133 uint8_t thold_mem; 134 uint8_t tset_mem; 135 uint8_t thold_att; 136 uint8_t tset_att; 137 }; 138 139 struct stm32_fmc2_nfc { 140 uintptr_t reg_base; 141 struct stm32_fmc2_cs_reg cs[MAX_CS]; 142 unsigned long clock_id; 143 unsigned int reset_id; 144 uint8_t cs_sel; 145 }; 146 147 static struct stm32_fmc2_nfc stm32_fmc2; 148 149 static uintptr_t fmc2_base(void) 150 { 151 return stm32_fmc2.reg_base; 152 } 153 154 static void stm32_fmc2_nand_setup_timing(void) 155 { 156 struct stm32_fmc2_nand_timings tims; 157 unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id); 158 unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); 159 unsigned long timing, tar, tclr, thiz, twait; 160 unsigned long tset_mem, tset_att, thold_mem, thold_att; 161 uint32_t pcr, pmem, patt; 162 163 tar = MAX(hclkp, NAND_TAR_MIN); 164 timing = div_round_up(tar, hclkp) - 1U; 165 tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 166 167 tclr = MAX(hclkp, NAND_TCLR_MIN); 168 timing = div_round_up(tclr, hclkp) - 1U; 169 tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 170 171 tims.thiz = FMC2_THIZ; 172 thiz = (tims.thiz + 1U) * hclkp; 173 174 /* 175 * tWAIT > tRP 176 * tWAIT > tWP 177 * tWAIT > tREA + tIO 178 */ 179 twait = MAX(hclkp, NAND_TRP_MIN); 180 twait = MAX(twait, NAND_TWP_MIN); 181 twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO); 182 timing = div_round_up(twait, hclkp); 183 tims.twait = CLAMP(timing, 1UL, 184 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 185 186 /* 187 * tSETUP_MEM > tCS - tWAIT 188 * tSETUP_MEM > tALS - tWAIT 189 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 190 */ 191 tset_mem = hclkp; 192 if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) { 193 tset_mem = NAND_TCS_MIN - twait; 194 } 195 if ((twait < NAND_TALS_MIN) && (tset_mem < (NAND_TALS_MIN - twait))) { 196 tset_mem = NAND_TALS_MIN - twait; 197 } 198 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 199 (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) { 200 tset_mem = NAND_TDS_MIN - (twait - thiz); 201 } 202 timing = div_round_up(tset_mem, hclkp); 203 tims.tset_mem = CLAMP(timing, 1UL, 204 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 205 206 /* 207 * tHOLD_MEM > tCH 208 * tHOLD_MEM > tREH - tSETUP_MEM 209 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 210 */ 211 thold_mem = MAX(hclkp, NAND_TCH_MIN); 212 if ((tset_mem < NAND_TREH_MIN) && 213 (thold_mem < (NAND_TREH_MIN - tset_mem))) { 214 thold_mem = NAND_TREH_MIN - tset_mem; 215 } 216 if (((tset_mem + twait) < NAND_TRC_MIN) && 217 (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) { 218 thold_mem = NAND_TRC_MIN - (tset_mem + twait); 219 } 220 if (((tset_mem + twait) < NAND_TWC_MIN) && 221 (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) { 222 thold_mem = NAND_TWC_MIN - (tset_mem + twait); 223 } 224 timing = div_round_up(thold_mem, hclkp); 225 tims.thold_mem = CLAMP(timing, 1UL, 226 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 227 228 /* 229 * tSETUP_ATT > tCS - tWAIT 230 * tSETUP_ATT > tCLS - tWAIT 231 * tSETUP_ATT > tALS - tWAIT 232 * tSETUP_ATT > tRHW - tHOLD_MEM 233 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 234 */ 235 tset_att = hclkp; 236 if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) { 237 tset_att = NAND_TCS_MIN - twait; 238 } 239 if ((twait < NAND_TCLS_MIN) && (tset_att < (NAND_TCLS_MIN - twait))) { 240 tset_att = NAND_TCLS_MIN - twait; 241 } 242 if ((twait < NAND_TALS_MIN) && (tset_att < (NAND_TALS_MIN - twait))) { 243 tset_att = NAND_TALS_MIN - twait; 244 } 245 if ((thold_mem < NAND_TRHW_MIN) && 246 (tset_att < (NAND_TRHW_MIN - thold_mem))) { 247 tset_att = NAND_TRHW_MIN - thold_mem; 248 } 249 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 250 (tset_att < (NAND_TDS_MIN - (twait - thiz)))) { 251 tset_att = NAND_TDS_MIN - (twait - thiz); 252 } 253 timing = div_round_up(tset_att, hclkp); 254 tims.tset_att = CLAMP(timing, 1UL, 255 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 256 257 /* 258 * tHOLD_ATT > tALH 259 * tHOLD_ATT > tCH 260 * tHOLD_ATT > tCLH 261 * tHOLD_ATT > tCOH 262 * tHOLD_ATT > tDH 263 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 264 * tHOLD_ATT > tADL - tSETUP_MEM 265 * tHOLD_ATT > tWH - tSETUP_MEM 266 * tHOLD_ATT > tWHR - tSETUP_MEM 267 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 268 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 269 */ 270 thold_att = MAX(hclkp, NAND_TALH_MIN); 271 thold_att = MAX(thold_att, NAND_TCH_MIN); 272 thold_att = MAX(thold_att, NAND_TCLH_MIN); 273 thold_att = MAX(thold_att, NAND_TCOH_MIN); 274 thold_att = MAX(thold_att, NAND_TDH_MIN); 275 if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) && 276 (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) { 277 thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem; 278 } 279 if ((tset_mem < NAND_TADL_MIN) && 280 (thold_att < (NAND_TADL_MIN - tset_mem))) { 281 thold_att = NAND_TADL_MIN - tset_mem; 282 } 283 if ((tset_mem < NAND_TWH_MIN) && 284 (thold_att < (NAND_TWH_MIN - tset_mem))) { 285 thold_att = NAND_TWH_MIN - tset_mem; 286 } 287 if ((tset_mem < NAND_TWHR_MIN) && 288 (thold_att < (NAND_TWHR_MIN - tset_mem))) { 289 thold_att = NAND_TWHR_MIN - tset_mem; 290 } 291 if (((tset_att + twait) < NAND_TRC_MIN) && 292 (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) { 293 thold_att = NAND_TRC_MIN - (tset_att + twait); 294 } 295 if (((tset_att + twait) < NAND_TWC_MIN) && 296 (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) { 297 thold_att = NAND_TWC_MIN - (tset_att + twait); 298 } 299 timing = div_round_up(thold_att, hclkp); 300 tims.thold_att = CLAMP(timing, 1UL, 301 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 302 303 VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n", 304 tims.tclr, tims.tar, tims.thiz, tims.twait, 305 tims.thold_mem, tims.tset_mem, 306 tims.thold_att, tims.tset_att); 307 308 /* Set tclr/tar timings */ 309 pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 310 pcr &= ~FMC2_PCR_TCLR_MASK; 311 pcr |= FMC2_PCR_TCLR(tims.tclr); 312 pcr &= ~FMC2_PCR_TAR_MASK; 313 pcr |= FMC2_PCR_TAR(tims.tar); 314 315 /* Set tset/twait/thold/thiz timings in common bank */ 316 pmem = FMC2_PMEM_MEMSET(tims.tset_mem); 317 pmem |= FMC2_PMEM_MEMWAIT(tims.twait); 318 pmem |= FMC2_PMEM_MEMHOLD(tims.thold_mem); 319 pmem |= FMC2_PMEM_MEMHIZ(tims.thiz); 320 321 /* Set tset/twait/thold/thiz timings in attribute bank */ 322 patt = FMC2_PATT_ATTSET(tims.tset_att); 323 patt |= FMC2_PATT_ATTWAIT(tims.twait); 324 patt |= FMC2_PATT_ATTHOLD(tims.thold_att); 325 patt |= FMC2_PATT_ATTHIZ(tims.thiz); 326 327 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 328 mmio_write_32(fmc2_base() + FMC2_PMEM, pmem); 329 mmio_write_32(fmc2_base() + FMC2_PATT, patt); 330 } 331 332 static void stm32_fmc2_set_buswidth_16(bool set) 333 { 334 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK, 335 (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U)); 336 } 337 338 static void stm32_fmc2_set_ecc(bool enable) 339 { 340 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN, 341 (enable ? FMC2_PCR_ECCEN : 0U)); 342 } 343 344 static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer, 345 uint8_t *ecc) 346 { 347 uint8_t xor_ecc_ones; 348 uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b; 349 union { 350 uint32_t val; 351 uint8_t bytes[4]; 352 } xor_ecc; 353 354 /* Page size--------ECC_Code Size 355 * 256---------------22 bits LSB (ECC_CODE & 0x003FFFFF) 356 * 512---------------24 bits (ECC_CODE & 0x00FFFFFF) 357 * 1024--------------26 bits (ECC_CODE & 0x03FFFFFF) 358 * 2048--------------28 bits (ECC_CODE & 0x0FFFFFFF) 359 * 4096--------------30 bits (ECC_CODE & 0x3FFFFFFF) 360 * 8192--------------32 bits (ECC_CODE & 0xFFFFFFFF) 361 */ 362 363 /* For Page size 512, ECC_Code size 24 bits */ 364 xor_ecc_1b = ecc[0] ^ eccbuffer[0]; 365 xor_ecc_2b = ecc[1] ^ eccbuffer[1]; 366 xor_ecc_3b = ecc[2] ^ eccbuffer[2]; 367 368 xor_ecc.val = 0U; 369 xor_ecc.bytes[2] = xor_ecc_3b; 370 xor_ecc.bytes[1] = xor_ecc_2b; 371 xor_ecc.bytes[0] = xor_ecc_1b; 372 373 if (xor_ecc.val == 0U) { 374 return 0; /* No Error */ 375 } 376 377 xor_ecc_ones = __builtin_popcount(xor_ecc.val); 378 if (xor_ecc_ones < 23U) { 379 if (xor_ecc_ones == 12U) { 380 uint16_t bit_address, byte_address; 381 382 /* Correctable ERROR */ 383 bit_address = ((xor_ecc_1b >> 1) & BIT(0)) | 384 ((xor_ecc_1b >> 2) & BIT(1)) | 385 ((xor_ecc_1b >> 3) & BIT(2)); 386 387 byte_address = ((xor_ecc_1b >> 7) & BIT(0)) | 388 ((xor_ecc_2b) & BIT(1)) | 389 ((xor_ecc_2b >> 1) & BIT(2)) | 390 ((xor_ecc_2b >> 2) & BIT(3)) | 391 ((xor_ecc_2b >> 3) & BIT(4)) | 392 ((xor_ecc_3b << 4) & BIT(5)) | 393 ((xor_ecc_3b << 3) & BIT(6)) | 394 ((xor_ecc_3b << 2) & BIT(7)) | 395 ((xor_ecc_3b << 1) & BIT(8)); 396 397 /* Correct bit error in the data */ 398 buffer[byte_address] = 399 buffer[byte_address] ^ BIT(bit_address); 400 VERBOSE("Hamming: 1 ECC error corrected\n"); 401 402 return 0; 403 } 404 405 /* Non Correctable ERROR */ 406 ERROR("%s: Uncorrectable ECC Errors\n", __func__); 407 return -1; 408 } 409 410 /* ECC ERROR */ 411 ERROR("%s: Hamming correction error\n", __func__); 412 return -1; 413 } 414 415 416 static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc) 417 { 418 uint32_t heccr; 419 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 420 421 while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) { 422 if (timeout_elapsed(timeout)) { 423 return -ETIMEDOUT; 424 } 425 } 426 427 heccr = mmio_read_32(fmc2_base() + FMC2_HECCR); 428 429 ecc[0] = heccr; 430 ecc[1] = heccr >> 8; 431 ecc[2] = heccr >> 16; 432 433 /* Disable ECC */ 434 stm32_fmc2_set_ecc(false); 435 436 return 0; 437 } 438 439 static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize) 440 { 441 uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4; 442 uint16_t pos[8]; 443 int i, den; 444 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 445 446 while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) & 447 FMC2_BCHISR_DERF) == 0U) { 448 if (timeout_elapsed(timeout)) { 449 return -ETIMEDOUT; 450 } 451 } 452 453 bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0); 454 bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1); 455 bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2); 456 bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3); 457 bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4); 458 459 /* Disable ECC */ 460 stm32_fmc2_set_ecc(false); 461 462 /* No error found */ 463 if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) { 464 return 0; 465 } 466 467 /* Too many errors detected */ 468 if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) { 469 return -EBADMSG; 470 } 471 472 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; 473 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; 474 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; 475 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; 476 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; 477 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; 478 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; 479 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; 480 481 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; 482 for (i = 0; i < den; i++) { 483 if (pos[i] < (eccsize * 8U)) { 484 uint8_t bitmask = BIT(pos[i] % 8U); 485 uint32_t offset = pos[i] / 8U; 486 487 *(buffer + offset) ^= bitmask; 488 } 489 } 490 491 return 0; 492 } 493 494 static void stm32_fmc2_hwctl(struct nand_device *nand) 495 { 496 stm32_fmc2_set_ecc(false); 497 498 if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) { 499 mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN); 500 } 501 502 stm32_fmc2_set_ecc(true); 503 } 504 505 static int stm32_fmc2_read_page(struct nand_device *nand, 506 unsigned int page, uintptr_t buffer) 507 { 508 unsigned int eccsize = nand->ecc.size; 509 unsigned int eccbytes = nand->ecc.bytes; 510 unsigned int eccsteps = nand->page_size / eccsize; 511 uint8_t ecc_corr[FMC2_MAX_ECC_BYTES]; 512 uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U}; 513 uint8_t *p; 514 unsigned int i; 515 unsigned int s; 516 int ret; 517 518 VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer); 519 520 ret = nand_read_page_cmd(page, 0U, 0U, 0U); 521 if (ret != 0) { 522 return ret; 523 } 524 525 for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer; 526 s < eccsteps; 527 s++, i += eccbytes, p += eccsize) { 528 stm32_fmc2_hwctl(nand); 529 530 /* Read the NAND page sector (512 bytes) */ 531 ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p, 532 eccsize); 533 if (ret != 0) { 534 return ret; 535 } 536 537 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 538 ret = stm32_fmc2_ham_calculate(p, ecc_cal); 539 if (ret != 0) { 540 return ret; 541 } 542 } 543 544 /* Read the corresponding ECC bytes */ 545 ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr, 546 eccbytes); 547 if (ret != 0) { 548 return ret; 549 } 550 551 /* Correct the data */ 552 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 553 ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal); 554 } else { 555 ret = stm32_fmc2_bch_correct(p, eccsize); 556 } 557 558 if (ret != 0) { 559 return ret; 560 } 561 } 562 563 return 0; 564 } 565 566 static void stm32_fmc2_read_data(struct nand_device *nand, 567 uint8_t *buff, unsigned int length, 568 bool use_bus8) 569 { 570 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 571 572 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 573 stm32_fmc2_set_buswidth_16(false); 574 } 575 576 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 577 *buff = mmio_read_8(data_base); 578 buff += sizeof(uint8_t); 579 length -= sizeof(uint8_t); 580 } 581 582 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 583 (length >= sizeof(uint16_t))) { 584 *(uint16_t *)buff = mmio_read_16(data_base); 585 buff += sizeof(uint16_t); 586 length -= sizeof(uint16_t); 587 } 588 589 /* 32bit aligned */ 590 while (length >= sizeof(uint32_t)) { 591 *(uint32_t *)buff = mmio_read_32(data_base); 592 buff += sizeof(uint32_t); 593 length -= sizeof(uint32_t); 594 } 595 596 /* Read remaining bytes */ 597 if (length >= sizeof(uint16_t)) { 598 *(uint16_t *)buff = mmio_read_16(data_base); 599 buff += sizeof(uint16_t); 600 length -= sizeof(uint16_t); 601 } 602 603 if (length != 0U) { 604 *buff = mmio_read_8(data_base); 605 } 606 607 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 608 /* Reconfigure bus width to 16-bit */ 609 stm32_fmc2_set_buswidth_16(true); 610 } 611 } 612 613 static void stm32_fmc2_write_data(struct nand_device *nand, 614 uint8_t *buff, unsigned int length, 615 bool use_bus8) 616 { 617 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 618 619 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 620 /* Reconfigure bus width to 8-bit */ 621 stm32_fmc2_set_buswidth_16(false); 622 } 623 624 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 625 mmio_write_8(data_base, *buff); 626 buff += sizeof(uint8_t); 627 length -= sizeof(uint8_t); 628 } 629 630 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 631 (length >= sizeof(uint16_t))) { 632 mmio_write_16(data_base, *(uint16_t *)buff); 633 buff += sizeof(uint16_t); 634 length -= sizeof(uint16_t); 635 } 636 637 /* 32bits aligned */ 638 while (length >= sizeof(uint32_t)) { 639 mmio_write_32(data_base, *(uint32_t *)buff); 640 buff += sizeof(uint32_t); 641 length -= sizeof(uint32_t); 642 } 643 644 /* Read remaining bytes */ 645 if (length >= sizeof(uint16_t)) { 646 mmio_write_16(data_base, *(uint16_t *)buff); 647 buff += sizeof(uint16_t); 648 length -= sizeof(uint16_t); 649 } 650 651 if (length != 0U) { 652 mmio_write_8(data_base, *buff); 653 } 654 655 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 656 /* Reconfigure bus width to 16-bit */ 657 stm32_fmc2_set_buswidth_16(true); 658 } 659 } 660 661 static void stm32_fmc2_ctrl_init(void) 662 { 663 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 664 uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1); 665 666 /* Enable wait feature and NAND flash memory bank */ 667 pcr |= FMC2_PCR_PWAITEN; 668 pcr |= FMC2_PCR_PBKEN; 669 670 /* Set buswidth to 8 bits mode for identification */ 671 pcr &= ~FMC2_PCR_PWID_MASK; 672 673 /* ECC logic is disabled */ 674 pcr &= ~FMC2_PCR_ECCEN; 675 676 /* Default mode */ 677 pcr &= ~FMC2_PCR_ECCALG; 678 pcr &= ~FMC2_PCR_BCHECC; 679 pcr &= ~FMC2_PCR_WEN; 680 681 /* Set default ECC sector size */ 682 pcr &= ~FMC2_PCR_ECCSS_MASK; 683 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); 684 685 /* Set default TCLR/TAR timings */ 686 pcr &= ~FMC2_PCR_TCLR_MASK; 687 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); 688 pcr &= ~FMC2_PCR_TAR_MASK; 689 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); 690 691 /* Enable FMC2 controller */ 692 bcr1 |= FMC2_BCR1_FMC2EN; 693 694 mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1); 695 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 696 mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT); 697 mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT); 698 } 699 700 static int stm32_fmc2_exec(struct nand_req *req) 701 { 702 int ret = 0; 703 704 switch (req->type & NAND_REQ_MASK) { 705 case NAND_REQ_CMD: 706 VERBOSE("Write CMD %x\n", (uint8_t)req->type); 707 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, 708 (uint8_t)req->type); 709 break; 710 case NAND_REQ_ADDR: 711 VERBOSE("Write ADDR %x\n", *(req->addr)); 712 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, 713 *(req->addr)); 714 break; 715 case NAND_REQ_DATAIN: 716 VERBOSE("Read data\n"); 717 stm32_fmc2_read_data(req->nand, req->addr, req->length, 718 ((req->type & NAND_REQ_BUS_WIDTH_8) != 719 0U)); 720 break; 721 case NAND_REQ_DATAOUT: 722 VERBOSE("Write data\n"); 723 stm32_fmc2_write_data(req->nand, req->addr, req->length, 724 ((req->type & NAND_REQ_BUS_WIDTH_8) != 725 0U)); 726 break; 727 case NAND_REQ_WAIT: 728 VERBOSE("WAIT Ready\n"); 729 ret = nand_wait_ready(req->delay_ms); 730 break; 731 default: 732 ret = -EINVAL; 733 break; 734 }; 735 736 return ret; 737 } 738 739 static void stm32_fmc2_setup(struct nand_device *nand) 740 { 741 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 742 743 /* Set buswidth */ 744 pcr &= ~FMC2_PCR_PWID_MASK; 745 if (nand->buswidth == NAND_BUS_WIDTH_16) { 746 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16); 747 } 748 749 if (nand->ecc.mode == NAND_ECC_HW) { 750 nand->mtd_read_page = stm32_fmc2_read_page; 751 752 pcr &= ~FMC2_PCR_ECCALG; 753 pcr &= ~FMC2_PCR_BCHECC; 754 755 pcr &= ~FMC2_PCR_ECCSS_MASK; 756 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); 757 758 switch (nand->ecc.max_bit_corr) { 759 case FMC2_ECC_HAM: 760 nand->ecc.bytes = 3; 761 break; 762 case FMC2_ECC_BCH8: 763 pcr |= FMC2_PCR_ECCALG; 764 pcr |= FMC2_PCR_BCHECC; 765 nand->ecc.bytes = 13; 766 break; 767 default: 768 /* Use FMC2 ECC BCH4 */ 769 pcr |= FMC2_PCR_ECCALG; 770 nand->ecc.bytes = 7; 771 break; 772 } 773 774 if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) { 775 nand->ecc.bytes++; 776 } 777 } 778 779 mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr); 780 } 781 782 static const struct nand_ctrl_ops ctrl_ops = { 783 .setup = stm32_fmc2_setup, 784 .exec = stm32_fmc2_exec 785 }; 786 787 int stm32_fmc2_init(void) 788 { 789 int fmc_node; 790 int fmc_subnode = 0; 791 int nchips = 0; 792 unsigned int i; 793 void *fdt = NULL; 794 const fdt32_t *cuint; 795 struct dt_node_info info; 796 797 if (fdt_get_address(&fdt) == 0) { 798 return -FDT_ERR_NOTFOUND; 799 } 800 801 fmc_node = dt_get_node(&info, -1, DT_FMC2_COMPAT); 802 if (fmc_node == -FDT_ERR_NOTFOUND) { 803 WARN("No FMC2 node found\n"); 804 return fmc_node; 805 } 806 807 if (info.status == DT_DISABLED) { 808 return -FDT_ERR_NOTFOUND; 809 } 810 811 stm32_fmc2.reg_base = info.base; 812 813 if ((info.clock < 0) || (info.reset < 0)) { 814 return -FDT_ERR_BADVALUE; 815 } 816 817 stm32_fmc2.clock_id = (unsigned long)info.clock; 818 stm32_fmc2.reset_id = (unsigned int)info.reset; 819 820 cuint = fdt_getprop(fdt, fmc_node, "reg", NULL); 821 if (cuint == NULL) { 822 return -FDT_ERR_BADVALUE; 823 } 824 825 cuint += 2; 826 827 for (i = 0U; i < MAX_CS; i++) { 828 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*cuint); 829 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 2)); 830 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 4)); 831 cuint += 6; 832 } 833 834 /* Pinctrl initialization */ 835 if (dt_set_pinctrl_config(fmc_node) != 0) { 836 return -FDT_ERR_BADVALUE; 837 } 838 839 /* Parse flash nodes */ 840 fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { 841 nchips++; 842 } 843 844 if (nchips != 1) { 845 WARN("Only one SLC NAND device supported\n"); 846 return -FDT_ERR_BADVALUE; 847 } 848 849 fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { 850 /* Get chip select */ 851 cuint = fdt_getprop(fdt, fmc_subnode, "reg", NULL); 852 if (cuint == NULL) { 853 WARN("Chip select not well defined\n"); 854 return -FDT_ERR_BADVALUE; 855 } 856 stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint); 857 VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel); 858 } 859 860 /* Enable Clock */ 861 stm32mp_clk_enable(stm32_fmc2.clock_id); 862 863 /* Reset IP */ 864 stm32mp_reset_assert(stm32_fmc2.reset_id); 865 stm32mp_reset_deassert(stm32_fmc2.reset_id); 866 867 /* Setup default IP registers */ 868 stm32_fmc2_ctrl_init(); 869 870 /* Setup default timings */ 871 stm32_fmc2_nand_setup_timing(); 872 873 /* Init NAND RAW framework */ 874 nand_raw_ctrl_init(&ctrl_ops); 875 876 return 0; 877 } 878