1 /* 2 * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <common/debug.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/raw_nand.h> 19 #include <drivers/st/stm32_fmc2_nand.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32mp_reset.h> 22 #include <lib/mmio.h> 23 #include <lib/utils_def.h> 24 25 /* Timeout for device interface reset */ 26 #define TIMEOUT_US_1_MS 1000U 27 28 /* FMC2 Compatibility */ 29 #define DT_FMC2_EBI_COMPAT "st,stm32mp1-fmc2-ebi" 30 #define DT_FMC2_NFC_COMPAT "st,stm32mp1-fmc2-nfc" 31 #define MAX_CS 2U 32 #define MAX_BANK 5U 33 34 /* FMC2 Controller Registers */ 35 #define FMC2_BCR1 0x00U 36 #define FMC2_PCR 0x80U 37 #define FMC2_SR 0x84U 38 #define FMC2_PMEM 0x88U 39 #define FMC2_PATT 0x8CU 40 #define FMC2_HECCR 0x94U 41 #define FMC2_BCHISR 0x254U 42 #define FMC2_BCHICR 0x258U 43 #define FMC2_BCHDSR0 0x27CU 44 #define FMC2_BCHDSR1 0x280U 45 #define FMC2_BCHDSR2 0x284U 46 #define FMC2_BCHDSR3 0x288U 47 #define FMC2_BCHDSR4 0x28CU 48 49 /* FMC2_BCR1 register */ 50 #define FMC2_BCR1_FMC2EN BIT(31) 51 /* FMC2_PCR register */ 52 #define FMC2_PCR_PWAITEN BIT(1) 53 #define FMC2_PCR_PBKEN BIT(2) 54 #define FMC2_PCR_PWID_MASK GENMASK_32(5, 4) 55 #define FMC2_PCR_PWID(x) (((x) << 4) & FMC2_PCR_PWID_MASK) 56 #define FMC2_PCR_PWID_8 0x0U 57 #define FMC2_PCR_PWID_16 0x1U 58 #define FMC2_PCR_ECCEN BIT(6) 59 #define FMC2_PCR_ECCALG BIT(8) 60 #define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9) 61 #define FMC2_PCR_TCLR(x) (((x) << 9) & FMC2_PCR_TCLR_MASK) 62 #define FMC2_PCR_TCLR_DEFAULT 0xFU 63 #define FMC2_PCR_TAR_MASK GENMASK_32(16, 13) 64 #define FMC2_PCR_TAR(x) (((x) << 13) & FMC2_PCR_TAR_MASK) 65 #define FMC2_PCR_TAR_DEFAULT 0xFU 66 #define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17) 67 #define FMC2_PCR_ECCSS(x) (((x) << 17) & FMC2_PCR_ECCSS_MASK) 68 #define FMC2_PCR_ECCSS_512 0x1U 69 #define FMC2_PCR_ECCSS_2048 0x3U 70 #define FMC2_PCR_BCHECC BIT(24) 71 #define FMC2_PCR_WEN BIT(25) 72 /* FMC2_SR register */ 73 #define FMC2_SR_NWRF BIT(6) 74 /* FMC2_PMEM register*/ 75 #define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0) 76 #define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 77 #define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 78 #define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 79 #define FMC2_PMEM_DEFAULT 0x0A0A0A0AU 80 /* FMC2_PATT register */ 81 #define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0) 82 #define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 83 #define FMC2_PATT_ATTHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 84 #define FMC2_PATT_ATTHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 85 #define FMC2_PATT_DEFAULT 0x0A0A0A0AU 86 /* FMC2_BCHISR register */ 87 #define FMC2_BCHISR_DERF BIT(1) 88 /* FMC2_BCHICR register */ 89 #define FMC2_BCHICR_CLEAR_IRQ GENMASK_32(4, 0) 90 /* FMC2_BCHDSR0 register */ 91 #define FMC2_BCHDSR0_DUE BIT(0) 92 #define FMC2_BCHDSR0_DEF BIT(1) 93 #define FMC2_BCHDSR0_DEN_MASK GENMASK_32(7, 4) 94 #define FMC2_BCHDSR0_DEN_SHIFT 4U 95 /* FMC2_BCHDSR1 register */ 96 #define FMC2_BCHDSR1_EBP1_MASK GENMASK_32(12, 0) 97 #define FMC2_BCHDSR1_EBP2_MASK GENMASK_32(28, 16) 98 #define FMC2_BCHDSR1_EBP2_SHIFT 16U 99 /* FMC2_BCHDSR2 register */ 100 #define FMC2_BCHDSR2_EBP3_MASK GENMASK_32(12, 0) 101 #define FMC2_BCHDSR2_EBP4_MASK GENMASK_32(28, 16) 102 #define FMC2_BCHDSR2_EBP4_SHIFT 16U 103 /* FMC2_BCHDSR3 register */ 104 #define FMC2_BCHDSR3_EBP5_MASK GENMASK_32(12, 0) 105 #define FMC2_BCHDSR3_EBP6_MASK GENMASK_32(28, 16) 106 #define FMC2_BCHDSR3_EBP6_SHIFT 16U 107 /* FMC2_BCHDSR4 register */ 108 #define FMC2_BCHDSR4_EBP7_MASK GENMASK_32(12, 0) 109 #define FMC2_BCHDSR4_EBP8_MASK GENMASK_32(28, 16) 110 #define FMC2_BCHDSR4_EBP8_SHIFT 16U 111 112 /* Timings */ 113 #define FMC2_THIZ 0x01U 114 #define FMC2_TIO 8000U 115 #define FMC2_TSYNC 3000U 116 #define FMC2_PCR_TIMING_MASK GENMASK_32(3, 0) 117 #define FMC2_PMEM_PATT_TIMING_MASK GENMASK_32(7, 0) 118 119 #define FMC2_BBM_LEN 2U 120 #define FMC2_MAX_ECC_BYTES 14U 121 #define TIMEOUT_US_10_MS 10000U 122 #define FMC2_PSEC_PER_MSEC (1000UL * 1000UL * 1000UL) 123 124 enum stm32_fmc2_ecc { 125 FMC2_ECC_HAM = 1U, 126 FMC2_ECC_BCH4 = 4U, 127 FMC2_ECC_BCH8 = 8U 128 }; 129 130 struct stm32_fmc2_cs_reg { 131 uintptr_t data_base; 132 uintptr_t cmd_base; 133 uintptr_t addr_base; 134 }; 135 136 struct stm32_fmc2_nand_timings { 137 uint8_t tclr; 138 uint8_t tar; 139 uint8_t thiz; 140 uint8_t twait; 141 uint8_t thold_mem; 142 uint8_t tset_mem; 143 uint8_t thold_att; 144 uint8_t tset_att; 145 }; 146 147 struct stm32_fmc2_nfc { 148 uintptr_t reg_base; 149 struct stm32_fmc2_cs_reg cs[MAX_CS]; 150 unsigned long clock_id; 151 unsigned int reset_id; 152 uint8_t cs_sel; 153 }; 154 155 static struct stm32_fmc2_nfc stm32_fmc2; 156 157 static uintptr_t fmc2_base(void) 158 { 159 return stm32_fmc2.reg_base; 160 } 161 162 static void stm32_fmc2_nand_setup_timing(void) 163 { 164 struct stm32_fmc2_nand_timings tims; 165 unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id); 166 unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); 167 unsigned long timing, tar, tclr, thiz, twait; 168 unsigned long tset_mem, tset_att, thold_mem, thold_att; 169 uint32_t pcr, pmem, patt; 170 171 tar = MAX(hclkp, NAND_TAR_MIN); 172 timing = div_round_up(tar, hclkp) - 1U; 173 tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 174 175 tclr = MAX(hclkp, NAND_TCLR_MIN); 176 timing = div_round_up(tclr, hclkp) - 1U; 177 tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 178 179 tims.thiz = FMC2_THIZ; 180 thiz = (tims.thiz + 1U) * hclkp; 181 182 /* 183 * tWAIT > tRP 184 * tWAIT > tWP 185 * tWAIT > tREA + tIO 186 */ 187 twait = MAX(hclkp, NAND_TRP_MIN); 188 twait = MAX(twait, NAND_TWP_MIN); 189 twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO); 190 timing = div_round_up(twait, hclkp); 191 tims.twait = CLAMP(timing, 1UL, 192 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 193 194 /* 195 * tSETUP_MEM > tCS - tWAIT 196 * tSETUP_MEM > tALS - tWAIT 197 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 198 */ 199 tset_mem = hclkp; 200 if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) { 201 tset_mem = NAND_TCS_MIN - twait; 202 } 203 if ((twait < NAND_TALS_MIN) && (tset_mem < (NAND_TALS_MIN - twait))) { 204 tset_mem = NAND_TALS_MIN - twait; 205 } 206 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 207 (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) { 208 tset_mem = NAND_TDS_MIN - (twait - thiz); 209 } 210 timing = div_round_up(tset_mem, hclkp); 211 tims.tset_mem = CLAMP(timing, 1UL, 212 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 213 214 /* 215 * tHOLD_MEM > tCH 216 * tHOLD_MEM > tREH - tSETUP_MEM 217 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 218 */ 219 thold_mem = MAX(hclkp, NAND_TCH_MIN); 220 if ((tset_mem < NAND_TREH_MIN) && 221 (thold_mem < (NAND_TREH_MIN - tset_mem))) { 222 thold_mem = NAND_TREH_MIN - tset_mem; 223 } 224 if (((tset_mem + twait) < NAND_TRC_MIN) && 225 (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) { 226 thold_mem = NAND_TRC_MIN - (tset_mem + twait); 227 } 228 if (((tset_mem + twait) < NAND_TWC_MIN) && 229 (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) { 230 thold_mem = NAND_TWC_MIN - (tset_mem + twait); 231 } 232 timing = div_round_up(thold_mem, hclkp); 233 tims.thold_mem = CLAMP(timing, 1UL, 234 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 235 236 /* 237 * tSETUP_ATT > tCS - tWAIT 238 * tSETUP_ATT > tCLS - tWAIT 239 * tSETUP_ATT > tALS - tWAIT 240 * tSETUP_ATT > tRHW - tHOLD_MEM 241 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 242 */ 243 tset_att = hclkp; 244 if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) { 245 tset_att = NAND_TCS_MIN - twait; 246 } 247 if ((twait < NAND_TCLS_MIN) && (tset_att < (NAND_TCLS_MIN - twait))) { 248 tset_att = NAND_TCLS_MIN - twait; 249 } 250 if ((twait < NAND_TALS_MIN) && (tset_att < (NAND_TALS_MIN - twait))) { 251 tset_att = NAND_TALS_MIN - twait; 252 } 253 if ((thold_mem < NAND_TRHW_MIN) && 254 (tset_att < (NAND_TRHW_MIN - thold_mem))) { 255 tset_att = NAND_TRHW_MIN - thold_mem; 256 } 257 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 258 (tset_att < (NAND_TDS_MIN - (twait - thiz)))) { 259 tset_att = NAND_TDS_MIN - (twait - thiz); 260 } 261 timing = div_round_up(tset_att, hclkp); 262 tims.tset_att = CLAMP(timing, 1UL, 263 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 264 265 /* 266 * tHOLD_ATT > tALH 267 * tHOLD_ATT > tCH 268 * tHOLD_ATT > tCLH 269 * tHOLD_ATT > tCOH 270 * tHOLD_ATT > tDH 271 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 272 * tHOLD_ATT > tADL - tSETUP_MEM 273 * tHOLD_ATT > tWH - tSETUP_MEM 274 * tHOLD_ATT > tWHR - tSETUP_MEM 275 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 276 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 277 */ 278 thold_att = MAX(hclkp, NAND_TALH_MIN); 279 thold_att = MAX(thold_att, NAND_TCH_MIN); 280 thold_att = MAX(thold_att, NAND_TCLH_MIN); 281 thold_att = MAX(thold_att, NAND_TCOH_MIN); 282 thold_att = MAX(thold_att, NAND_TDH_MIN); 283 if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) && 284 (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) { 285 thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem; 286 } 287 if ((tset_mem < NAND_TADL_MIN) && 288 (thold_att < (NAND_TADL_MIN - tset_mem))) { 289 thold_att = NAND_TADL_MIN - tset_mem; 290 } 291 if ((tset_mem < NAND_TWH_MIN) && 292 (thold_att < (NAND_TWH_MIN - tset_mem))) { 293 thold_att = NAND_TWH_MIN - tset_mem; 294 } 295 if ((tset_mem < NAND_TWHR_MIN) && 296 (thold_att < (NAND_TWHR_MIN - tset_mem))) { 297 thold_att = NAND_TWHR_MIN - tset_mem; 298 } 299 if (((tset_att + twait) < NAND_TRC_MIN) && 300 (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) { 301 thold_att = NAND_TRC_MIN - (tset_att + twait); 302 } 303 if (((tset_att + twait) < NAND_TWC_MIN) && 304 (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) { 305 thold_att = NAND_TWC_MIN - (tset_att + twait); 306 } 307 timing = div_round_up(thold_att, hclkp); 308 tims.thold_att = CLAMP(timing, 1UL, 309 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 310 311 VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n", 312 tims.tclr, tims.tar, tims.thiz, tims.twait, 313 tims.thold_mem, tims.tset_mem, 314 tims.thold_att, tims.tset_att); 315 316 /* Set tclr/tar timings */ 317 pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 318 pcr &= ~FMC2_PCR_TCLR_MASK; 319 pcr |= FMC2_PCR_TCLR(tims.tclr); 320 pcr &= ~FMC2_PCR_TAR_MASK; 321 pcr |= FMC2_PCR_TAR(tims.tar); 322 323 /* Set tset/twait/thold/thiz timings in common bank */ 324 pmem = FMC2_PMEM_MEMSET(tims.tset_mem); 325 pmem |= FMC2_PMEM_MEMWAIT(tims.twait); 326 pmem |= FMC2_PMEM_MEMHOLD(tims.thold_mem); 327 pmem |= FMC2_PMEM_MEMHIZ(tims.thiz); 328 329 /* Set tset/twait/thold/thiz timings in attribute bank */ 330 patt = FMC2_PATT_ATTSET(tims.tset_att); 331 patt |= FMC2_PATT_ATTWAIT(tims.twait); 332 patt |= FMC2_PATT_ATTHOLD(tims.thold_att); 333 patt |= FMC2_PATT_ATTHIZ(tims.thiz); 334 335 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 336 mmio_write_32(fmc2_base() + FMC2_PMEM, pmem); 337 mmio_write_32(fmc2_base() + FMC2_PATT, patt); 338 } 339 340 static void stm32_fmc2_set_buswidth_16(bool set) 341 { 342 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK, 343 (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U)); 344 } 345 346 static void stm32_fmc2_set_ecc(bool enable) 347 { 348 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN, 349 (enable ? FMC2_PCR_ECCEN : 0U)); 350 } 351 352 static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer, 353 uint8_t *ecc) 354 { 355 uint8_t xor_ecc_ones; 356 uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b; 357 union { 358 uint32_t val; 359 uint8_t bytes[4]; 360 } xor_ecc; 361 362 /* Page size--------ECC_Code Size 363 * 256---------------22 bits LSB (ECC_CODE & 0x003FFFFF) 364 * 512---------------24 bits (ECC_CODE & 0x00FFFFFF) 365 * 1024--------------26 bits (ECC_CODE & 0x03FFFFFF) 366 * 2048--------------28 bits (ECC_CODE & 0x0FFFFFFF) 367 * 4096--------------30 bits (ECC_CODE & 0x3FFFFFFF) 368 * 8192--------------32 bits (ECC_CODE & 0xFFFFFFFF) 369 */ 370 371 /* For Page size 512, ECC_Code size 24 bits */ 372 xor_ecc_1b = ecc[0] ^ eccbuffer[0]; 373 xor_ecc_2b = ecc[1] ^ eccbuffer[1]; 374 xor_ecc_3b = ecc[2] ^ eccbuffer[2]; 375 376 xor_ecc.val = 0U; 377 xor_ecc.bytes[2] = xor_ecc_3b; 378 xor_ecc.bytes[1] = xor_ecc_2b; 379 xor_ecc.bytes[0] = xor_ecc_1b; 380 381 if (xor_ecc.val == 0U) { 382 return 0; /* No Error */ 383 } 384 385 xor_ecc_ones = __builtin_popcount(xor_ecc.val); 386 if (xor_ecc_ones < 23U) { 387 if (xor_ecc_ones == 12U) { 388 uint16_t bit_address, byte_address; 389 390 /* Correctable ERROR */ 391 bit_address = ((xor_ecc_1b >> 1) & BIT(0)) | 392 ((xor_ecc_1b >> 2) & BIT(1)) | 393 ((xor_ecc_1b >> 3) & BIT(2)); 394 395 byte_address = ((xor_ecc_1b >> 7) & BIT(0)) | 396 ((xor_ecc_2b) & BIT(1)) | 397 ((xor_ecc_2b >> 1) & BIT(2)) | 398 ((xor_ecc_2b >> 2) & BIT(3)) | 399 ((xor_ecc_2b >> 3) & BIT(4)) | 400 ((xor_ecc_3b << 4) & BIT(5)) | 401 ((xor_ecc_3b << 3) & BIT(6)) | 402 ((xor_ecc_3b << 2) & BIT(7)) | 403 ((xor_ecc_3b << 1) & BIT(8)); 404 405 /* Correct bit error in the data */ 406 buffer[byte_address] = 407 buffer[byte_address] ^ BIT(bit_address); 408 VERBOSE("Hamming: 1 ECC error corrected\n"); 409 410 return 0; 411 } 412 413 /* Non Correctable ERROR */ 414 ERROR("%s: Uncorrectable ECC Errors\n", __func__); 415 return -1; 416 } 417 418 /* ECC ERROR */ 419 ERROR("%s: Hamming correction error\n", __func__); 420 return -1; 421 } 422 423 424 static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc) 425 { 426 uint32_t heccr; 427 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 428 429 while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) { 430 if (timeout_elapsed(timeout)) { 431 return -ETIMEDOUT; 432 } 433 } 434 435 heccr = mmio_read_32(fmc2_base() + FMC2_HECCR); 436 437 ecc[0] = heccr; 438 ecc[1] = heccr >> 8; 439 ecc[2] = heccr >> 16; 440 441 /* Disable ECC */ 442 stm32_fmc2_set_ecc(false); 443 444 return 0; 445 } 446 447 static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize) 448 { 449 uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4; 450 uint16_t pos[8]; 451 int i, den; 452 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 453 454 while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) & 455 FMC2_BCHISR_DERF) == 0U) { 456 if (timeout_elapsed(timeout)) { 457 return -ETIMEDOUT; 458 } 459 } 460 461 bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0); 462 bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1); 463 bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2); 464 bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3); 465 bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4); 466 467 /* Disable ECC */ 468 stm32_fmc2_set_ecc(false); 469 470 /* No error found */ 471 if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) { 472 return 0; 473 } 474 475 /* Too many errors detected */ 476 if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) { 477 return -EBADMSG; 478 } 479 480 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; 481 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; 482 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; 483 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; 484 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; 485 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; 486 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; 487 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; 488 489 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; 490 for (i = 0; i < den; i++) { 491 if (pos[i] < (eccsize * 8U)) { 492 uint8_t bitmask = BIT(pos[i] % 8U); 493 uint32_t offset = pos[i] / 8U; 494 495 *(buffer + offset) ^= bitmask; 496 } 497 } 498 499 return 0; 500 } 501 502 static void stm32_fmc2_hwctl(struct nand_device *nand) 503 { 504 stm32_fmc2_set_ecc(false); 505 506 if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) { 507 mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN); 508 mmio_write_32(fmc2_base() + FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ); 509 } 510 511 stm32_fmc2_set_ecc(true); 512 } 513 514 static int stm32_fmc2_read_page(struct nand_device *nand, 515 unsigned int page, uintptr_t buffer) 516 { 517 unsigned int eccsize = nand->ecc.size; 518 unsigned int eccbytes = nand->ecc.bytes; 519 unsigned int eccsteps = nand->page_size / eccsize; 520 uint8_t ecc_corr[FMC2_MAX_ECC_BYTES]; 521 uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U}; 522 uint8_t *p; 523 unsigned int i; 524 unsigned int s; 525 int ret; 526 527 VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer); 528 529 ret = nand_read_page_cmd(page, 0U, 0U, 0U); 530 if (ret != 0) { 531 return ret; 532 } 533 534 for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer; 535 s < eccsteps; 536 s++, i += eccbytes, p += eccsize) { 537 stm32_fmc2_hwctl(nand); 538 539 /* Read the NAND page sector (512 bytes) */ 540 ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p, 541 eccsize); 542 if (ret != 0) { 543 return ret; 544 } 545 546 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 547 ret = stm32_fmc2_ham_calculate(p, ecc_cal); 548 if (ret != 0) { 549 return ret; 550 } 551 } 552 553 /* Read the corresponding ECC bytes */ 554 ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr, 555 eccbytes); 556 if (ret != 0) { 557 return ret; 558 } 559 560 /* Correct the data */ 561 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 562 ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal); 563 } else { 564 ret = stm32_fmc2_bch_correct(p, eccsize); 565 } 566 567 if (ret != 0) { 568 return ret; 569 } 570 } 571 572 return 0; 573 } 574 575 static void stm32_fmc2_read_data(struct nand_device *nand, 576 uint8_t *buff, unsigned int length, 577 bool use_bus8) 578 { 579 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 580 581 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 582 stm32_fmc2_set_buswidth_16(false); 583 } 584 585 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 586 *buff = mmio_read_8(data_base); 587 buff += sizeof(uint8_t); 588 length -= sizeof(uint8_t); 589 } 590 591 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 592 (length >= sizeof(uint16_t))) { 593 *(uint16_t *)buff = mmio_read_16(data_base); 594 buff += sizeof(uint16_t); 595 length -= sizeof(uint16_t); 596 } 597 598 /* 32bit aligned */ 599 while (length >= sizeof(uint32_t)) { 600 *(uint32_t *)buff = mmio_read_32(data_base); 601 buff += sizeof(uint32_t); 602 length -= sizeof(uint32_t); 603 } 604 605 /* Read remaining bytes */ 606 if (length >= sizeof(uint16_t)) { 607 *(uint16_t *)buff = mmio_read_16(data_base); 608 buff += sizeof(uint16_t); 609 length -= sizeof(uint16_t); 610 } 611 612 if (length != 0U) { 613 *buff = mmio_read_8(data_base); 614 } 615 616 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 617 /* Reconfigure bus width to 16-bit */ 618 stm32_fmc2_set_buswidth_16(true); 619 } 620 } 621 622 static void stm32_fmc2_write_data(struct nand_device *nand, 623 uint8_t *buff, unsigned int length, 624 bool use_bus8) 625 { 626 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 627 628 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 629 /* Reconfigure bus width to 8-bit */ 630 stm32_fmc2_set_buswidth_16(false); 631 } 632 633 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 634 mmio_write_8(data_base, *buff); 635 buff += sizeof(uint8_t); 636 length -= sizeof(uint8_t); 637 } 638 639 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 640 (length >= sizeof(uint16_t))) { 641 mmio_write_16(data_base, *(uint16_t *)buff); 642 buff += sizeof(uint16_t); 643 length -= sizeof(uint16_t); 644 } 645 646 /* 32bits aligned */ 647 while (length >= sizeof(uint32_t)) { 648 mmio_write_32(data_base, *(uint32_t *)buff); 649 buff += sizeof(uint32_t); 650 length -= sizeof(uint32_t); 651 } 652 653 /* Read remaining bytes */ 654 if (length >= sizeof(uint16_t)) { 655 mmio_write_16(data_base, *(uint16_t *)buff); 656 buff += sizeof(uint16_t); 657 length -= sizeof(uint16_t); 658 } 659 660 if (length != 0U) { 661 mmio_write_8(data_base, *buff); 662 } 663 664 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 665 /* Reconfigure bus width to 16-bit */ 666 stm32_fmc2_set_buswidth_16(true); 667 } 668 } 669 670 static void stm32_fmc2_ctrl_init(void) 671 { 672 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 673 uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1); 674 675 /* Enable wait feature and NAND flash memory bank */ 676 pcr |= FMC2_PCR_PWAITEN; 677 pcr |= FMC2_PCR_PBKEN; 678 679 /* Set buswidth to 8 bits mode for identification */ 680 pcr &= ~FMC2_PCR_PWID_MASK; 681 682 /* ECC logic is disabled */ 683 pcr &= ~FMC2_PCR_ECCEN; 684 685 /* Default mode */ 686 pcr &= ~FMC2_PCR_ECCALG; 687 pcr &= ~FMC2_PCR_BCHECC; 688 pcr &= ~FMC2_PCR_WEN; 689 690 /* Set default ECC sector size */ 691 pcr &= ~FMC2_PCR_ECCSS_MASK; 692 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); 693 694 /* Set default TCLR/TAR timings */ 695 pcr &= ~FMC2_PCR_TCLR_MASK; 696 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); 697 pcr &= ~FMC2_PCR_TAR_MASK; 698 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); 699 700 /* Enable FMC2 controller */ 701 bcr1 |= FMC2_BCR1_FMC2EN; 702 703 mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1); 704 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 705 mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT); 706 mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT); 707 } 708 709 static int stm32_fmc2_exec(struct nand_req *req) 710 { 711 int ret = 0; 712 713 switch (req->type & NAND_REQ_MASK) { 714 case NAND_REQ_CMD: 715 VERBOSE("Write CMD %x\n", (uint8_t)req->type); 716 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, 717 (uint8_t)req->type); 718 break; 719 case NAND_REQ_ADDR: 720 VERBOSE("Write ADDR %x\n", *(req->addr)); 721 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, 722 *(req->addr)); 723 break; 724 case NAND_REQ_DATAIN: 725 VERBOSE("Read data\n"); 726 stm32_fmc2_read_data(req->nand, req->addr, req->length, 727 ((req->type & NAND_REQ_BUS_WIDTH_8) != 728 0U)); 729 break; 730 case NAND_REQ_DATAOUT: 731 VERBOSE("Write data\n"); 732 stm32_fmc2_write_data(req->nand, req->addr, req->length, 733 ((req->type & NAND_REQ_BUS_WIDTH_8) != 734 0U)); 735 break; 736 case NAND_REQ_WAIT: 737 VERBOSE("WAIT Ready\n"); 738 ret = nand_wait_ready(req->delay_ms); 739 break; 740 default: 741 ret = -EINVAL; 742 break; 743 }; 744 745 return ret; 746 } 747 748 static void stm32_fmc2_setup(struct nand_device *nand) 749 { 750 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 751 752 /* Set buswidth */ 753 pcr &= ~FMC2_PCR_PWID_MASK; 754 if (nand->buswidth == NAND_BUS_WIDTH_16) { 755 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16); 756 } 757 758 if (nand->ecc.mode == NAND_ECC_HW) { 759 nand->mtd_read_page = stm32_fmc2_read_page; 760 761 pcr &= ~FMC2_PCR_ECCALG; 762 pcr &= ~FMC2_PCR_BCHECC; 763 764 pcr &= ~FMC2_PCR_ECCSS_MASK; 765 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); 766 767 switch (nand->ecc.max_bit_corr) { 768 case FMC2_ECC_HAM: 769 nand->ecc.bytes = 3; 770 break; 771 case FMC2_ECC_BCH8: 772 pcr |= FMC2_PCR_ECCALG; 773 pcr |= FMC2_PCR_BCHECC; 774 nand->ecc.bytes = 13; 775 break; 776 default: 777 /* Use FMC2 ECC BCH4 */ 778 pcr |= FMC2_PCR_ECCALG; 779 nand->ecc.bytes = 7; 780 break; 781 } 782 783 if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) { 784 nand->ecc.bytes++; 785 } 786 } 787 788 mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr); 789 } 790 791 static const struct nand_ctrl_ops ctrl_ops = { 792 .setup = stm32_fmc2_setup, 793 .exec = stm32_fmc2_exec 794 }; 795 796 int stm32_fmc2_init(void) 797 { 798 int fmc_ebi_node; 799 int fmc_nfc_node; 800 int fmc_flash_node = 0; 801 int nchips = 0; 802 unsigned int i; 803 void *fdt = NULL; 804 const fdt32_t *cuint; 805 struct dt_node_info info; 806 uintptr_t bank_address[MAX_BANK] = { 0, 0, 0, 0, 0 }; 807 uint8_t bank_assigned = 0; 808 uint8_t bank; 809 int ret; 810 811 if (fdt_get_address(&fdt) == 0) { 812 return -FDT_ERR_NOTFOUND; 813 } 814 815 fmc_ebi_node = dt_get_node(&info, -1, DT_FMC2_EBI_COMPAT); 816 if (fmc_ebi_node < 0) { 817 return fmc_ebi_node; 818 } 819 820 if (info.status == DT_DISABLED) { 821 return -FDT_ERR_NOTFOUND; 822 } 823 824 stm32_fmc2.reg_base = info.base; 825 826 if ((info.clock < 0) || (info.reset < 0)) { 827 return -FDT_ERR_BADVALUE; 828 } 829 830 stm32_fmc2.clock_id = (unsigned long)info.clock; 831 stm32_fmc2.reset_id = (unsigned int)info.reset; 832 833 cuint = fdt_getprop(fdt, fmc_ebi_node, "ranges", NULL); 834 if (cuint == NULL) { 835 return -FDT_ERR_BADVALUE; 836 } 837 838 for (i = 0U; i < MAX_BANK; i++) { 839 bank = fdt32_to_cpu(*cuint); 840 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { 841 return -FDT_ERR_BADVALUE; 842 } 843 bank_assigned |= BIT(bank); 844 bank_address[bank] = fdt32_to_cpu(*(cuint + 2)); 845 cuint += 4; 846 } 847 848 /* Pinctrl initialization */ 849 if (dt_set_pinctrl_config(fmc_ebi_node) != 0) { 850 return -FDT_ERR_BADVALUE; 851 } 852 853 /* Parse NFC controller node */ 854 fmc_nfc_node = fdt_node_offset_by_compatible(fdt, fmc_ebi_node, 855 DT_FMC2_NFC_COMPAT); 856 if (fmc_nfc_node < 0) { 857 return fmc_nfc_node; 858 } 859 860 if (fdt_get_status(fmc_nfc_node) == DT_DISABLED) { 861 return -FDT_ERR_NOTFOUND; 862 } 863 864 cuint = fdt_getprop(fdt, fmc_nfc_node, "reg", NULL); 865 if (cuint == NULL) { 866 return -FDT_ERR_BADVALUE; 867 } 868 869 for (i = 0U; i < MAX_CS; i++) { 870 bank = fdt32_to_cpu(*cuint); 871 if (bank >= MAX_BANK) { 872 return -FDT_ERR_BADVALUE; 873 } 874 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) + 875 bank_address[bank]; 876 877 bank = fdt32_to_cpu(*(cuint + 3)); 878 if (bank >= MAX_BANK) { 879 return -FDT_ERR_BADVALUE; 880 } 881 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) + 882 bank_address[bank]; 883 884 bank = fdt32_to_cpu(*(cuint + 6)); 885 if (bank >= MAX_BANK) { 886 return -FDT_ERR_BADVALUE; 887 } 888 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) + 889 bank_address[bank]; 890 891 cuint += 9; 892 } 893 894 /* Parse flash nodes */ 895 fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) { 896 nchips++; 897 } 898 899 if (nchips != 1) { 900 WARN("Only one SLC NAND device supported\n"); 901 return -FDT_ERR_BADVALUE; 902 } 903 904 fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) { 905 /* Get chip select */ 906 cuint = fdt_getprop(fdt, fmc_flash_node, "reg", NULL); 907 if (cuint == NULL) { 908 WARN("Chip select not well defined\n"); 909 return -FDT_ERR_BADVALUE; 910 } 911 912 stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint); 913 if (stm32_fmc2.cs_sel >= MAX_CS) { 914 return -FDT_ERR_BADVALUE; 915 } 916 917 VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel); 918 } 919 920 /* Enable Clock */ 921 stm32mp_clk_enable(stm32_fmc2.clock_id); 922 923 /* Reset IP */ 924 ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); 925 if (ret != 0) { 926 panic(); 927 } 928 ret = stm32mp_reset_deassert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); 929 if (ret != 0) { 930 panic(); 931 } 932 933 /* Setup default IP registers */ 934 stm32_fmc2_ctrl_init(); 935 936 /* Setup default timings */ 937 stm32_fmc2_nand_setup_timing(); 938 939 /* Init NAND RAW framework */ 940 nand_raw_ctrl_init(&ctrl_ops); 941 942 return 0; 943 } 944