1 /* 2 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/st/etzpc.h> 14 #include <dt-bindings/soc/st,stm32-etzpc.h> 15 #include <lib/mmio.h> 16 #include <lib/utils_def.h> 17 #include <libfdt.h> 18 19 #include <platform_def.h> 20 21 /* Device Tree related definitions */ 22 #define ETZPC_COMPAT "st,stm32-etzpc" 23 #define ETZPC_LOCK_MASK 0x1U 24 #define ETZPC_MODE_SHIFT 8 25 #define ETZPC_MODE_MASK GENMASK(1, 0) 26 #define ETZPC_ID_SHIFT 16 27 #define ETZPC_ID_MASK GENMASK(7, 0) 28 29 /* ID Registers */ 30 #define ETZPC_TZMA0_SIZE 0x000U 31 #define ETZPC_DECPROT0 0x010U 32 #define ETZPC_DECPROT_LOCK0 0x030U 33 #define ETZPC_HWCFGR 0x3F0U 34 #define ETZPC_VERR 0x3F4U 35 36 /* ID Registers fields */ 37 #define ETZPC_TZMA0_SIZE_LOCK BIT(31) 38 #define ETZPC_DECPROT0_MASK GENMASK(1, 0) 39 #define ETZPC_HWCFGR_NUM_TZMA_SHIFT 0 40 #define ETZPC_HWCFGR_NUM_PER_SEC_SHIFT 8 41 #define ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT 16 42 #define ETZPC_HWCFGR_CHUNCKS1N4_SHIFT 24 43 44 #define DECPROT_SHIFT 1 45 #define IDS_PER_DECPROT_REGS 16U 46 #define IDS_PER_DECPROT_LOCK_REGS 32U 47 48 /* 49 * etzpc_instance. 50 * base : register base address set during init given by user 51 * chunk_size : supported TZMA size steps 52 * num_tzma: number of TZMA zone read from register at init 53 * num_ahb_sec : number of securable AHB master zone read from register 54 * num_per_sec : number of securable AHB & APB Peripherals read from register 55 * revision : IP revision read from register at init 56 */ 57 struct etzpc_instance { 58 uintptr_t base; 59 uint8_t chunck_size; 60 uint8_t num_tzma; 61 uint8_t num_per_sec; 62 uint8_t num_ahb_sec; 63 uint8_t revision; 64 }; 65 66 /* Only 1 instance of the ETZPC is expected per platform */ 67 static struct etzpc_instance etzpc_dev; 68 69 /* 70 * Implementation uses uint8_t to store each securable DECPROT configuration. 71 * When resuming from deep suspend, the DECPROT configurations are restored. 72 */ 73 #define PERIPH_LOCK_BIT BIT(7) 74 #define PERIPH_ATTR_MASK GENMASK(2, 0) 75 76 #if ENABLE_ASSERTIONS 77 static bool valid_decprot_id(unsigned int id) 78 { 79 return id < (unsigned int)etzpc_dev.num_per_sec; 80 } 81 82 static bool valid_tzma_id(unsigned int id) 83 { 84 return id < (unsigned int)etzpc_dev.num_tzma; 85 } 86 #endif 87 88 /* 89 * etzpc_configure_decprot : Load a DECPROT configuration 90 * decprot_id : ID of the IP 91 * decprot_attr : Restriction access attribute 92 */ 93 void etzpc_configure_decprot(uint32_t decprot_id, 94 enum etzpc_decprot_attributes decprot_attr) 95 { 96 uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS); 97 uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; 98 uint32_t masked_decprot = (uint32_t)decprot_attr & ETZPC_DECPROT0_MASK; 99 100 assert(valid_decprot_id(decprot_id)); 101 102 mmio_clrsetbits_32(etzpc_dev.base + ETZPC_DECPROT0 + offset, 103 (uint32_t)ETZPC_DECPROT0_MASK << shift, 104 masked_decprot << shift); 105 } 106 107 /* 108 * etzpc_get_decprot : Get the DECPROT attribute 109 * decprot_id : ID of the IP 110 * return : Attribute of this DECPROT 111 */ 112 enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id) 113 { 114 uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS); 115 uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; 116 uintptr_t base_decprot = etzpc_dev.base + offset; 117 uint32_t value; 118 119 assert(valid_decprot_id(decprot_id)); 120 121 value = (mmio_read_32(base_decprot + ETZPC_DECPROT0) >> shift) & 122 ETZPC_DECPROT0_MASK; 123 124 return (enum etzpc_decprot_attributes)value; 125 } 126 127 /* 128 * etzpc_lock_decprot : Lock access to the DECPROT attribute 129 * decprot_id : ID of the IP 130 */ 131 void etzpc_lock_decprot(uint32_t decprot_id) 132 { 133 uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_LOCK_REGS); 134 uint32_t shift = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS); 135 uintptr_t base_decprot = etzpc_dev.base + offset; 136 137 assert(valid_decprot_id(decprot_id)); 138 139 mmio_write_32(base_decprot + ETZPC_DECPROT_LOCK0, shift); 140 } 141 142 /* 143 * etzpc_configure_tzma : Configure the target TZMA read only size 144 * tzma_id : ID of the memory 145 * tzma_value : read-only size 146 */ 147 void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value) 148 { 149 assert(valid_tzma_id(tzma_id)); 150 151 mmio_write_32(etzpc_dev.base + ETZPC_TZMA0_SIZE + 152 (sizeof(uint32_t) * tzma_id), tzma_value); 153 } 154 155 /* 156 * etzpc_get_tzma : Get the target TZMA read only size 157 * tzma_id : TZMA ID 158 * return : Size of read only size 159 */ 160 uint16_t etzpc_get_tzma(uint32_t tzma_id) 161 { 162 assert(valid_tzma_id(tzma_id)); 163 164 return (uint16_t)mmio_read_32(etzpc_dev.base + ETZPC_TZMA0_SIZE + 165 (sizeof(uint32_t) * tzma_id)); 166 } 167 168 /* 169 * etzpc_lock_tzma : Lock the target TZMA 170 * tzma_id : TZMA ID 171 */ 172 void etzpc_lock_tzma(uint32_t tzma_id) 173 { 174 assert(valid_tzma_id(tzma_id)); 175 176 mmio_setbits_32(etzpc_dev.base + ETZPC_TZMA0_SIZE + 177 (sizeof(uint32_t) * tzma_id), ETZPC_TZMA0_SIZE_LOCK); 178 } 179 180 /* 181 * etzpc_get_lock_tzma : Return the lock status of the target TZMA 182 * tzma_id : TZMA ID 183 * return : True if TZMA is locked, false otherwise 184 */ 185 bool etzpc_get_lock_tzma(uint32_t tzma_id) 186 { 187 uint32_t tzma_size; 188 189 assert(valid_tzma_id(tzma_id)); 190 191 tzma_size = mmio_read_32(etzpc_dev.base + ETZPC_TZMA0_SIZE + 192 (sizeof(uint32_t) * tzma_id)); 193 194 return (tzma_size & ETZPC_TZMA0_SIZE_LOCK) != 0; 195 } 196 197 /* 198 * etzpc_get_num_per_sec : Return the DECPROT ID limit value 199 */ 200 uint8_t etzpc_get_num_per_sec(void) 201 { 202 return etzpc_dev.num_per_sec; 203 } 204 205 /* 206 * etzpc_get_revision : Return the ETZPC IP revision 207 */ 208 uint8_t etzpc_get_revision(void) 209 { 210 return etzpc_dev.revision; 211 } 212 213 /* 214 * etzpc_get_base_address : Return the ETZPC IP base address 215 */ 216 uintptr_t etzpc_get_base_address(void) 217 { 218 return etzpc_dev.base; 219 } 220 221 /* 222 * etzpc_init : Initialize the ETZPC driver 223 * Return 0 on success and a negative errno on failure 224 */ 225 int etzpc_init(void) 226 { 227 uint32_t hwcfg; 228 229 etzpc_dev.base = STM32MP1_ETZPC_BASE; 230 231 hwcfg = mmio_read_32(etzpc_dev.base + ETZPC_HWCFGR); 232 233 etzpc_dev.num_tzma = (uint8_t)(hwcfg >> ETZPC_HWCFGR_NUM_TZMA_SHIFT); 234 etzpc_dev.num_per_sec = (uint8_t)(hwcfg >> 235 ETZPC_HWCFGR_NUM_PER_SEC_SHIFT); 236 etzpc_dev.num_ahb_sec = (uint8_t)(hwcfg >> 237 ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT); 238 etzpc_dev.chunck_size = (uint8_t)(hwcfg >> 239 ETZPC_HWCFGR_CHUNCKS1N4_SHIFT); 240 241 etzpc_dev.revision = mmio_read_8(etzpc_dev.base + ETZPC_VERR); 242 243 VERBOSE("ETZPC version 0x%x", etzpc_dev.revision); 244 245 return 0; 246 } 247