1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdio.h> 8 9 #include <common/debug.h> 10 11 #include <ddrphy_phyinit.h> 12 13 #include <lib/mmio.h> 14 15 #include <platform_def.h> 16 17 /* 18 * Writes local memory content into the SRAM via APB interface. 19 * 20 * This function issued APB writes commands to SRAM address based on values 21 * stored in a local PhyInit array that contains consolidated IMEM and DMEM 22 * data. 23 * @param[in] mem[] Local memory array. 24 * @param[in] mem_offset offset index. if provided, skips to the offset index 25 * from the local array and issues APB commands from mem_offset to mem_size. 26 * @param[in] mem_size size of the memroy (in mem array index) 27 * @returns void 28 */ 29 void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size) 30 { 31 uint32_t index; 32 33 /* 34 * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. 35 * This allows the memory controller unrestricted access to the configuration CSRs. 36 */ 37 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), 38 0x0U); 39 40 for (index = 0U; index < mem_size / sizeof(uint32_t); index++) { 41 uint32_t data = mem[index]; 42 43 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + mem_offset))), 44 data & 0xFFFFU); 45 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + 1 + mem_offset))), 46 (data >> 16) & 0xFFFFU); 47 } 48 49 /* 50 * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. 51 * This allows the firmware unrestricted access to the configuration CSRs. 52 */ 53 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), 54 0x1U); 55 } 56 57 /* Similar function for message block */ 58 void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size) 59 { 60 uint32_t index; 61 62 /* 63 * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. 64 * This allows the memory controller unrestricted access to the configuration CSRs. 65 */ 66 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), 67 0x0U); 68 69 for (index = 0U; index < mem_size / sizeof(uint16_t); index++) { 70 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (index + mem_offset))), mem[index]); 71 } 72 73 /* 74 * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. 75 * This allows the firmware unrestricted access to the configuration CSRs. 76 */ 77 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), 78 0x1U); 79 } 80