1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MNPMUSRAMMSGBLOCK_DDR4_H 8 #define MNPMUSRAMMSGBLOCK_DDR4_H 9 10 /* DDR4U_1D training firmware message block structure 11 * 12 * Please refer to the Training Firmware App Note for futher information about 13 * the usage for Message Block. 14 */ 15 struct pmu_smb_ddr_1d { 16 uint8_t reserved00; /* 17 * Byte offset 0x00, CSR Addr 0x54000, Direction=In 18 * reserved00[0:4] RFU, must be zero 19 * 20 * reserved00[5] = Train vrefDAC0 During Read Deskew 21 * 0x1 = Read Deskew will begin by enabling and roughly 22 * training the phy's per-lane reference voltages. 23 * Training the vrefDACs CSRs will increase the maximum 1D 24 * training time by around half a millisecond, but will 25 * improve 1D training accuracy on systems with 26 * significant voltage-offsets between lane read eyes. 27 * 0x0 = Read Deskew will assume the messageblock's 28 * phyVref setting will work for all lanes. 29 * 30 * reserved00[6] = Enable High Effort WrDQ1D 31 * 0x1 = WrDQ1D will conditionally retry training at 32 * several extra RxClkDly Timings. This will increase the 33 * maximum 1D training time by up to 4 extra iterations of 34 * WrDQ1D. This is only required in systems that suffer 35 * from very large, asymmetric eye-collapse when receiving 36 * PRBS patterns. 37 * 0x0 = WrDQ1D assume rxClkDly values found by SI 38 * Friendly RdDqs1D will work for receiving PRBS patterns 39 * 40 * reserved00[7] = Optimize for the special hard macros in 41 * TSMC28. 42 * 0x1 = set if the phy being trained was manufactured in 43 * any TSMC28 process node. 44 * 0x0 = otherwise, when not training a TSMC28 phy, leave 45 * this field as 0. 46 */ 47 uint8_t msgmisc; /* 48 * Byte offset 0x01, CSR Addr 0x54000, Direction=In 49 * Contains various global options for training. 50 * 51 * Bit fields: 52 * 53 * msgmisc[0] = MTESTEnable 54 * 0x1 = Pulse primary digital test output bump at the end 55 * of each major training stage. This enables observation 56 * of training stage completion by observing the digital 57 * test output. 58 * 0x0 = Do not pulse primary digital test output bump 59 * 60 * msgmisc[1] = SimulationOnlyReset 61 * 0x1 = Verilog only simulation option to shorten 62 * duration of DRAM reset pulse length to 1ns. 63 * Must never be set to 1 in silicon. 64 * 0x0 = Use reset pulse length specified by JEDEC 65 * standard. 66 * 67 * msgmisc[2] = SimulationOnlyTraining 68 * 0x1 = Verilog only simulation option to shorten the 69 * duration of the training steps by performing fewer 70 * iterations. 71 * Must never be set to 1 in silicon. 72 * 0x0 = Use standard training duration. 73 * 74 * msgmisc[3] = RFU, must be zero 75 * 0x1 = Program user characterized Vref DQ values per 76 * DDR4 DRAM device. The message block vrefdqr*nib* fields 77 * must be populated with the desired per device Vref DQs 78 * when using this option. Note: this option is not 79 * applicable in 2D training because these values are 80 * explicitly trained in 2D. 81 * 0x0 = Program Vref DQ for all DDR4 devices with the 82 * single value provided in mr6 message block field 83 * 84 * msgmisc[4] = Suppress streaming messages, including 85 * assertions, regardless of hdtctrl setting. 86 * Stage Completion messages, as well as training completion 87 * and error messages are still sent depending on hdtctrl 88 * setting. 89 * 90 * msgmisc[5] = PerByteMaxRdLat 91 * 0x1 = Each DBYTE will return dfi_rddata_valid at the 92 * lowest possible latency. This may result in unaligned 93 * data between bytes to be returned to the DFI. 94 * 0x0 = Every DBYTE will return dfi_rddata_valid 95 * simultaneously. This will ensure that data bytes will 96 * return aligned accesses to the DFI. 97 * 98 * msgmisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, 99 * otherwise RFU, must be zero) 100 * 0x1 = Support rank populated with a subset of byte, but 101 * where even-odd pair of rank support all the byte 102 * 0x0 = All rank populated with all the byte (tyical 103 * configuration) 104 * 105 * msgmisc[7] RFU, must be zero 106 * 107 * Notes: 108 * 109 * - SimulationOnlyReset and SimulationOnlyTraining can be 110 * used to speed up simulation run times, and must never 111 * be used in real silicon. Some VIPs may have checks on 112 * DRAM reset parameters that may need to be disabled when 113 * using SimulationOnlyReset. 114 */ 115 uint16_t pmurevision; /* 116 * Byte offset 0x02, CSR Addr 0x54001, Direction=Out 117 * PMU firmware revision ID 118 * After training is run, this address will contain the 119 * revision ID of the firmware. 120 * Please reference this revision ID when filing support 121 * cases. 122 */ 123 uint8_t pstate; /* 124 * Byte offset 0x04, CSR Addr 0x54002, Direction=In 125 * Must be set to the target pstate to be trained 126 * 0x0 = pstate 0 127 * 0x1 = pstate 1 128 * 0x2 = pstate 2 129 * 0x3 = pstate 3 130 * All other encodings are reserved 131 */ 132 uint8_t pllbypassen; /* 133 * Byte offset 0x05, CSR Addr 0x54002, Direction=In 134 * Set according to whether target pstate uses PHY PLL 135 * bypass 136 * 0x0 = PHY PLL is enabled for target pstate 137 * 0x1 = PHY PLL is bypassed for target pstate 138 */ 139 uint16_t dramfreq; /* 140 * Byte offset 0x06, CSR Addr 0x54003, Direction=In 141 * DDR data rate for the target pstate in units of MT/s. 142 * For example enter 0x0640 for DDR1600. 143 */ 144 uint8_t dfifreqratio; /* 145 * Byte offset 0x08, CSR Addr 0x54004, Direction=In 146 * Frequency ratio betwen DfiCtlClk and SDRAM memclk. 147 * 0x1 = 1:1 148 * 0x2 = 1:2 149 * 0x4 = 1:4 150 */ 151 uint8_t bpznresval; /* 152 * Byte offset 0x09, CSR Addr 0x54004, Direction=In 153 * Overwrite the value of precision resistor connected to 154 * Phy BP_ZN 155 * 0x00 = Do not program. Use current CSR value. 156 * 0xf0 = 240 Ohm 157 * 0x78 = 120 Ohm 158 * 0x28 = 40 Ohm 159 * All other values are reserved. 160 * It is recommended to set this to 0x00. 161 */ 162 uint8_t phyodtimpedance; /* 163 * Byte offset 0x0a, CSR Addr 0x54005, Direction=In 164 * Must be programmed to the termination impedance in ohms 165 * used by PHY during reads. 166 * 167 * 0x0 = Firmware skips programming (must be manually 168 * programmed by user prior to training start) 169 * 170 * See PHY databook for legal termination impedance values. 171 * 172 * For digital simulation, any legal value can be used. For 173 * silicon, the users must determine the correct value 174 * through SI simulation or other methods. 175 */ 176 uint8_t phydrvimpedance; /* 177 * Byte offset 0x0b, CSR Addr 0x54005, Direction=In 178 * Must be programmed to the driver impedance in ohms used 179 * by PHY during writes for all DBYTE drivers 180 * (DQ/DM/DBI/DQS). 181 * 182 * 0x0 = Firmware skips programming (must be manually 183 * programmed by user prior to training start) 184 * 185 * See PHY databook for legal R_on driver impedance values. 186 * 187 * For digital simulation, any value can be used that is not 188 * Hi-Z. For silicon, the users must determine the correct 189 * value through SI simulation or other methods. 190 */ 191 uint8_t phyvref; /* 192 * Byte offset 0x0c, CSR Addr 0x54006, Direction=In 193 * Must be programmed with the Vref level to be used by the 194 * PHY during reads 195 * 196 * The units of this field are a percentage of VDDQ 197 * according to the following equation: 198 * 199 * Receiver Vref = VDDQ*phyvref[6:0]/128 200 * 201 * For example to set Vref at 0.75*VDDQ, set this field to 202 * 0x60. 203 * 204 * For digital simulation, any legal value can be used. For 205 * silicon, the users must calculate the analytical Vref by 206 * using the impedances, terminations, and series resistance 207 * present in the system. 208 */ 209 uint8_t dramtype; /* 210 * Byte offset 0x0d, CSR Addr 0x54006, Direction=In 211 * Module Type: 212 * 0x01 = Reserved 213 * 0x02 = DDR4 unbuffered 214 * 0x03 = Reserved 215 * 0x04 = Reserved 216 * 0x05 = Reserved 217 */ 218 uint8_t disableddbyte; /* 219 * Byte offset 0x0e, CSR Addr 0x54007, Direction=In 220 * Bitmap to indicate which Dbyte are not connected (for 221 * DByte 0 to 7): 222 * Set disableddbyte[i] to 1 only to specify that DByte is 223 * not need to be trained (DByte 8 can be disabled via 224 * enableddqs setting) 225 */ 226 uint8_t enableddqs; /* 227 * Byte offset 0x0f, CSR Addr 0x54007, Direction=In 228 * Total number of DQ bits enabled in PHY 229 */ 230 uint8_t cspresent; /* 231 * Byte offset 0x10, CSR Addr 0x54008, Direction=In 232 * Indicates presence of DRAM at each chip select for PHY. 233 * Each bit corresponds to a logical CS. 234 * 235 * If the bit is set to 1, the CS is connected to DRAM. 236 * If the bit is set to 0, the CS is not connected to DRAM. 237 * 238 * cspresent[0] = CS0 is populated with DRAM 239 * cspresent[1] = CS1 is populated with DRAM 240 * cspresent[2] = CS2 is populated with DRAM 241 * cspresent[3] = CS3 is populated with DRAM 242 * cspresent[7:4] = Reserved (must be programmed to 0) 243 */ 244 uint8_t cspresentd0; /* 245 * Byte offset 0x11, CSR Addr 0x54008, Direction=In 246 * The CS signals from field cspresent that are routed to 247 * DIMM connector 0 248 */ 249 uint8_t cspresentd1; /* 250 * Byte offset 0x12, CSR Addr 0x54009, Direction=In 251 * The CS signals from field cspresent that are routed to 252 * DIMM connector 1 253 */ 254 uint8_t addrmirror; /* 255 * Byte offset 0x13, CSR Addr 0x54009, Direction=In 256 * Corresponds to CS[3:0] 257 * 1 = Address Mirror. 258 * 0 = No Address Mirror. 259 */ 260 uint8_t cstestfail; /* 261 * Byte offset 0x14, CSR Addr 0x5400a, Direction=Out 262 * This field will be set if training fails on any rank. 263 * 0x0 = No failures 264 * non-zero = one or more ranks failed training 265 */ 266 uint8_t phycfg; /* 267 * Byte offset 0x15, CSR Addr 0x5400a, Direction=In 268 * Additional mode bits. 269 * 270 * Bit fields: 271 * [0] SlowAccessMode: 272 * 1 = 2T Address Timing. 273 * 0 = 1T Address Timing. 274 * [7-1] RFU, must be zero 275 * 276 * WARNING: In case of DDR4 Geardown Mode (mr3[A3] == 1), 277 * phycfg[0] must be 0. 278 */ 279 uint16_t sequencectrl; /* 280 * Byte offset 0x16, CSR Addr 0x5400b, Direction=In 281 * Controls the training steps to be run. Each bit 282 * corresponds to a training step. 283 * 284 * If the bit is set to 1, the training step will run. 285 * If the bit is set to 0, the training step will be 286 * skipped. 287 * 288 * Training step to bit mapping: 289 * sequencectrl[0] = Run DevInit - Device/phy 290 * initialization. Should always be set. 291 * sequencectrl[1] = Run WrLvl - Write leveling 292 * sequencectrl[2] = Run RxEn - Read gate training 293 * sequencectrl[3] = Run RdDQS1D - 1d read dqs training 294 * sequencectrl[4] = Run WrDQ1D - 1d write dq training 295 * sequencectrl[5] = RFU, must be zero 296 * sequencectrl[6] = RFU, must be zero 297 * sequencectrl[7] = RFU, must be zero 298 * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew 299 * training 300 * sequencectrl[9] = Run MxRdLat - Max read latency training 301 * sequencectrl[10] = Run Reserved 302 * sequencectrl[11] = Run Reserved 303 * sequencectrl[12] = Run Reserved 304 * sequencectrl[13] = Run Reserved 305 * sequencectrl[15-14] = RFU, must be zero 306 */ 307 uint8_t hdtctrl; /* 308 * Byte offset 0x18, CSR Addr 0x5400c, Direction=In 309 * To control the total number of debug messages, a 310 * verbosity subfield (hdtctrl, Hardware Debug Trace 311 * Control) exists in the message block. Every message has a 312 * verbosity level associated with it, and as the hdtctrl 313 * value is increased, less important s messages stop being 314 * sent through the mailboxes. The meanings of several major 315 * hdtctrl thresholds are explained below: 316 * 317 * 0x04 = Maximal debug messages (e.g., Eye contours) 318 * 0x05 = Detailed debug messages (e.g. Eye delays) 319 * 0x0A = Coarse debug messages (e.g. rank information) 320 * 0xC8 = Stage completion 321 * 0xC9 = Assertion messages 322 * 0xFF = Firmware completion messages only 323 */ 324 uint8_t reserved19; /* Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A */ 325 uint8_t reserved1a; /* Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A */ 326 uint8_t share2dvrefresult; /* 327 * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In 328 * Bitmap that designates the phy's vref source for every 329 * pstate 330 * If share2dvrefresult[x] = 0, then after 2D training, 331 * pstate x will continue using the phyVref provided in 332 * pstate x's 1D messageblock. 333 * If share2dvrefresult[x] = 1, then after 2D training, 334 * pstate x will use the per-lane VrefDAC0/1 CSRs trained by 335 * 2d training. 336 */ 337 uint8_t reserved1c; /* Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A */ 338 uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */ 339 uint8_t reserved1e; /* 340 * Byte offset 0x1e, CSR Addr 0x5400f, Direction=In 341 * Input for constraining the range of vref(DQ) values 342 * training will collect data for, usually reducing training 343 * time. However, too large of a voltage range may cause 344 * longer 2D training times while too small of a voltage 345 * range may truncate passing regions. When in doubt, leave 346 * this field set to 0. 347 * Used by 2D training in: Rd2D, Wr2D 348 * 349 * reserved1E[0-3]: Rd2D Voltage Range 350 * 0 = Training will search all phy vref(DQ) settings 351 * 1 = limit to +/-2 %VDDQ from phyVref 352 * 2 = limit to +/-4 %VDDQ from phyVref 353 * . . . 354 * 15 = limit to +/-30% VDDQ from phyVref 355 * 356 * reserved1E[4-7]: Wr2D Voltage Range 357 * 0 = Training will search all dram vref(DQ) settings 358 * 1 = limit to +/-2 %VDDQ from mr6 359 * 2 = limit to +/-4 %VDDQ from mr6 360 * . . . 361 * 15 = limit to +/-30% VDDQ from mr6 362 */ 363 uint8_t reserved1f; /* 364 * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In 365 * Extended training option: 366 * 367 * reserved1F[1:0]: Configured RxClkDly offset try during 368 * WrDq1D high-effort (i.e., when reserved00[6] is set) 369 * 0: -8, +8, -16, +16 370 * 1: -4, +4, -8, +8, -12, +12, -16, +16 371 * 2: -2, +2, -4, +4, -6, +6, -8, +8 372 * 3: -2, +2, -4, +4, -6, +6, -8, +8, -10, +10, -12, +12, 373 * -14, +14, -16, +16 374 * 375 * reserved1F[2]: When set, execute again WrDq1D after 376 * RdDqs1D PRBS 377 * reserved1F[3]: When set redo RdDeskew with PRBS after 378 * (first) WrDqs1D 379 * reserved1F[7:4]: This field is reserved and must be 380 * programmed to 0x00. 381 */ 382 uint8_t reserved20; /* 383 * Byte offset 0x20, CSR Addr 0x54010, Direction=In 384 * This field is reserved and must be programmed to 0x00, 385 * excepted for Reserved: 386 * Reserved MREP assume raising edge is found when 387 * reserved20[3:0]+3 consecutive 1 are received during MREP 388 * fine delay swept; reserved20[6:0] thus permits to 389 * increase tolerance for noisy system. And if reserved20[7] 390 * is set, MREP training is failing if no raising edge is 391 * found (otherwise the raising edge is assume close to 392 * delay 0). 393 */ 394 uint8_t reserved21; /* 395 * Byte offset 0x21, CSR Addr 0x54010, Direction=In 396 * This field is reserved and must be programmed to 0x00, 397 * excepted for Reserved: 398 * Reserved DWL assume raising edge is found when 399 * reserved21[3:0]+3 consecutive 1 are received during DWL 400 * fine delay swept; reserved21[6:0] thus permits to 401 * increase tolerance for noisy system. And if reserved21[7] 402 * is set, DWL training is failing if no raising edge is 403 * found (otherwise the raising edge is assume close to 404 * delay 0). 405 */ 406 uint16_t phyconfigoverride; /* 407 * Byte offset 0x22, CSR Addr 0x54011, Direction=In 408 * Override PhyConfig csr. 409 * 0x0: Use hardware csr value for PhyConfing 410 * (recommended) 411 * Other values: Use value for PhyConfig instead of 412 * Hardware value. 413 */ 414 uint8_t dfimrlmargin; /* 415 * Byte offset 0x24, CSR Addr 0x54012, Direction=In 416 * Margin added to smallest passing trained DFI Max Read 417 * Latency value, in units of DFI clocks. Recommended to be 418 * >= 1. 419 */ 420 int8_t cdd_rr_3_2; /* 421 * Byte offset 0x25, CSR Addr 0x54012, Direction=Out 422 * This is a signed integer value. 423 * Read to read critical delay difference from cs 3 to cs 2. 424 */ 425 int8_t cdd_rr_3_1; /* 426 * Byte offset 0x26, CSR Addr 0x54013, Direction=Out 427 * This is a signed integer value. 428 * Read to read critical delay difference from cs 3 to cs 1. 429 */ 430 int8_t cdd_rr_3_0; /* 431 * Byte offset 0x27, CSR Addr 0x54013, Direction=Out 432 * This is a signed integer value. 433 * Read to read critical delay difference from cs 3 to cs 0. 434 */ 435 int8_t cdd_rr_2_3; /* 436 * Byte offset 0x28, CSR Addr 0x54014, Direction=Out 437 * This is a signed integer value. 438 * Read to read critical delay difference from cs 2 to cs 3. 439 */ 440 int8_t cdd_rr_2_1; /* 441 * Byte offset 0x29, CSR Addr 0x54014, Direction=Out 442 * This is a signed integer value. 443 * Read to read critical delay difference from cs 2 to cs 1. 444 */ 445 int8_t cdd_rr_2_0; /* 446 * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out 447 * This is a signed integer value. 448 * Read to read critical delay difference from cs 2 to cs 0. 449 */ 450 int8_t cdd_rr_1_3; /* 451 * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out 452 * This is a signed integer value. 453 * Read to read critical delay difference from cs 1 to cs 3. 454 */ 455 int8_t cdd_rr_1_2; /* 456 * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out 457 * This is a signed integer value. 458 * Read to read critical delay difference from cs 1 to cs 2. 459 */ 460 int8_t cdd_rr_1_0; /* 461 * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out 462 * This is a signed integer value. 463 * Read to read critical delay difference from cs 1 to cs 0. 464 */ 465 int8_t cdd_rr_0_3; /* 466 * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out 467 * This is a signed integer value. 468 * Read to read critical delay difference from cs 0 to cs 3. 469 */ 470 int8_t cdd_rr_0_2; /* 471 * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out 472 * This is a signed integer value. 473 * Read to read critical delay difference from cs 0 to cs 2. 474 */ 475 int8_t cdd_rr_0_1; /* 476 * Byte offset 0x30, CSR Addr 0x54018, Direction=Out 477 * This is a signed integer value. 478 * Read to read critical delay difference from cs 0 to cs 1. 479 */ 480 int8_t cdd_ww_3_2; /* 481 * Byte offset 0x31, CSR Addr 0x54018, Direction=Out 482 * This is a signed integer value. 483 * Write to write critical delay difference from cs 3 to cs 484 * 2. 485 */ 486 int8_t cdd_ww_3_1; /* 487 * Byte offset 0x32, CSR Addr 0x54019, Direction=Out 488 * This is a signed integer value. 489 * Write to write critical delay difference from cs 3 to cs 490 * 1. 491 */ 492 int8_t cdd_ww_3_0; /* 493 * Byte offset 0x33, CSR Addr 0x54019, Direction=Out 494 * This is a signed integer value. 495 * Write to write critical delay difference from cs 3 to cs 496 * 0. 497 */ 498 int8_t cdd_ww_2_3; /* 499 * Byte offset 0x34, CSR Addr 0x5401a, Direction=Out 500 * This is a signed integer value. 501 * Write to write critical delay difference from cs 2 to cs 502 * 3. 503 */ 504 int8_t cdd_ww_2_1; /* 505 * Byte offset 0x35, CSR Addr 0x5401a, Direction=Out 506 * This is a signed integer value. 507 * Write to write critical delay difference from cs 2 to cs 508 * 1. 509 */ 510 int8_t cdd_ww_2_0; /* 511 * Byte offset 0x36, CSR Addr 0x5401b, Direction=Out 512 * This is a signed integer value. 513 * Write to write critical delay difference from cs 2 to cs 514 * 0. 515 */ 516 int8_t cdd_ww_1_3; /* 517 * Byte offset 0x37, CSR Addr 0x5401b, Direction=Out 518 * This is a signed integer value. 519 * Write to write critical delay difference from cs 1 to cs 520 * 3. 521 */ 522 int8_t cdd_ww_1_2; /* 523 * Byte offset 0x38, CSR Addr 0x5401c, Direction=Out 524 * This is a signed integer value. 525 * Write to write critical delay difference from cs 1 to cs 526 * 2. 527 */ 528 int8_t cdd_ww_1_0; /* 529 * Byte offset 0x39, CSR Addr 0x5401c, Direction=Out 530 * This is a signed integer value. 531 * Write to write critical delay difference from cs 1 to cs 532 * 0. 533 */ 534 int8_t cdd_ww_0_3; /* 535 * Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out 536 * This is a signed integer value. 537 * Write to write critical delay difference from cs 0 to cs 538 * 3. 539 */ 540 int8_t cdd_ww_0_2; /* 541 * Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out 542 * This is a signed integer value. 543 * Write to write critical delay difference from cs 0 to cs 544 * 2. 545 */ 546 int8_t cdd_ww_0_1; /* 547 * Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out 548 * This is a signed integer value. 549 * Write to write critical delay difference from cs 0 to cs 550 * 1. 551 */ 552 int8_t cdd_rw_3_3; /* 553 * Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out 554 * This is a signed integer value. 555 * Read to write critical delay difference from cs 3 to 556 * cs 3. 557 */ 558 int8_t cdd_rw_3_2; /* 559 * Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out 560 * This is a signed integer value. 561 * Read to write critical delay difference from cs 3 to 562 * cs 2. 563 */ 564 int8_t cdd_rw_3_1; /* 565 * Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out 566 * This is a signed integer value. 567 * Read to write critical delay difference from cs 3 to 568 * cs 1. 569 */ 570 int8_t cdd_rw_3_0; /* 571 * Byte offset 0x40, CSR Addr 0x54020, Direction=Out 572 * This is a signed integer value. 573 * Read to write critical delay difference from cs 3 to 574 * cs 0. 575 */ 576 int8_t cdd_rw_2_3; /* 577 * Byte offset 0x41, CSR Addr 0x54020, Direction=Out 578 * This is a signed integer value. 579 * Read to write critical delay difference from cs 2 to 580 * cs 3. 581 */ 582 int8_t cdd_rw_2_2; /* 583 * Byte offset 0x42, CSR Addr 0x54021, Direction=Out 584 * This is a signed integer value. 585 * Read to write critical delay difference from cs 2 to 586 * cs 2. 587 */ 588 int8_t cdd_rw_2_1; /* 589 * Byte offset 0x43, CSR Addr 0x54021, Direction=Out 590 * This is a signed integer value. 591 * Read to write critical delay difference from cs 2 to 592 * cs 1. 593 */ 594 int8_t cdd_rw_2_0; /* 595 * Byte offset 0x44, CSR Addr 0x54022, Direction=Out 596 * This is a signed integer value. 597 * Read to write critical delay difference from cs 2 to 598 * cs 0. 599 */ 600 int8_t cdd_rw_1_3; /* 601 * Byte offset 0x45, CSR Addr 0x54022, Direction=Out 602 * This is a signed integer value. 603 * Read to write critical delay difference from cs 1 to 604 * cs 3. 605 */ 606 int8_t cdd_rw_1_2; /* 607 * Byte offset 0x46, CSR Addr 0x54023, Direction=Out 608 * This is a signed integer value. 609 * Read to write critical delay difference from cs 1 to 610 * cs 2. 611 */ 612 int8_t cdd_rw_1_1; /* 613 * Byte offset 0x47, CSR Addr 0x54023, Direction=Out 614 * This is a signed integer value. 615 * Read to write critical delay difference from cs 1 to 616 * cs 1. 617 */ 618 int8_t cdd_rw_1_0; /* 619 * Byte offset 0x48, CSR Addr 0x54024, Direction=Out 620 * This is a signed integer value. 621 * Read to write critical delay difference from cs 1 to 622 * cs 0. 623 */ 624 int8_t cdd_rw_0_3; /* 625 * Byte offset 0x49, CSR Addr 0x54024, Direction=Out 626 * This is a signed integer value. 627 * Read to write critical delay difference from cs 0 to 628 * cs 3. 629 */ 630 int8_t cdd_rw_0_2; /* 631 * Byte offset 0x4a, CSR Addr 0x54025, Direction=Out 632 * This is a signed integer value. 633 * Read to write critical delay difference from cs 0 to 634 * cs 2. 635 */ 636 int8_t cdd_rw_0_1; /* 637 * Byte offset 0x4b, CSR Addr 0x54025, Direction=Out 638 * This is a signed integer value. 639 * Read to write critical delay difference from cs 0 to 640 * cs 1. 641 */ 642 int8_t cdd_rw_0_0; /* 643 * Byte offset 0x4c, CSR Addr 0x54026, Direction=Out 644 * This is a signed integer value. 645 * Read to write critical delay difference from cs 0 to 646 * cs 0. 647 */ 648 int8_t cdd_wr_3_3; /* 649 * Byte offset 0x4d, CSR Addr 0x54026, Direction=Out 650 * This is a signed integer value. 651 * Write to read critical delay difference from cs 3 to 652 * cs 3. 653 */ 654 int8_t cdd_wr_3_2; /* 655 * Byte offset 0x4e, CSR Addr 0x54027, Direction=Out 656 * This is a signed integer value. 657 * Write to read critical delay difference from cs 3 to 658 * cs 2. 659 */ 660 int8_t cdd_wr_3_1; /* 661 * Byte offset 0x4f, CSR Addr 0x54027, Direction=Out 662 * This is a signed integer value. 663 * Write to read critical delay difference from cs 3 to 664 * cs 1. 665 */ 666 int8_t cdd_wr_3_0; /* 667 * Byte offset 0x50, CSR Addr 0x54028, Direction=Out 668 * This is a signed integer value. 669 * Write to read critical delay difference from cs 3 to 670 * cs 0. 671 */ 672 int8_t cdd_wr_2_3; /* 673 * Byte offset 0x51, CSR Addr 0x54028, Direction=Out 674 * This is a signed integer value. 675 * Write to read critical delay difference from cs 2 to 676 * cs 3. 677 */ 678 int8_t cdd_wr_2_2; /* 679 * Byte offset 0x52, CSR Addr 0x54029, Direction=Out 680 * This is a signed integer value. 681 * Write to read critical delay difference from cs 2 to 682 * cs 2. 683 */ 684 int8_t cdd_wr_2_1; /* 685 * Byte offset 0x53, CSR Addr 0x54029, Direction=Out 686 * This is a signed integer value. 687 * Write to read critical delay difference from cs 2 to 688 * cs 1. 689 */ 690 int8_t cdd_wr_2_0; /* 691 * Byte offset 0x54, CSR Addr 0x5402a, Direction=Out 692 * This is a signed integer value. 693 * Write to read critical delay difference from cs 2 to 694 * cs 0. 695 */ 696 int8_t cdd_wr_1_3; /* 697 * Byte offset 0x55, CSR Addr 0x5402a, Direction=Out 698 * This is a signed integer value. 699 * Write to read critical delay difference from cs 1 to 700 * cs 3. 701 */ 702 int8_t cdd_wr_1_2; /* 703 * Byte offset 0x56, CSR Addr 0x5402b, Direction=Out 704 * This is a signed integer value. 705 * Write to read critical delay difference from cs 1 to 706 * cs 2. 707 */ 708 int8_t cdd_wr_1_1; /* 709 * Byte offset 0x57, CSR Addr 0x5402b, Direction=Out 710 * This is a signed integer value. 711 * Write to read critical delay difference from cs 1 to 712 * cs 1. 713 */ 714 int8_t cdd_wr_1_0; /* 715 * Byte offset 0x58, CSR Addr 0x5402c, Direction=Out 716 * This is a signed integer value. 717 * Write to read critical delay difference from cs 1 to 718 * cs 0. 719 */ 720 int8_t cdd_wr_0_3; /* 721 * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out 722 * This is a signed integer value. 723 * Write to read critical delay difference from cs 0 to 724 * cs 3. 725 */ 726 int8_t cdd_wr_0_2; /* 727 * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out 728 * This is a signed integer value. 729 * Write to read critical delay difference from cs 0 to 730 * cs 2. 731 */ 732 int8_t cdd_wr_0_1; /* 733 * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out 734 * This is a signed integer value. 735 * Write to read critical delay difference from cs 0 to 736 * cs 1. 737 */ 738 int8_t cdd_wr_0_0; /* 739 * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out 740 * This is a signed integer value. 741 * Write to read critical delay difference from cs 0 to 742 * cs 0. 743 */ 744 uint8_t reserved5d; /* 745 * Byte offset 0x5d, CSR Addr 0x5402e, Direction=In 746 * This field is reserved and must be programmed to 0x00, 747 * excepted for DDR4: 748 * By default, if this parameter is 0, the offset applied at 749 * the end of DDR4 RxEn training resulting in the trained 750 * RxEnDly is 3/8 of the RX preamble width; if reserved5D is 751 * non zero, this offset is used instead (in fine step). 752 */ 753 uint16_t mr0; /* 754 * Byte offset 0x5e, CSR Addr 0x5402f, Direction=In 755 * Value of DDR mode register mr0 for all ranks for current 756 * pstate. 757 */ 758 uint16_t mr1; /* 759 * Byte offset 0x60, CSR Addr 0x54030, Direction=In 760 * Value of DDR mode register mr1 for all ranks for current 761 * pstate. 762 */ 763 uint16_t mr2; /* 764 * Byte offset 0x62, CSR Addr 0x54031, Direction=In 765 * Value of DDR mode register mr2 for all ranks for current 766 * pstate. 767 */ 768 uint16_t mr3; /* 769 * Byte offset 0x64, CSR Addr 0x54032, Direction=In 770 * Value of DDR mode register mr3 for all ranks for current 771 * pstate. 772 */ 773 uint16_t mr4; /* 774 * Byte offset 0x66, CSR Addr 0x54033, Direction=In 775 * Value of DDR mode register mr4 for all ranks for current 776 * pstate. 777 */ 778 uint16_t mr5; /* 779 * Byte offset 0x68, CSR Addr 0x54034, Direction=In 780 * Value of DDR mode register mr5 for all ranks for current 781 * pstate. 782 */ 783 uint16_t mr6; /* 784 * Byte offset 0x6a, CSR Addr 0x54035, Direction=In 785 * Value of DDR mode register mr6 for all ranks for current 786 * pstate. Note: The initial VrefDq value and range must be 787 * set in A6:A0. 788 */ 789 uint8_t x16present; /* 790 * Byte offset 0x6c, CSR Addr 0x54036, Direction=In 791 * X16 device map. Corresponds to CS[3:0]. 792 * x16present[0] = CS0 is populated with X16 devices 793 * x16present[1] = CS1 is populated with X16 devices 794 * x16present[2] = CS2 is populated with X16 devices 795 * x16present[3] = CS3 is populated with X16 devices 796 * x16present[7:4] = Reserved (must be programmed to 0) 797 * 798 * Ranks may not contain mixed device types. 799 */ 800 uint8_t cssetupgddec; /* 801 * Byte offset 0x6d, CSR Addr 0x54036, Direction=In 802 * controls timing of chip select signals when DDR4 803 * gear-down mode is active 804 * 0 - Leave delay of chip select timing group signal 805 * the same both before and after gear-down sync occurs 806 * 1 - Add 1UI of delay to chip select timing group 807 * signals when geardown-mode is active. This allows CS 808 * signals to have equal setup and hold time in gear-down 809 * mode 810 */ 811 uint16_t rtt_nom_wr_park0; /* 812 * Byte offset 0x6e, CSR Addr 0x54037, Direction=In 813 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 814 * DRAM: 815 * rtt_nom_wr_park0[0] = 1: Option is enable (otherwise, 816 * remaining bit fields are don't care) 817 * rtt_nom_wr_park0[5:3]: Optional RTT_NOM value to be used 818 * in mr1[10:8] for rank 0 819 * rtt_nom_wr_park0[11:9]: Optional RTT_WR value to be used 820 * in mr2[11:9] for rank 0 821 * rtt_nom_wr_park0[8:6]: Optional RTT_PARK value to be used 822 * in mr5[8:6] for rank 0 823 */ 824 uint16_t rtt_nom_wr_park1; /* 825 * Byte offset 0x70, CSR Addr 0x54038, Direction=In 826 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 827 * DRAM: 828 * rtt_nom_wr_park1[0] = 1: Option is enable (otherwise, 829 * remaining bit fields are don't care) 830 * rtt_nom_wr_park1[5:3]: Optional RTT_NOM value to be used 831 * in mr1[10:8] for rank 1 832 * rtt_nom_wr_park1[11:9]: Optional RTT_WR value to be used 833 * in mr2[11:9] for rank 1 834 * rtt_nom_wr_park1[8:6]: Optional RTT_PARK value to be used 835 * in mr5[8:6] for rank 1 836 */ 837 uint16_t rtt_nom_wr_park2; /* 838 * Byte offset 0x72, CSR Addr 0x54039, Direction=In 839 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 840 * DRAM: 841 * rtt_nom_wr_park2[0] = 1: Option is enable (otherwise, 842 * remaining bit fields are don't care) 843 * rtt_nom_wr_park2[5:3]: Optional RTT_NOM value to be used 844 * in mr1[10:8] for rank 2 845 * rtt_nom_wr_park2[11:9]: Optional RTT_WR value to be used 846 * in mr2[11:9] for rank 2 847 * rtt_nom_wr_park2[8:6]: Optional RTT_PARK value to be used 848 * in mr5[8:6] for rank 2 849 */ 850 uint16_t rtt_nom_wr_park3; /* 851 * Byte offset 0x74, CSR Addr 0x5403a, Direction=In 852 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 853 * DRAM: 854 * rtt_nom_wr_park3[0] = 1: Option is enable (otherwise, 855 * remaining bit fields are don't care) 856 * rtt_nom_wr_park3[5:3]: Optional RTT_NOM value to be used 857 * in mr1[10:8] for rank 3 858 * rtt_nom_wr_park3[11:9]: Optional RTT_WR value to be used 859 * in mr2[11:9] for rank 3 860 * rtt_nom_wr_park3[8:6]: Optional RTT_PARK value to be used 861 * in mr5[8:6] for rank 3 862 */ 863 uint16_t rtt_nom_wr_park4; /* 864 * Byte offset 0x76, CSR Addr 0x5403b, Direction=In 865 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 866 * DRAM: 867 * rtt_nom_wr_park4[0] = 1: Option is enable (otherwise, 868 * remaining bit fields are don't care) 869 * rtt_nom_wr_park4[5:3]: Optional RTT_NOM value to be used 870 * in mr1[10:8] for rank 4 871 * rtt_nom_wr_park4[11:9]: Optional RTT_WR value to be used 872 * in mr2[11:9] for rank 4 873 * rtt_nom_wr_park4[8:6]: Optional RTT_PARK value to be used 874 * in mr5[8:6] for rank 4 875 */ 876 uint16_t rtt_nom_wr_park5; /* 877 * Byte offset 0x78, CSR Addr 0x5403c, Direction=In 878 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 879 * DRAM: 880 * rtt_nom_wr_park5[0] = 1: Option is enable (otherwise, 881 * remaining bit fields are don't care) 882 * rtt_nom_wr_park5[5:3]: Optional RTT_NOM value to be used 883 * in mr1[10:8] for rank 5 884 * rtt_nom_wr_park5[11:9]: Optional RTT_WR value to be used 885 * in mr2[11:9] for rank 5 886 * rtt_nom_wr_park5[8:6]: Optional RTT_PARK value to be used 887 * in mr5[8:6] for rank 5 888 */ 889 uint16_t rtt_nom_wr_park6; /* 890 * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In 891 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 892 * DRAM: 893 * rtt_nom_wr_park6[0] = 1: Option is enable (otherwise, 894 * remaining bit fields are don't care) 895 * rtt_nom_wr_park6[5:3]: Optional RTT_NOM value to be used 896 * in mr1[10:8] for rank 6 897 * rtt_nom_wr_park6[11:9]: Optional RTT_WR value to be used 898 * in mr2[11:9] for rank 6 899 * rtt_nom_wr_park6[8:6]: Optional RTT_PARK value to be used 900 * in mr5[8:6] for rank 6 901 */ 902 uint16_t rtt_nom_wr_park7; /* 903 * Byte offset 0x7c, CSR Addr 0x5403e, Direction=In 904 * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 905 * DRAM: 906 * rtt_nom_wr_park7[0] = 1: Option is enable (otherwise, 907 * remaining bit fields are don't care) 908 * rtt_nom_wr_park7[5:3]: Optional RTT_NOM value to be used 909 * in mr1[10:8] for rank 7 910 * rtt_nom_wr_park7[11:9]: Optional RTT_WR value to be used 911 * in mr2[11:9] for rank 7 912 * rtt_nom_wr_park7[8:6]: Optional RTT_PARK value to be used 913 * in mr5[8:6] for rank 7 914 */ 915 uint8_t acsmodtctrl0; /* 916 * Byte offset 0x7e, CSR Addr 0x5403f, Direction=In 917 * Odt pattern for accesses targeting rank 0. [3:0] is used 918 * for write ODT [7:4] is used for read ODT 919 */ 920 uint8_t acsmodtctrl1; /* 921 * Byte offset 0x7f, CSR Addr 0x5403f, Direction=In 922 * Odt pattern for accesses targeting rank 1. [3:0] is used 923 * for write ODT [7:4] is used for read ODT 924 */ 925 uint8_t acsmodtctrl2; /* 926 * Byte offset 0x80, CSR Addr 0x54040, Direction=In 927 * Odt pattern for accesses targeting rank 2. [3:0] is used 928 * for write ODT [7:4] is used for read ODT 929 */ 930 uint8_t acsmodtctrl3; /* 931 * Byte offset 0x81, CSR Addr 0x54040, Direction=In 932 * Odt pattern for accesses targeting rank 3. [3:0] is used 933 * for write ODT [7:4] is used for read ODT 934 */ 935 uint8_t acsmodtctrl4; /* 936 * Byte offset 0x82, CSR Addr 0x54041, Direction=In 937 * Odt pattern for accesses targeting rank 4. [3:0] is used 938 * for write ODT [7:4] is used for read ODT 939 */ 940 uint8_t acsmodtctrl5; /* 941 * Byte offset 0x83, CSR Addr 0x54041, Direction=In 942 * Odt pattern for accesses targeting rank 5. [3:0] is used 943 * for write ODT [7:4] is used for read ODT 944 */ 945 uint8_t acsmodtctrl6; /* 946 * Byte offset 0x84, CSR Addr 0x54042, Direction=In 947 * Odt pattern for accesses targeting rank 6. [3:0] is used 948 * for write ODT [7:4] is used for read ODT 949 */ 950 uint8_t acsmodtctrl7; /* 951 * Byte offset 0x85, CSR Addr 0x54042, Direction=In 952 * Odt pattern for accesses targeting rank 7. [3:0] is used 953 * for write ODT [7:4] is used for read ODT 954 */ 955 uint8_t vrefdqr0nib0; /* 956 * Byte offset 0x86, CSR Addr 0x54043, Direction=InOut 957 * VrefDq for rank 0 nibble 0. Specifies mr6[6:0] 958 */ 959 uint8_t vrefdqr0nib1; /* 960 * Byte offset 0x87, CSR Addr 0x54043, Direction=InOut 961 * VrefDq for rank 0 nibble 1. Specifies mr6[6:0]. 962 * Identical to vrefdqr0nib0 for x8 or x16 devices. 963 */ 964 uint8_t vrefdqr0nib2; /* 965 * Byte offset 0x88, CSR Addr 0x54044, Direction=InOut 966 * VrefDq for rank 0 nibble 2. Specifies mr6[6:0]. 967 * Identical to vrefdqr0nib0 for x16 devices. 968 */ 969 uint8_t vrefdqr0nib3; /* 970 * Byte offset 0x89, CSR Addr 0x54044, Direction=InOut 971 * VrefDq for rank 0 nibble 3. Specifies mr6[6:0]. 972 * Identical to vrefdqr0nib0 for x16 devices, or 973 * vrefdqr0nib2 for x8 devices. 974 */ 975 uint8_t vrefdqr0nib4; /* 976 * Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut 977 * VrefDq for rank 0 nibble 4. Specifies mr6[6:0] 978 */ 979 uint8_t vrefdqr0nib5; /* 980 * Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut 981 * VrefDq for rank 0 nibble 5. Specifies mr6[6:0]. 982 * Identical to vrefdqr0nib4 for x8 or x16 devices. 983 */ 984 uint8_t vrefdqr0nib6; /* 985 * Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut 986 * VrefDq for rank 0 nibble 6. Specifies mr6[6:0]. 987 * Identical to vrefdqr0nib4 for x16 devices. 988 */ 989 uint8_t vrefdqr0nib7; /* 990 * Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut 991 * VrefDq for rank 0 nibble 7. Specifies mr6[6:0]. 992 * Identical to vrefdqr0nib4 for x16 devices, 993 * or vrefdqr0nib6 for x8 devices. 994 */ 995 uint8_t vrefdqr0nib8; /* 996 * Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut 997 * VrefDq for rank 0 nibble 8. Specifies mr6[6:0] 998 */ 999 uint8_t vrefdqr0nib9; /* 1000 * Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut 1001 * VrefDq for rank 0 nibble 9. Specifies mr6[6:0]. 1002 * Identical to vrefdqr0nib8 for x8 or x16 devices. 1003 */ 1004 uint8_t vrefdqr0nib10; /* 1005 * Byte offset 0x90, CSR Addr 0x54048, Direction=InOut 1006 * VrefDq for rank 0 nibble 10. Specifies mr6[6:0]. 1007 * Identical to vrefdqr0nib8 for x16 devices. 1008 */ 1009 uint8_t vrefdqr0nib11; /* 1010 * Byte offset 0x91, CSR Addr 0x54048, Direction=InOut 1011 * VrefDq for rank 0 nibble 11. Specifies mr6[6:0]. 1012 * Identical to vrefdqr0nib8 for x16 devices, 1013 * or vrefdqr0nib10 for x8 devices. 1014 */ 1015 uint8_t vrefdqr0nib12; /* 1016 * Byte offset 0x92, CSR Addr 0x54049, Direction=InOut 1017 * VrefDq for rank 0 nibble 12. Specifies mr6[6:0] 1018 */ 1019 uint8_t vrefdqr0nib13; /* 1020 * Byte offset 0x93, CSR Addr 0x54049, Direction=InOut 1021 * VrefDq for rank 0 nibble 13. Specifies mr6[6:0]. 1022 * Identical to vrefdqr0nib12 for x8 or x16 devices. 1023 */ 1024 uint8_t vrefdqr0nib14; /* 1025 * Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut 1026 * VrefDq for rank 0 nibble 14. Specifies mr6[6:0]. 1027 * Identical to vrefdqr0nib12 for x16 devices. 1028 */ 1029 uint8_t vrefdqr0nib15; /* 1030 * Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut 1031 * VrefDq for rank 0 nibble 15. Specifies mr6[6:0]. 1032 * Identical to vrefdqr0nib12 for x16 devices, 1033 * or vrefdqr0nib14 for x8 devices. 1034 */ 1035 uint8_t vrefdqr0nib16; /* 1036 * Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut 1037 * VrefDq for rank 0 nibble 16. Specifies mr6[6:0] 1038 */ 1039 uint8_t vrefdqr0nib17; /* 1040 * Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut 1041 * VrefDq for rank 0 nibble 17. Specifies mr6[6:0]. 1042 * Identical to vrefdqr0nib16 for x8 or x16 devices. 1043 */ 1044 uint8_t vrefdqr0nib18; /* 1045 * Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut 1046 * VrefDq for rank 0 nibble 18. Specifies mr6[6:0]. 1047 * Identical to vrefdqr0nib16 for x16 devices. 1048 */ 1049 uint8_t vrefdqr0nib19; /* 1050 * Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut 1051 * VrefDq for rank 0 nibble 19. Specifies mr6[6:0]. 1052 * Identical to vrefdqr0nib16 for x16 devices, 1053 * or vrefdqr0nib18 for x8 devices. 1054 */ 1055 uint8_t vrefdqr1nib0; /* 1056 * Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut 1057 * VrefDq for rank 1 nibble 0. Specifies mr6[6:0] 1058 */ 1059 uint8_t vrefdqr1nib1; /* 1060 * Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut 1061 * VrefDq for rank 1 nibble 1. Specifies mr6[6:0]. 1062 * Identical to vrefdqr1nib0 for x8 or x16 devices. 1063 */ 1064 uint8_t vrefdqr1nib2; /* 1065 * Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut 1066 * VrefDq for rank 1 nibble 2. Specifies mr6[6:0]. 1067 * Identical to vrefdqr1nib0 for x16 devices. 1068 */ 1069 uint8_t vrefdqr1nib3; /* 1070 * Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut 1071 * VrefDq for rank 1 nibble 3. Specifies mr6[6:0]. 1072 * Identical to vrefdqr1nib0 for x16 devices, 1073 * or vrefdqr1nib2 for x8 devices. 1074 */ 1075 uint8_t vrefdqr1nib4; /* 1076 * Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut 1077 * VrefDq for rank 1 nibble 4. Specifies mr6[6:0] 1078 */ 1079 uint8_t vrefdqr1nib5; /* 1080 * Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut 1081 * VrefDq for rank 1 nibble 5. Specifies mr6[6:0]. 1082 * Identical to vrefdqr1nib4 for x8 or x16 devices. 1083 */ 1084 uint8_t vrefdqr1nib6; /* 1085 * Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut 1086 * VrefDq for rank 1 nibble 6. Specifies mr6[6:0]. 1087 * Identical to vrefdqr1nib4 for x16 devices. 1088 */ 1089 uint8_t vrefdqr1nib7; /* 1090 * Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut 1091 * VrefDq for rank 1 nibble 7. Specifies mr6[6:0]. 1092 * Identical to vrefdqr1nib4 for x16 devices, 1093 * or vrefdqr1nib6 for x8 devices. 1094 */ 1095 uint8_t vrefdqr1nib8; /* 1096 * Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut 1097 * VrefDq for rank 1 nibble 8. Specifies mr6[6:0] 1098 */ 1099 uint8_t vrefdqr1nib9; /* 1100 * Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut 1101 * VrefDq for rank 1 nibble 9. Specifies mr6[6:0]. 1102 * Identical to vrefdqr1nib8 for x8 or x16 devices. 1103 */ 1104 uint8_t vrefdqr1nib10; /* 1105 * Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut 1106 * VrefDq for rank 1 nibble 10. Specifies mr6[6:0]. 1107 * Identical to vrefdqr1nib8 for x16 devices. 1108 */ 1109 uint8_t vrefdqr1nib11; /* 1110 * Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut 1111 * VrefDq for rank 1 nibble 11. Specifies mr6[6:0]. 1112 * Identical to vrefdqr1nib8 for x16 devices, 1113 * or vrefdqr1nib10 for x8 devices. 1114 */ 1115 uint8_t vrefdqr1nib12; /* 1116 * Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut 1117 * VrefDq for rank 1 nibble 12. Specifies mr6[6:0] 1118 */ 1119 uint8_t vrefdqr1nib13; /* 1120 * Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut 1121 * VrefDq for rank 1 nibble 13. Specifies mr6[6:0]. 1122 * Identical to vrefdqr1nib12 for x8 or x16 devices. 1123 */ 1124 uint8_t vrefdqr1nib14; /* 1125 * Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut 1126 * VrefDq for rank 1 nibble 14. Specifies mr6[6:0]. 1127 * Identical to vrefdqr1nib12 for x16 devices. 1128 */ 1129 uint8_t vrefdqr1nib15; /* 1130 * Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut 1131 * VrefDq for rank 1 nibble 15. Specifies mr6[6:0]. 1132 * Identical to vrefdqr1nib12 for x16 devices, 1133 * or vrefdqr1nib14 for x8 devices. 1134 */ 1135 uint8_t vrefdqr1nib16; /* 1136 * Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut 1137 * VrefDq for rank 1 nibble 16. Specifies mr6[6:0] 1138 */ 1139 uint8_t vrefdqr1nib17; /* 1140 * Byte offset 0xab, CSR Addr 0x54055, Direction=InOut 1141 * VrefDq for rank 1 nibble 17. Specifies mr6[6:0]. 1142 * Identical to vrefdqr1nib16 for x8 or x16 devices. 1143 */ 1144 uint8_t vrefdqr1nib18; /* 1145 * Byte offset 0xac, CSR Addr 0x54056, Direction=InOut 1146 * VrefDq for rank 1 nibble 18. Specifies mr6[6:0]. 1147 * Identical to vrefdqr1nib16 for x16 devices. 1148 */ 1149 uint8_t vrefdqr1nib19; /* 1150 * Byte offset 0xad, CSR Addr 0x54056, Direction=InOut 1151 * VrefDq for rank 1 nibble 19. Specifies mr6[6:0]. 1152 * Identical to vrefdqr1nib16 for x16 devices, 1153 * or vrefdqr1nib18 for x8 devices. 1154 */ 1155 uint8_t vrefdqr2nib0; /* 1156 * Byte offset 0xae, CSR Addr 0x54057, Direction=InOut 1157 * VrefDq for rank 2 nibble 0. Specifies mr6[6:0] 1158 */ 1159 uint8_t vrefdqr2nib1; /* 1160 * Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut 1161 * VrefDq for rank 2 nibble 1. Specifies mr6[6:0]. 1162 * Identical to vrefdqr2nib0 for x8 or x16 devices. 1163 */ 1164 uint8_t vrefdqr2nib2; /* 1165 * Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut 1166 * VrefDq for rank 2 nibble 2. Specifies mr6[6:0]. 1167 * Identical to vrefdqr2nib0 for x16 devices. 1168 */ 1169 uint8_t vrefdqr2nib3; /* 1170 * Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut 1171 * VrefDq for rank 2 nibble 3. Specifies mr6[6:0]. 1172 * Identical to vrefdqr2nib0 for x16 devices, 1173 * or vrefdqr2nib2 for x8 devices. 1174 */ 1175 uint8_t vrefdqr2nib4; /* 1176 * Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut 1177 * VrefDq for rank 2 nibble 4. Specifies mr6[6:0] 1178 */ 1179 uint8_t vrefdqr2nib5; /* 1180 * Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut 1181 * VrefDq for rank 2 nibble 5. Specifies mr6[6:0]. 1182 * Identical to vrefdqr2nib4 for x8 or x16 devices. 1183 */ 1184 uint8_t vrefdqr2nib6; /* 1185 * Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut 1186 * VrefDq for rank 2 nibble 6. Specifies mr6[6:0]. 1187 * Identical to vrefdqr2nib4 for x16 devices. 1188 */ 1189 uint8_t vrefdqr2nib7; /* 1190 * Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut 1191 * VrefDq for rank 2 nibble 7. Specifies mr6[6:0]. 1192 * Identical to vrefdqr2nib4 for x16 devices, 1193 * or vrefdqr2nib6 for x8 devices. 1194 */ 1195 uint8_t vrefdqr2nib8; /* 1196 * Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut 1197 * VrefDq for rank 2 nibble 8. Specifies mr6[6:0] 1198 */ 1199 uint8_t vrefdqr2nib9; /* 1200 * Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut 1201 * VrefDq for rank 2 nibble 9. Specifies mr6[6:0]. 1202 * Identical to vrefdqr2nib8 for x8 or x16 devices. 1203 */ 1204 uint8_t vrefdqr2nib10; /* 1205 * Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut 1206 * VrefDq for rank 2 nibble 10. Specifies mr6[6:0]. 1207 * Identical to vrefdqr2nib8 for x16 devices. 1208 */ 1209 uint8_t vrefdqr2nib11; /* 1210 * Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut 1211 * VrefDq for rank 2 nibble 11. Specifies mr6[6:0]. 1212 * Identical to vrefdqr2nib8 for x16 devices, 1213 * or vrefdqr2nib10 for x8 devices. 1214 */ 1215 uint8_t vrefdqr2nib12; /* 1216 * Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut 1217 * VrefDq for rank 2 nibble 12. Specifies mr6[6:0] 1218 */ 1219 uint8_t vrefdqr2nib13; /* 1220 * Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut 1221 * VrefDq for rank 2 nibble 13. Specifies mr6[6:0]. 1222 * Identical to vrefdqr2nib12 for x8 or x16 devices. 1223 */ 1224 uint8_t vrefdqr2nib14; /* 1225 * Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut 1226 * VrefDq for rank 2 nibble 14. Specifies mr6[6:0]. 1227 * Identical to vrefdqr2nib12 for x16 devices. 1228 */ 1229 uint8_t vrefdqr2nib15; /* 1230 * Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut 1231 * VrefDq for rank 2 nibble 15. Specifies mr6[6:0]. 1232 * Identical to vrefdqr2nib12 for x16 devices, 1233 * or vrefdqr2nib14 for x8 devices. 1234 */ 1235 uint8_t vrefdqr2nib16; /* 1236 * Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut 1237 * VrefDq for rank 2 nibble 16. Specifies mr6[6:0] 1238 */ 1239 uint8_t vrefdqr2nib17; /* 1240 * Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut 1241 * VrefDq for rank 2 nibble 17. Specifies mr6[6:0]. 1242 * Identical to vrefdqr2nib16 for x8 or x16 devices. 1243 */ 1244 uint8_t vrefdqr2nib18; /* 1245 * Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut 1246 * VrefDq for rank 2 nibble 18. Specifies mr6[6:0]. 1247 * Identical to vrefdqr2nib16 for x16 devices. 1248 */ 1249 uint8_t vrefdqr2nib19; /* 1250 * Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut 1251 * VrefDq for rank 2 nibble 19. Specifies mr6[6:0]. 1252 * Identical to vrefdqr2nib16 for x16 devices, 1253 * or vrefdqr2nib18 for x8 devices. 1254 */ 1255 uint8_t vrefdqr3nib0; /* 1256 * Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut 1257 * VrefDq for rank 3 nibble 0. Specifies mr6[6:0] 1258 */ 1259 uint8_t vrefdqr3nib1; /* 1260 * Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut 1261 * VrefDq for rank 3 nibble 1. Specifies mr6[6:0]. 1262 * Identical to vrefdqr3nib0 for x8 or x16 devices. 1263 */ 1264 uint8_t vrefdqr3nib2; /* 1265 * Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut 1266 * VrefDq for rank 3 nibble 2. Specifies mr6[6:0]. 1267 * Identical to vrefdqr3nib0 for x16 devices. 1268 */ 1269 uint8_t vrefdqr3nib3; /* 1270 * Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut 1271 * VrefDq for rank 3 nibble 3. Specifies mr6[6:0]. 1272 * Identical to vrefdqr3nib0 for x16 devices, 1273 * or vrefdqr3nib2 for x8 devices. 1274 */ 1275 uint8_t vrefdqr3nib4; /* 1276 * Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut 1277 * VrefDq for rank 3 nibble 4. Specifies mr6[6:0] 1278 */ 1279 uint8_t vrefdqr3nib5; /* 1280 * Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut 1281 * VrefDq for rank 3 nibble 5. Specifies mr6[6:0]. 1282 * Identical to vrefdqr3nib4 for x8 or x16 devices. 1283 */ 1284 uint8_t vrefdqr3nib6; /* 1285 * Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut 1286 * VrefDq for rank 3 nibble 6. Specifies mr6[6:0]. 1287 * Identical to vrefdqr3nib4 for x16 devices. 1288 */ 1289 uint8_t vrefdqr3nib7; /* 1290 * Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut 1291 * VrefDq for rank 3 nibble 7. Specifies mr6[6:0]. 1292 * Identical to vrefdqr3nib4 for x16 devices, 1293 * or vrefdqr3nib6 for x8 devices. 1294 */ 1295 uint8_t vrefdqr3nib8; /* 1296 * Byte offset 0xca, CSR Addr 0x54065, Direction=InOut 1297 * VrefDq for rank 3 nibble 8. Specifies mr6[6:0] 1298 */ 1299 uint8_t vrefdqr3nib9; /* 1300 * Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut 1301 * VrefDq for rank 3 nibble 9. Specifies mr6[6:0]. 1302 * Identical to vrefdqr3nib8 for x8 or x16 devices. 1303 */ 1304 uint8_t vrefdqr3nib10; /* 1305 * Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut 1306 * VrefDq for rank 3 nibble 10. Specifies mr6[6:0]. 1307 * Identical to vrefdqr3nib8 for x16 devices. 1308 */ 1309 uint8_t vrefdqr3nib11; /* 1310 * Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut 1311 * VrefDq for rank 3 nibble 11. Specifies mr6[6:0]. 1312 * Identical to vrefdqr3nib8 for x16 devices, 1313 * or vrefdqr3nib10 for x8 devices. 1314 */ 1315 uint8_t vrefdqr3nib12; /* 1316 * Byte offset 0xce, CSR Addr 0x54067, Direction=InOut 1317 * VrefDq for rank 3 nibble 12. Specifies mr6[6:0] 1318 */ 1319 uint8_t vrefdqr3nib13; /* 1320 * Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut 1321 * VrefDq for rank 3 nibble 13. Specifies mr6[6:0]. 1322 * Identical to vrefdqr3nib12 for x8 or x16 devices. 1323 */ 1324 uint8_t vrefdqr3nib14; /* 1325 * Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut 1326 * VrefDq for rank 3 nibble 14. Specifies mr6[6:0]. 1327 * Identical to vrefdqr3nib12 for x16 devices. 1328 */ 1329 uint8_t vrefdqr3nib15; /* 1330 * Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut 1331 * VrefDq for rank 3 nibble 15. Specifies mr6[6:0]. 1332 * Identical to vrefdqr3nib12 for x16 devices, 1333 * or vrefdqr3nib14 for x8 devices. 1334 */ 1335 uint8_t vrefdqr3nib16; /* 1336 * Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut 1337 * VrefDq for rank 3 nibble 16. Specifies mr6[6:0] 1338 */ 1339 uint8_t vrefdqr3nib17; /* 1340 * Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut 1341 * VrefDq for rank 3 nibble 17. Specifies mr6[6:0]. 1342 * Identical to vrefdqr3nib16 for x8 or x16 devices. 1343 */ 1344 uint8_t vrefdqr3nib18; /* 1345 * Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut 1346 * VrefDq for rank 3 nibble 18. Specifies mr6[6:0]. 1347 * Identical to vrefdqr3nib16 for x16 devices. 1348 */ 1349 uint8_t vrefdqr3nib19; /* 1350 * Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut 1351 * VrefDq for rank 3 nibble 19. Specifies mr6[6:0]. 1352 * Identical to vrefdqr3nib16 for x16 devices, 1353 * or vrefdqr3nib18 for x8 devices. 1354 */ 1355 uint8_t reservedd6; /* Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A */ 1356 uint8_t reservedd7; /* Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A */ 1357 uint8_t reservedd8; /* Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A */ 1358 uint8_t reservedd9; /* Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A */ 1359 uint8_t reservedda; /* Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A */ 1360 uint8_t reserveddb; /* Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A */ 1361 uint8_t reserveddc; /* Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A */ 1362 uint8_t reserveddd; /* Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A */ 1363 uint8_t reservedde; /* Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A */ 1364 uint8_t reserveddf; /* Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A */ 1365 uint8_t reservede0; /* Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A */ 1366 uint8_t reservede1; /* Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A */ 1367 uint8_t reservede2; /* Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A */ 1368 uint8_t reservede3; /* Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A */ 1369 uint8_t reservede4; /* Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A */ 1370 uint8_t reservede5; /* Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A */ 1371 uint8_t reservede6; /* Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A */ 1372 uint8_t reservede7; /* Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A */ 1373 uint8_t reservede8; /* Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A */ 1374 uint8_t reservede9; /* Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A */ 1375 uint8_t reservedea; /* Byte offset 0xea, CSR Addr 0x54075, Direction=N/A */ 1376 uint8_t reservedeb; /* Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A */ 1377 uint8_t reservedec; /* Byte offset 0xec, CSR Addr 0x54076, Direction=N/A */ 1378 uint8_t reserveded; /* Byte offset 0xed, CSR Addr 0x54076, Direction=N/A */ 1379 uint8_t reservedee; /* Byte offset 0xee, CSR Addr 0x54077, Direction=N/A */ 1380 uint8_t reservedef; /* Byte offset 0xef, CSR Addr 0x54077, Direction=N/A */ 1381 uint8_t reservedf0; /* Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A */ 1382 uint8_t reservedf1; /* Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A */ 1383 uint8_t reservedf2; /* Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A */ 1384 uint8_t reservedf3; /* Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A */ 1385 uint8_t reservedf4; /* Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A */ 1386 uint8_t reservedf5; /* Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A */ 1387 uint8_t reservedf6; /* Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A */ 1388 uint8_t reservedf7; /* Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A */ 1389 uint8_t reservedf8; /* Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A */ 1390 uint8_t reservedf9; /* Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A */ 1391 uint8_t reservedfa; /* Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A */ 1392 uint8_t reservedfb; /* Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A */ 1393 uint8_t reservedfc; /* Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A */ 1394 uint8_t reservedfd; /* Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A */ 1395 uint8_t reservedfe; /* Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A */ 1396 uint8_t reservedff; /* Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A */ 1397 uint8_t reserved100; /* Byte offset 0x100, CSR Addr 0x54080, Direction=N/A */ 1398 uint8_t reserved101; /* Byte offset 0x101, CSR Addr 0x54080, Direction=N/A */ 1399 uint8_t reserved102; /* Byte offset 0x102, CSR Addr 0x54081, Direction=N/A */ 1400 uint8_t reserved103; /* Byte offset 0x103, CSR Addr 0x54081, Direction=N/A */ 1401 uint8_t reserved104; /* Byte offset 0x104, CSR Addr 0x54082, Direction=N/A */ 1402 uint8_t reserved105; /* Byte offset 0x105, CSR Addr 0x54082, Direction=N/A */ 1403 uint8_t reserved106; /* Byte offset 0x106, CSR Addr 0x54083, Direction=N/A */ 1404 uint8_t reserved107; /* Byte offset 0x107, CSR Addr 0x54083, Direction=N/A */ 1405 uint8_t reserved108; /* Byte offset 0x108, CSR Addr 0x54084, Direction=N/A */ 1406 uint8_t reserved109; /* Byte offset 0x109, CSR Addr 0x54084, Direction=N/A */ 1407 uint8_t reserved10a; /* Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A */ 1408 uint8_t reserved10b; /* Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A */ 1409 uint8_t reserved10c; /* Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A */ 1410 uint8_t reserved10d; /* Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A */ 1411 uint8_t reserved10e; /* Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A */ 1412 uint8_t reserved10f; /* Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A */ 1413 uint8_t reserved110; /* Byte offset 0x110, CSR Addr 0x54088, Direction=N/A */ 1414 uint8_t reserved111; /* Byte offset 0x111, CSR Addr 0x54088, Direction=N/A */ 1415 uint8_t reserved112; /* Byte offset 0x112, CSR Addr 0x54089, Direction=N/A */ 1416 uint8_t reserved113; /* Byte offset 0x113, CSR Addr 0x54089, Direction=N/A */ 1417 uint8_t reserved114; /* Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A */ 1418 uint8_t reserved115; /* Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A */ 1419 uint8_t reserved116; /* Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A */ 1420 uint8_t reserved117; /* Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A */ 1421 uint8_t reserved118; /* Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A */ 1422 uint8_t reserved119; /* Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A */ 1423 uint8_t reserved11a; /* Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A */ 1424 uint8_t reserved11b; /* Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A */ 1425 uint8_t reserved11c; /* Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A */ 1426 uint8_t reserved11d; /* Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A */ 1427 uint8_t reserved11e; /* Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A */ 1428 uint8_t reserved11f; /* Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A */ 1429 uint8_t reserved120; /* Byte offset 0x120, CSR Addr 0x54090, Direction=N/A */ 1430 uint8_t reserved121; /* Byte offset 0x121, CSR Addr 0x54090, Direction=N/A */ 1431 uint8_t reserved122; /* Byte offset 0x122, CSR Addr 0x54091, Direction=N/A */ 1432 uint8_t reserved123; /* Byte offset 0x123, CSR Addr 0x54091, Direction=N/A */ 1433 uint8_t reserved124; /* Byte offset 0x124, CSR Addr 0x54092, Direction=N/A */ 1434 uint8_t reserved125; /* Byte offset 0x125, CSR Addr 0x54092, Direction=N/A */ 1435 uint8_t reserved126; /* Byte offset 0x126, CSR Addr 0x54093, Direction=N/A */ 1436 uint8_t reserved127; /* Byte offset 0x127, CSR Addr 0x54093, Direction=N/A */ 1437 uint8_t reserved128; /* Byte offset 0x128, CSR Addr 0x54094, Direction=N/A */ 1438 uint8_t reserved129; /* Byte offset 0x129, CSR Addr 0x54094, Direction=N/A */ 1439 uint8_t reserved12a; /* Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A */ 1440 uint8_t reserved12b; /* Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A */ 1441 uint8_t reserved12c; /* Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A */ 1442 uint8_t reserved12d; /* Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A */ 1443 uint8_t reserved12e; /* Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A */ 1444 uint8_t reserved12f; /* Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A */ 1445 uint8_t reserved130; /* Byte offset 0x130, CSR Addr 0x54098, Direction=N/A */ 1446 uint8_t reserved131; /* Byte offset 0x131, CSR Addr 0x54098, Direction=N/A */ 1447 uint8_t reserved132; /* Byte offset 0x132, CSR Addr 0x54099, Direction=N/A */ 1448 uint8_t reserved133; /* Byte offset 0x133, CSR Addr 0x54099, Direction=N/A */ 1449 uint8_t reserved134; /* Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A */ 1450 uint8_t reserved135; /* Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A */ 1451 uint8_t reserved136; /* Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A */ 1452 uint8_t reserved137; /* Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A */ 1453 uint8_t reserved138; /* Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A */ 1454 uint8_t reserved139; /* Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A */ 1455 uint8_t reserved13a; /* Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A */ 1456 uint8_t reserved13b; /* Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A */ 1457 uint8_t reserved13c; /* Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A */ 1458 uint8_t reserved13d; /* Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A */ 1459 uint8_t reserved13e; /* Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A */ 1460 uint8_t reserved13f; /* Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A */ 1461 uint8_t reserved140; /* Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A */ 1462 uint8_t reserved141; /* Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A */ 1463 uint8_t reserved142; /* Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A */ 1464 uint8_t reserved143; /* Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A */ 1465 uint8_t reserved144; /* Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A */ 1466 uint8_t reserved145; /* Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A */ 1467 uint8_t reserved146; /* Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A */ 1468 uint8_t reserved147; /* Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A */ 1469 uint8_t reserved148; /* Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A */ 1470 uint8_t reserved149; /* Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A */ 1471 uint8_t reserved14a; /* Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A */ 1472 uint8_t reserved14b; /* Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A */ 1473 uint8_t reserved14c; /* Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A */ 1474 uint8_t reserved14d; /* Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A */ 1475 uint8_t reserved14e; /* Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A */ 1476 uint8_t reserved14f; /* Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A */ 1477 uint8_t reserved150; /* Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A */ 1478 uint8_t reserved151; /* Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A */ 1479 uint8_t reserved152; /* Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A */ 1480 uint8_t reserved153; /* Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A */ 1481 uint8_t reserved154; /* Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A */ 1482 uint8_t reserved155; /* Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A */ 1483 uint8_t reserved156; /* Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A */ 1484 uint8_t reserved157; /* Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A */ 1485 uint8_t reserved158; /* Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A */ 1486 uint8_t reserved159; /* Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A */ 1487 uint8_t reserved15a; /* Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A */ 1488 uint8_t reserved15b; /* Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A */ 1489 uint8_t reserved15c; /* Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A */ 1490 uint8_t reserved15d; /* Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A */ 1491 uint8_t reserved15e; /* Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A */ 1492 uint8_t reserved15f; /* Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A */ 1493 uint8_t reserved160; /* Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A */ 1494 uint8_t reserved161; /* Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A */ 1495 uint8_t reserved162; /* Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A */ 1496 uint8_t reserved163; /* Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A */ 1497 uint8_t reserved164; /* Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A */ 1498 uint8_t reserved165; /* Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A */ 1499 uint8_t reserved166; /* Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A */ 1500 uint8_t reserved167; /* Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A */ 1501 uint8_t reserved168; /* Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A */ 1502 uint8_t reserved169; /* Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A */ 1503 uint8_t reserved16a; /* Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A */ 1504 uint8_t reserved16b; /* Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A */ 1505 uint8_t reserved16c; /* Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A */ 1506 uint8_t reserved16d; /* Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A */ 1507 uint8_t reserved16e; /* Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A */ 1508 uint8_t reserved16f; /* Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A */ 1509 uint8_t reserved170; /* Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A */ 1510 uint8_t reserved171; /* Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A */ 1511 uint8_t reserved172; /* Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A */ 1512 uint8_t reserved173; /* Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A */ 1513 uint8_t reserved174; /* Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A */ 1514 uint8_t reserved175; /* Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A */ 1515 uint8_t reserved176; /* Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A */ 1516 uint8_t reserved177; /* Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A */ 1517 uint8_t reserved178; /* Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A */ 1518 uint8_t reserved179; /* Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A */ 1519 uint8_t reserved17a; /* Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A */ 1520 uint8_t reserved17b; /* Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A */ 1521 uint8_t reserved17c; /* Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A */ 1522 uint8_t reserved17d; /* Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A */ 1523 uint8_t reserved17e; /* Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A */ 1524 uint8_t reserved17f; /* Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A */ 1525 uint8_t reserved180; /* Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A */ 1526 uint8_t reserved181; /* Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A */ 1527 uint8_t reserved182; /* Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A */ 1528 uint8_t reserved183; /* Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A */ 1529 uint8_t reserved184; /* Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A */ 1530 uint8_t reserved185; /* Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A */ 1531 uint8_t reserved186; /* Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A */ 1532 uint8_t reserved187; /* Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A */ 1533 uint8_t reserved188; /* Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A */ 1534 uint8_t reserved189; /* Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A */ 1535 uint8_t reserved18a; /* Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A */ 1536 uint8_t reserved18b; /* Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A */ 1537 uint8_t reserved18c; /* Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A */ 1538 uint8_t reserved18d; /* Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A */ 1539 uint8_t reserved18e; /* Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A */ 1540 uint8_t reserved18f; /* Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A */ 1541 uint8_t reserved190; /* Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A */ 1542 uint8_t reserved191; /* Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A */ 1543 uint8_t reserved192; /* Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A */ 1544 uint8_t reserved193; /* Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A */ 1545 uint8_t reserved194; /* Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A */ 1546 uint8_t reserved195; /* Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A */ 1547 uint8_t reserved196; /* Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A */ 1548 uint8_t reserved197; /* Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A */ 1549 uint8_t reserved198; /* Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A */ 1550 uint8_t reserved199; /* Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A */ 1551 uint8_t reserved19a; /* Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A */ 1552 uint8_t reserved19b; /* Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A */ 1553 uint8_t reserved19c; /* Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A */ 1554 uint8_t reserved19d; /* Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A */ 1555 uint8_t reserved19e; /* Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A */ 1556 uint8_t reserved19f; /* Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A */ 1557 uint8_t reserved1a0; /* Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A */ 1558 uint8_t reserved1a1; /* Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A */ 1559 uint8_t reserved1a2; /* Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A */ 1560 uint8_t reserved1a3; /* Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A */ 1561 uint8_t reserved1a4; /* Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A */ 1562 uint8_t reserved1a5; /* Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A */ 1563 uint8_t reserved1a6; /* Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A */ 1564 uint8_t reserved1a7; /* Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A */ 1565 uint8_t reserved1a8; /* Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A */ 1566 uint8_t reserved1a9; /* Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A */ 1567 uint8_t reserved1aa; /* Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A */ 1568 uint8_t reserved1ab; /* Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A */ 1569 uint8_t reserved1ac; /* Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A */ 1570 uint8_t reserved1ad; /* Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A */ 1571 uint8_t reserved1ae; /* Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A */ 1572 uint8_t reserved1af; /* Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A */ 1573 uint8_t reserved1b0; /* Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A */ 1574 uint8_t reserved1b1; /* Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A */ 1575 uint8_t reserved1b2; /* Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A */ 1576 uint8_t reserved1b3; /* Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A */ 1577 uint8_t reserved1b4; /* Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A */ 1578 uint8_t reserved1b5; /* Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A */ 1579 uint8_t reserved1b6; /* Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A */ 1580 uint8_t reserved1b7; /* Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A */ 1581 uint8_t reserved1b8; /* Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A */ 1582 uint8_t reserved1b9; /* Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A */ 1583 uint8_t reserved1ba; /* Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A */ 1584 uint8_t reserved1bb; /* Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A */ 1585 uint8_t reserved1bc; /* Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A */ 1586 uint8_t reserved1bd; /* Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A */ 1587 uint8_t reserved1be; /* Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A */ 1588 uint8_t reserved1bf; /* Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A */ 1589 uint8_t reserved1c0; /* Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A */ 1590 uint8_t reserved1c1; /* Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A */ 1591 uint8_t reserved1c2; /* Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A */ 1592 uint8_t reserved1c3; /* Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A */ 1593 uint8_t reserved1c4; /* Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A */ 1594 uint8_t reserved1c5; /* Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A */ 1595 uint8_t reserved1c6; /* Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A */ 1596 uint8_t reserved1c7; /* Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A */ 1597 uint8_t reserved1c8; /* Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A */ 1598 uint8_t reserved1c9; /* Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A */ 1599 uint8_t reserved1ca; /* Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A */ 1600 uint8_t reserved1cb; /* Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A */ 1601 uint8_t reserved1cc; /* Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A */ 1602 uint8_t reserved1cd; /* Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A */ 1603 uint8_t reserved1ce; /* Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A */ 1604 uint8_t reserved1cf; /* Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A */ 1605 uint8_t reserved1d0; /* Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A */ 1606 uint8_t reserved1d1; /* Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A */ 1607 uint8_t reserved1d2; /* Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A */ 1608 uint8_t reserved1d3; /* Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A */ 1609 uint8_t reserved1d4; /* Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A */ 1610 uint8_t reserved1d5; /* Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A */ 1611 uint8_t reserved1d6; /* Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A */ 1612 uint8_t reserved1d7; /* Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A */ 1613 uint8_t reserved1d8; /* Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A */ 1614 uint8_t reserved1d9; /* Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A */ 1615 uint8_t reserved1da; /* Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A */ 1616 uint8_t reserved1db; /* Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A */ 1617 uint8_t reserved1dc; /* Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A */ 1618 uint8_t reserved1dd; /* Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A */ 1619 uint8_t reserved1de; /* Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A */ 1620 uint8_t reserved1df; /* Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A */ 1621 uint8_t reserved1e0; /* Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A */ 1622 uint8_t reserved1e1; /* Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A */ 1623 uint8_t reserved1e2; /* Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A */ 1624 uint8_t reserved1e3; /* Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A */ 1625 uint8_t reserved1e4; /* Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A */ 1626 uint8_t reserved1e5; /* Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A */ 1627 uint8_t reserved1e6; /* Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A */ 1628 uint8_t reserved1e7; /* Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A */ 1629 uint8_t reserved1e8; /* Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A */ 1630 uint8_t reserved1e9; /* Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A */ 1631 uint8_t reserved1ea; /* Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A */ 1632 uint8_t reserved1eb; /* Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A */ 1633 uint8_t reserved1ec; /* Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A */ 1634 uint8_t reserved1ed; /* Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A */ 1635 uint8_t reserved1ee; /* Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A */ 1636 uint8_t reserved1ef; /* Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A */ 1637 uint8_t reserved1f0; /* Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A */ 1638 uint8_t reserved1f1; /* Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A */ 1639 uint8_t reserved1f2; /* Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A */ 1640 uint8_t reserved1f3; /* Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A */ 1641 uint8_t reserved1f4; /* Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A */ 1642 uint8_t reserved1f5; /* Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A */ 1643 uint8_t reserved1f6; /* Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A */ 1644 uint8_t reserved1f7; /* Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A */ 1645 uint8_t reserved1f8; /* Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A */ 1646 uint8_t reserved1f9; /* Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A */ 1647 uint8_t reserved1fa; /* Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A */ 1648 uint8_t reserved1fb; /* Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A */ 1649 uint8_t reserved1fc; /* Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A */ 1650 uint8_t reserved1fd; /* Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A */ 1651 uint8_t reserved1fe; /* Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A */ 1652 uint8_t reserved1ff; /* Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A */ 1653 uint8_t reserved200; /* Byte offset 0x200, CSR Addr 0x54100, Direction=N/A */ 1654 uint8_t reserved201; /* Byte offset 0x201, CSR Addr 0x54100, Direction=N/A */ 1655 uint8_t reserved202; /* Byte offset 0x202, CSR Addr 0x54101, Direction=N/A */ 1656 uint8_t reserved203; /* Byte offset 0x203, CSR Addr 0x54101, Direction=N/A */ 1657 uint8_t reserved204; /* Byte offset 0x204, CSR Addr 0x54102, Direction=N/A */ 1658 uint8_t reserved205; /* Byte offset 0x205, CSR Addr 0x54102, Direction=N/A */ 1659 uint8_t reserved206; /* Byte offset 0x206, CSR Addr 0x54103, Direction=N/A */ 1660 uint8_t reserved207; /* Byte offset 0x207, CSR Addr 0x54103, Direction=N/A */ 1661 uint8_t reserved208; /* Byte offset 0x208, CSR Addr 0x54104, Direction=N/A */ 1662 uint8_t reserved209; /* Byte offset 0x209, CSR Addr 0x54104, Direction=N/A */ 1663 uint8_t reserved20a; /* Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A */ 1664 uint8_t reserved20b; /* Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A */ 1665 uint8_t reserved20c; /* Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A */ 1666 uint8_t reserved20d; /* Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A */ 1667 uint8_t reserved20e; /* Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A */ 1668 uint8_t reserved20f; /* Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A */ 1669 uint8_t reserved210; /* Byte offset 0x210, CSR Addr 0x54108, Direction=N/A */ 1670 uint8_t reserved211; /* Byte offset 0x211, CSR Addr 0x54108, Direction=N/A */ 1671 uint8_t reserved212; /* Byte offset 0x212, CSR Addr 0x54109, Direction=N/A */ 1672 uint8_t reserved213; /* Byte offset 0x213, CSR Addr 0x54109, Direction=N/A */ 1673 uint8_t reserved214; /* Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A */ 1674 uint8_t reserved215; /* Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A */ 1675 uint8_t reserved216; /* Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A */ 1676 uint8_t reserved217; /* Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A */ 1677 uint8_t reserved218; /* Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A */ 1678 uint8_t reserved219; /* Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A */ 1679 uint8_t reserved21a; /* Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A */ 1680 uint8_t reserved21b; /* Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A */ 1681 uint8_t reserved21c; /* Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A */ 1682 uint8_t reserved21d; /* Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A */ 1683 uint8_t reserved21e; /* Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A */ 1684 uint8_t reserved21f; /* Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A */ 1685 uint8_t reserved220; /* Byte offset 0x220, CSR Addr 0x54110, Direction=N/A */ 1686 uint8_t reserved221; /* Byte offset 0x221, CSR Addr 0x54110, Direction=N/A */ 1687 uint8_t reserved222; /* Byte offset 0x222, CSR Addr 0x54111, Direction=N/A */ 1688 uint8_t reserved223; /* Byte offset 0x223, CSR Addr 0x54111, Direction=N/A */ 1689 uint8_t reserved224; /* Byte offset 0x224, CSR Addr 0x54112, Direction=N/A */ 1690 uint8_t reserved225; /* Byte offset 0x225, CSR Addr 0x54112, Direction=N/A */ 1691 uint8_t reserved226; /* Byte offset 0x226, CSR Addr 0x54113, Direction=N/A */ 1692 uint8_t reserved227; /* Byte offset 0x227, CSR Addr 0x54113, Direction=N/A */ 1693 uint8_t reserved228; /* Byte offset 0x228, CSR Addr 0x54114, Direction=N/A */ 1694 uint8_t reserved229; /* Byte offset 0x229, CSR Addr 0x54114, Direction=N/A */ 1695 uint8_t reserved22a; /* Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A */ 1696 uint8_t reserved22b; /* Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A */ 1697 uint8_t reserved22c; /* Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A */ 1698 uint8_t reserved22d; /* Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A */ 1699 uint8_t reserved22e; /* Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A */ 1700 uint8_t reserved22f; /* Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A */ 1701 uint8_t reserved230; /* Byte offset 0x230, CSR Addr 0x54118, Direction=N/A */ 1702 uint8_t reserved231; /* Byte offset 0x231, CSR Addr 0x54118, Direction=N/A */ 1703 uint8_t reserved232; /* Byte offset 0x232, CSR Addr 0x54119, Direction=N/A */ 1704 uint8_t reserved233; /* Byte offset 0x233, CSR Addr 0x54119, Direction=N/A */ 1705 uint8_t reserved234; /* Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A */ 1706 uint8_t reserved235; /* Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A */ 1707 uint8_t reserved236; /* Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A */ 1708 uint8_t reserved237; /* Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A */ 1709 uint8_t reserved238; /* Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A */ 1710 uint8_t reserved239; /* Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A */ 1711 uint8_t reserved23a; /* Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A */ 1712 uint8_t reserved23b; /* Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A */ 1713 uint8_t reserved23c; /* Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A */ 1714 uint8_t reserved23d; /* Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A */ 1715 uint8_t reserved23e; /* Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A */ 1716 uint8_t reserved23f; /* Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A */ 1717 uint8_t reserved240; /* Byte offset 0x240, CSR Addr 0x54120, Direction=N/A */ 1718 uint8_t reserved241; /* Byte offset 0x241, CSR Addr 0x54120, Direction=N/A */ 1719 uint8_t reserved242; /* Byte offset 0x242, CSR Addr 0x54121, Direction=N/A */ 1720 uint8_t reserved243; /* Byte offset 0x243, CSR Addr 0x54121, Direction=N/A */ 1721 uint8_t reserved244; /* Byte offset 0x244, CSR Addr 0x54122, Direction=N/A */ 1722 uint8_t reserved245; /* Byte offset 0x245, CSR Addr 0x54122, Direction=N/A */ 1723 uint8_t reserved246; /* Byte offset 0x246, CSR Addr 0x54123, Direction=N/A */ 1724 uint8_t reserved247; /* Byte offset 0x247, CSR Addr 0x54123, Direction=N/A */ 1725 uint8_t reserved248; /* Byte offset 0x248, CSR Addr 0x54124, Direction=N/A */ 1726 uint8_t reserved249; /* Byte offset 0x249, CSR Addr 0x54124, Direction=N/A */ 1727 uint8_t reserved24a; /* Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A */ 1728 uint8_t reserved24b; /* Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A */ 1729 uint8_t reserved24c; /* Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A */ 1730 uint8_t reserved24d; /* Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A */ 1731 uint8_t reserved24e; /* Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A */ 1732 uint8_t reserved24f; /* Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A */ 1733 uint8_t reserved250; /* Byte offset 0x250, CSR Addr 0x54128, Direction=N/A */ 1734 uint8_t reserved251; /* Byte offset 0x251, CSR Addr 0x54128, Direction=N/A */ 1735 uint8_t reserved252; /* Byte offset 0x252, CSR Addr 0x54129, Direction=N/A */ 1736 uint8_t reserved253; /* Byte offset 0x253, CSR Addr 0x54129, Direction=N/A */ 1737 uint8_t reserved254; /* Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A */ 1738 uint8_t reserved255; /* Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A */ 1739 uint8_t reserved256; /* Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A */ 1740 uint8_t reserved257; /* Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A */ 1741 uint8_t reserved258; /* Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A */ 1742 uint8_t reserved259; /* Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A */ 1743 uint8_t reserved25a; /* Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A */ 1744 uint8_t reserved25b; /* Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A */ 1745 uint8_t reserved25c; /* Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A */ 1746 uint8_t reserved25d; /* Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A */ 1747 uint8_t reserved25e; /* Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A */ 1748 uint8_t reserved25f; /* Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A */ 1749 uint8_t reserved260; /* Byte offset 0x260, CSR Addr 0x54130, Direction=N/A */ 1750 uint8_t reserved261; /* Byte offset 0x261, CSR Addr 0x54130, Direction=N/A */ 1751 uint8_t reserved262; /* Byte offset 0x262, CSR Addr 0x54131, Direction=N/A */ 1752 uint8_t reserved263; /* Byte offset 0x263, CSR Addr 0x54131, Direction=N/A */ 1753 uint8_t reserved264; /* Byte offset 0x264, CSR Addr 0x54132, Direction=N/A */ 1754 uint8_t reserved265; /* Byte offset 0x265, CSR Addr 0x54132, Direction=N/A */ 1755 uint8_t reserved266; /* Byte offset 0x266, CSR Addr 0x54133, Direction=N/A */ 1756 uint8_t reserved267; /* Byte offset 0x267, CSR Addr 0x54133, Direction=N/A */ 1757 uint8_t reserved268; /* Byte offset 0x268, CSR Addr 0x54134, Direction=N/A */ 1758 uint8_t reserved269; /* Byte offset 0x269, CSR Addr 0x54134, Direction=N/A */ 1759 uint8_t reserved26a; /* Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A */ 1760 uint8_t reserved26b; /* Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A */ 1761 uint8_t reserved26c; /* Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A */ 1762 uint8_t reserved26d; /* Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A */ 1763 uint8_t reserved26e; /* Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A */ 1764 uint8_t reserved26f; /* Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A */ 1765 uint8_t reserved270; /* Byte offset 0x270, CSR Addr 0x54138, Direction=N/A */ 1766 uint8_t reserved271; /* Byte offset 0x271, CSR Addr 0x54138, Direction=N/A */ 1767 uint8_t reserved272; /* Byte offset 0x272, CSR Addr 0x54139, Direction=N/A */ 1768 uint8_t reserved273; /* Byte offset 0x273, CSR Addr 0x54139, Direction=N/A */ 1769 uint8_t reserved274; /* Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A */ 1770 uint8_t reserved275; /* Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A */ 1771 uint8_t reserved276; /* Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A */ 1772 uint8_t reserved277; /* Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A */ 1773 uint8_t reserved278; /* Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A */ 1774 uint8_t reserved279; /* Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A */ 1775 uint8_t reserved27a; /* Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A */ 1776 uint8_t reserved27b; /* Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A */ 1777 uint8_t reserved27c; /* Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A */ 1778 uint8_t reserved27d; /* Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A */ 1779 uint8_t reserved27e; /* Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A */ 1780 uint8_t reserved27f; /* Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A */ 1781 uint8_t reserved280; /* Byte offset 0x280, CSR Addr 0x54140, Direction=N/A */ 1782 uint8_t reserved281; /* Byte offset 0x281, CSR Addr 0x54140, Direction=N/A */ 1783 uint8_t reserved282; /* Byte offset 0x282, CSR Addr 0x54141, Direction=N/A */ 1784 uint8_t reserved283; /* Byte offset 0x283, CSR Addr 0x54141, Direction=N/A */ 1785 uint8_t reserved284; /* Byte offset 0x284, CSR Addr 0x54142, Direction=N/A */ 1786 uint8_t reserved285; /* Byte offset 0x285, CSR Addr 0x54142, Direction=N/A */ 1787 uint8_t reserved286; /* Byte offset 0x286, CSR Addr 0x54143, Direction=N/A */ 1788 uint8_t reserved287; /* Byte offset 0x287, CSR Addr 0x54143, Direction=N/A */ 1789 uint8_t reserved288; /* Byte offset 0x288, CSR Addr 0x54144, Direction=N/A */ 1790 uint8_t reserved289; /* Byte offset 0x289, CSR Addr 0x54144, Direction=N/A */ 1791 uint8_t reserved28a; /* Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A */ 1792 uint8_t reserved28b; /* Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A */ 1793 uint8_t reserved28c; /* Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A */ 1794 uint8_t reserved28d; /* Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A */ 1795 uint8_t reserved28e; /* Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A */ 1796 uint8_t reserved28f; /* Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A */ 1797 uint8_t reserved290; /* Byte offset 0x290, CSR Addr 0x54148, Direction=N/A */ 1798 uint8_t reserved291; /* Byte offset 0x291, CSR Addr 0x54148, Direction=N/A */ 1799 uint8_t reserved292; /* Byte offset 0x292, CSR Addr 0x54149, Direction=N/A */ 1800 uint8_t reserved293; /* Byte offset 0x293, CSR Addr 0x54149, Direction=N/A */ 1801 uint8_t reserved294; /* Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A */ 1802 uint8_t reserved295; /* Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A */ 1803 uint8_t reserved296; /* Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A */ 1804 uint8_t reserved297; /* Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A */ 1805 uint8_t reserved298; /* Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A */ 1806 uint8_t reserved299; /* Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A */ 1807 uint8_t reserved29a; /* Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A */ 1808 uint8_t reserved29b; /* Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A */ 1809 uint8_t reserved29c; /* Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A */ 1810 uint8_t reserved29d; /* Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A */ 1811 uint8_t reserved29e; /* Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A */ 1812 uint8_t reserved29f; /* Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A */ 1813 uint8_t reserved2a0; /* Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A */ 1814 uint8_t reserved2a1; /* Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A */ 1815 uint8_t reserved2a2; /* Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A */ 1816 uint8_t reserved2a3; /* Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A */ 1817 uint8_t reserved2a4; /* Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A */ 1818 uint8_t reserved2a5; /* Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A */ 1819 uint8_t reserved2a6; /* Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A */ 1820 uint8_t reserved2a7; /* Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A */ 1821 uint8_t reserved2a8; /* Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A */ 1822 uint8_t reserved2a9; /* Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A */ 1823 uint8_t reserved2aa; /* Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A */ 1824 uint8_t reserved2ab; /* Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A */ 1825 uint8_t reserved2ac; /* Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A */ 1826 uint8_t reserved2ad; /* Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A */ 1827 uint8_t reserved2ae; /* Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A */ 1828 uint8_t reserved2af; /* Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A */ 1829 uint8_t reserved2b0; /* Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A */ 1830 uint8_t reserved2b1; /* Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A */ 1831 uint8_t reserved2b2; /* Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A */ 1832 uint8_t reserved2b3; /* Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A */ 1833 uint8_t reserved2b4; /* Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A */ 1834 uint8_t reserved2b5; /* Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A */ 1835 uint8_t reserved2b6; /* Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A */ 1836 uint8_t reserved2b7; /* Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A */ 1837 uint8_t reserved2b8; /* Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A */ 1838 uint8_t reserved2b9; /* Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A */ 1839 uint8_t reserved2ba; /* Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A */ 1840 uint8_t reserved2bb; /* Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A */ 1841 uint8_t reserved2bc; /* Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A */ 1842 uint8_t reserved2bd; /* Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A */ 1843 uint8_t reserved2be; /* Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A */ 1844 uint8_t reserved2bf; /* Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A */ 1845 uint8_t reserved2c0; /* Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A */ 1846 uint8_t reserved2c1; /* Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A */ 1847 uint8_t reserved2c2; /* Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A */ 1848 uint8_t reserved2c3; /* Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A */ 1849 uint8_t reserved2c4; /* Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A */ 1850 uint8_t reserved2c5; /* Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A */ 1851 uint8_t reserved2c6; /* Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A */ 1852 uint8_t reserved2c7; /* Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A */ 1853 uint8_t reserved2c8; /* Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A */ 1854 uint8_t reserved2c9; /* Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A */ 1855 uint8_t reserved2ca; /* Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A */ 1856 uint8_t reserved2cb; /* Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A */ 1857 uint8_t reserved2cc; /* Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A */ 1858 uint8_t reserved2cd; /* Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A */ 1859 uint8_t reserved2ce; /* Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A */ 1860 uint8_t reserved2cf; /* Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A */ 1861 uint8_t reserved2d0; /* Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A */ 1862 uint8_t reserved2d1; /* Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A */ 1863 uint8_t reserved2d2; /* Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A */ 1864 uint8_t reserved2d3; /* Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A */ 1865 uint8_t reserved2d4; /* Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A */ 1866 uint8_t reserved2d5; /* Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A */ 1867 uint8_t reserved2d6; /* Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A */ 1868 uint8_t reserved2d7; /* Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A */ 1869 uint8_t reserved2d8; /* Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A */ 1870 uint8_t reserved2d9; /* Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A */ 1871 uint8_t reserved2da; /* Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A */ 1872 uint8_t reserved2db; /* Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A */ 1873 uint8_t reserved2dc; /* Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A */ 1874 uint8_t reserved2dd; /* Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A */ 1875 uint8_t reserved2de; /* Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A */ 1876 uint8_t reserved2df; /* Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A */ 1877 uint8_t reserved2e0; /* Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A */ 1878 uint8_t reserved2e1; /* Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A */ 1879 uint8_t reserved2e2; /* Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A */ 1880 uint8_t reserved2e3; /* Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A */ 1881 uint8_t reserved2e4; /* Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A */ 1882 uint8_t reserved2e5; /* Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A */ 1883 uint8_t reserved2e6; /* Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A */ 1884 uint8_t reserved2e7; /* Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A */ 1885 uint8_t reserved2e8; /* Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A */ 1886 uint8_t reserved2e9; /* Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A */ 1887 uint8_t reserved2ea; /* Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A */ 1888 uint8_t reserved2eb; /* Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A */ 1889 uint8_t reserved2ec; /* Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A */ 1890 uint8_t reserved2ed; /* Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A */ 1891 uint8_t reserved2ee; /* Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A */ 1892 uint8_t reserved2ef; /* Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A */ 1893 uint8_t reserved2f0; /* Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A */ 1894 uint8_t reserved2f1; /* Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A */ 1895 uint8_t reserved2f2; /* Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A */ 1896 uint8_t reserved2f3; /* Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A */ 1897 uint8_t reserved2f4; /* Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A */ 1898 uint8_t reserved2f5; /* Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A */ 1899 uint8_t reserved2f6; /* Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A */ 1900 uint8_t reserved2f7; /* Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A */ 1901 uint8_t reserved2f8; /* Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A */ 1902 uint8_t reserved2f9; /* Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A */ 1903 uint8_t reserved2fa; /* Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A */ 1904 uint8_t reserved2fb; /* Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A */ 1905 uint8_t reserved2fc; /* Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A */ 1906 uint8_t reserved2fd; /* Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A */ 1907 uint8_t reserved2fe; /* Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A */ 1908 uint8_t reserved2ff; /* Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A */ 1909 uint8_t reserved300; /* Byte offset 0x300, CSR Addr 0x54180, Direction=N/A */ 1910 uint8_t reserved301; /* Byte offset 0x301, CSR Addr 0x54180, Direction=N/A */ 1911 uint8_t reserved302; /* Byte offset 0x302, CSR Addr 0x54181, Direction=N/A */ 1912 uint8_t reserved303; /* Byte offset 0x303, CSR Addr 0x54181, Direction=N/A */ 1913 uint8_t reserved304; /* Byte offset 0x304, CSR Addr 0x54182, Direction=N/A */ 1914 uint8_t reserved305; /* Byte offset 0x305, CSR Addr 0x54182, Direction=N/A */ 1915 uint8_t reserved306; /* Byte offset 0x306, CSR Addr 0x54183, Direction=N/A */ 1916 uint8_t reserved307; /* Byte offset 0x307, CSR Addr 0x54183, Direction=N/A */ 1917 uint8_t reserved308; /* Byte offset 0x308, CSR Addr 0x54184, Direction=N/A */ 1918 uint8_t reserved309; /* Byte offset 0x309, CSR Addr 0x54184, Direction=N/A */ 1919 uint8_t reserved30a; /* Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A */ 1920 uint8_t reserved30b; /* Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A */ 1921 uint8_t reserved30c; /* Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A */ 1922 uint8_t reserved30d; /* Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A */ 1923 uint8_t reserved30e; /* Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A */ 1924 uint8_t reserved30f; /* Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A */ 1925 uint8_t reserved310; /* Byte offset 0x310, CSR Addr 0x54188, Direction=N/A */ 1926 uint8_t reserved311; /* Byte offset 0x311, CSR Addr 0x54188, Direction=N/A */ 1927 uint8_t reserved312; /* Byte offset 0x312, CSR Addr 0x54189, Direction=N/A */ 1928 uint8_t reserved313; /* Byte offset 0x313, CSR Addr 0x54189, Direction=N/A */ 1929 uint8_t reserved314; /* Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A */ 1930 uint8_t reserved315; /* Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A */ 1931 uint8_t reserved316; /* Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A */ 1932 uint8_t reserved317; /* Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A */ 1933 uint8_t reserved318; /* Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A */ 1934 uint8_t reserved319; /* Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A */ 1935 uint8_t reserved31a; /* Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A */ 1936 uint8_t reserved31b; /* Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A */ 1937 uint8_t reserved31c; /* Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A */ 1938 uint8_t reserved31d; /* Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A */ 1939 uint8_t reserved31e; /* Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A */ 1940 uint8_t reserved31f; /* Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A */ 1941 uint8_t reserved320; /* Byte offset 0x320, CSR Addr 0x54190, Direction=N/A */ 1942 uint8_t reserved321; /* Byte offset 0x321, CSR Addr 0x54190, Direction=N/A */ 1943 uint8_t reserved322; /* Byte offset 0x322, CSR Addr 0x54191, Direction=N/A */ 1944 uint8_t reserved323; /* Byte offset 0x323, CSR Addr 0x54191, Direction=N/A */ 1945 uint8_t reserved324; /* Byte offset 0x324, CSR Addr 0x54192, Direction=N/A */ 1946 uint8_t reserved325; /* Byte offset 0x325, CSR Addr 0x54192, Direction=N/A */ 1947 uint8_t reserved326; /* Byte offset 0x326, CSR Addr 0x54193, Direction=N/A */ 1948 uint8_t reserved327; /* Byte offset 0x327, CSR Addr 0x54193, Direction=N/A */ 1949 uint8_t reserved328; /* Byte offset 0x328, CSR Addr 0x54194, Direction=N/A */ 1950 uint8_t reserved329; /* Byte offset 0x329, CSR Addr 0x54194, Direction=N/A */ 1951 uint8_t reserved32a; /* Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A */ 1952 uint8_t reserved32b; /* Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A */ 1953 uint8_t reserved32c; /* Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A */ 1954 uint8_t reserved32d; /* Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A */ 1955 uint8_t reserved32e; /* Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A */ 1956 uint8_t reserved32f; /* Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A */ 1957 uint8_t reserved330; /* Byte offset 0x330, CSR Addr 0x54198, Direction=N/A */ 1958 uint8_t reserved331; /* Byte offset 0x331, CSR Addr 0x54198, Direction=N/A */ 1959 uint8_t reserved332; /* Byte offset 0x332, CSR Addr 0x54199, Direction=N/A */ 1960 uint8_t reserved333; /* Byte offset 0x333, CSR Addr 0x54199, Direction=N/A */ 1961 uint8_t reserved334; /* Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A */ 1962 uint8_t reserved335; /* Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A */ 1963 uint8_t reserved336; /* Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A */ 1964 uint8_t reserved337; /* Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A */ 1965 uint8_t reserved338; /* Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A */ 1966 uint8_t reserved339; /* Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A */ 1967 uint8_t reserved33a; /* Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A */ 1968 uint8_t reserved33b; /* Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A */ 1969 uint8_t reserved33c; /* Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A */ 1970 uint8_t reserved33d; /* Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A */ 1971 uint8_t reserved33e; /* Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A */ 1972 uint8_t reserved33f; /* Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A */ 1973 uint8_t reserved340; /* Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A */ 1974 uint8_t reserved341; /* Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A */ 1975 uint8_t reserved342; /* Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A */ 1976 uint8_t reserved343; /* Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A */ 1977 uint8_t reserved344; /* Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A */ 1978 uint8_t reserved345; /* Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A */ 1979 uint8_t reserved346; /* Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A */ 1980 uint8_t reserved347; /* Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A */ 1981 uint8_t reserved348; /* Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A */ 1982 uint8_t reserved349; /* Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A */ 1983 uint8_t reserved34a; /* Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A */ 1984 uint8_t reserved34b; /* Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A */ 1985 uint8_t reserved34c; /* Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A */ 1986 uint8_t reserved34d; /* Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A */ 1987 uint8_t reserved34e; /* Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A */ 1988 uint8_t reserved34f; /* Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A */ 1989 uint8_t reserved350; /* Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A */ 1990 uint8_t reserved351; /* Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A */ 1991 uint8_t reserved352; /* Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A */ 1992 uint8_t reserved353; /* Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A */ 1993 uint8_t reserved354; /* Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A */ 1994 uint8_t reserved355; /* Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A */ 1995 uint8_t reserved356; /* Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A */ 1996 uint8_t reserved357; /* Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A */ 1997 uint8_t reserved358; /* Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A */ 1998 uint8_t reserved359; /* Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A */ 1999 uint8_t reserved35a; /* Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A */ 2000 uint8_t reserved35b; /* Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A */ 2001 uint8_t reserved35c; /* Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A */ 2002 uint8_t reserved35d; /* Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A */ 2003 uint8_t reserved35e; /* Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A */ 2004 uint8_t reserved35f; /* Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A */ 2005 uint8_t reserved360; /* Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A */ 2006 uint8_t reserved361; /* Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A */ 2007 uint8_t reserved362; /* Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A */ 2008 uint8_t reserved363; /* Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A */ 2009 uint8_t reserved364; /* Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A */ 2010 uint8_t reserved365; /* Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A */ 2011 uint8_t reserved366; /* Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A */ 2012 uint8_t reserved367; /* Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A */ 2013 uint8_t reserved368; /* Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A */ 2014 uint8_t reserved369; /* Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A */ 2015 uint8_t reserved36a; /* Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A */ 2016 uint8_t reserved36b; /* Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A */ 2017 uint8_t reserved36c; /* Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A */ 2018 uint8_t reserved36d; /* Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A */ 2019 uint8_t reserved36e; /* Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A */ 2020 uint8_t reserved36f; /* Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A */ 2021 uint8_t reserved370; /* Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A */ 2022 uint8_t reserved371; /* Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A */ 2023 uint8_t reserved372; /* Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A */ 2024 uint8_t reserved373; /* Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A */ 2025 uint8_t reserved374; /* Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A */ 2026 uint8_t reserved375; /* Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A */ 2027 uint8_t reserved376; /* Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A */ 2028 uint8_t reserved377; /* Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A */ 2029 uint8_t reserved378; /* Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A */ 2030 uint8_t reserved379; /* Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A */ 2031 uint8_t reserved37a; /* Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A */ 2032 uint8_t reserved37b; /* Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A */ 2033 uint8_t reserved37c; /* Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A */ 2034 uint8_t reserved37d; /* Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A */ 2035 uint8_t reserved37e; /* Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A */ 2036 uint8_t reserved37f; /* Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A */ 2037 uint8_t reserved380; /* Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A */ 2038 uint8_t reserved381; /* Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A */ 2039 uint8_t reserved382; /* Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A */ 2040 uint8_t reserved383; /* Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A */ 2041 uint8_t reserved384; /* Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A */ 2042 uint8_t reserved385; /* Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A */ 2043 uint8_t reserved386; /* Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A */ 2044 uint8_t reserved387; /* Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A */ 2045 uint8_t reserved388; /* Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A */ 2046 uint8_t reserved389; /* Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A */ 2047 uint8_t reserved38a; /* Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A */ 2048 uint8_t reserved38b; /* Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A */ 2049 uint8_t reserved38c; /* Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A */ 2050 uint8_t reserved38d; /* Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A */ 2051 uint8_t reserved38e; /* Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A */ 2052 uint8_t reserved38f; /* Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A */ 2053 uint8_t reserved390; /* Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A */ 2054 uint8_t reserved391; /* Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A */ 2055 uint8_t reserved392; /* Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A */ 2056 uint8_t reserved393; /* Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A */ 2057 uint8_t reserved394; /* Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A */ 2058 uint8_t reserved395; /* Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A */ 2059 uint8_t reserved396; /* Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A */ 2060 uint8_t reserved397; /* Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A */ 2061 uint8_t reserved398; /* Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A */ 2062 uint8_t reserved399; /* Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A */ 2063 uint8_t reserved39a; /* Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A */ 2064 uint8_t reserved39b; /* Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A */ 2065 uint8_t reserved39c; /* Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A */ 2066 uint8_t reserved39d; /* Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A */ 2067 uint8_t reserved39e; /* Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A */ 2068 uint8_t reserved39f; /* Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A */ 2069 uint8_t reserved3a0; /* Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A */ 2070 uint8_t reserved3a1; /* Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A */ 2071 uint8_t reserved3a2; /* Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A */ 2072 uint8_t reserved3a3; /* Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A */ 2073 uint8_t reserved3a4; /* Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A */ 2074 uint8_t reserved3a5; /* Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A */ 2075 uint8_t reserved3a6; /* Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A */ 2076 uint8_t reserved3a7; /* Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A */ 2077 uint8_t reserved3a8; /* Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A */ 2078 uint8_t reserved3a9; /* Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A */ 2079 uint8_t reserved3aa; /* Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A */ 2080 uint8_t reserved3ab; /* Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A */ 2081 uint8_t reserved3ac; /* Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A */ 2082 uint8_t reserved3ad; /* Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A */ 2083 uint8_t reserved3ae; /* Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A */ 2084 uint8_t reserved3af; /* Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A */ 2085 uint8_t reserved3b0; /* Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A */ 2086 uint8_t reserved3b1; /* Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A */ 2087 uint8_t reserved3b2; /* Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A */ 2088 uint8_t reserved3b3; /* Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A */ 2089 uint8_t reserved3b4; /* Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A */ 2090 uint8_t reserved3b5; /* Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A */ 2091 uint8_t reserved3b6; /* Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A */ 2092 uint8_t reserved3b7; /* Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A */ 2093 uint8_t reserved3b8; /* Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A */ 2094 uint8_t reserved3b9; /* Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A */ 2095 uint8_t reserved3ba; /* Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A */ 2096 uint8_t reserved3bb; /* Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A */ 2097 uint8_t reserved3bc; /* Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A */ 2098 uint8_t reserved3bd; /* Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A */ 2099 uint8_t reserved3be; /* Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A */ 2100 uint8_t reserved3bf; /* Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A */ 2101 uint8_t reserved3c0; /* Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A */ 2102 uint8_t reserved3c1; /* Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A */ 2103 uint8_t reserved3c2; /* Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A */ 2104 uint8_t reserved3c3; /* Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A */ 2105 uint8_t reserved3c4; /* Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A */ 2106 uint8_t reserved3c5; /* Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A */ 2107 uint8_t reserved3c6; /* Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A */ 2108 uint8_t reserved3c7; /* Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A */ 2109 uint8_t reserved3c8; /* Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A */ 2110 uint8_t reserved3c9; /* Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A */ 2111 uint8_t reserved3ca; /* Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A */ 2112 uint8_t reserved3cb; /* Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A */ 2113 uint8_t reserved3cc; /* Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A */ 2114 uint8_t reserved3cd; /* Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A */ 2115 uint8_t reserved3ce; /* Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A */ 2116 uint8_t reserved3cf; /* Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A */ 2117 uint8_t reserved3d0; /* Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A */ 2118 uint8_t reserved3d1; /* Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A */ 2119 uint8_t reserved3d2; /* Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A */ 2120 uint8_t reserved3d3; /* Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A */ 2121 uint8_t reserved3d4; /* Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A */ 2122 uint8_t reserved3d5; /* Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A */ 2123 uint8_t reserved3d6; /* Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A */ 2124 uint8_t reserved3d7; /* Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A */ 2125 uint8_t reserved3d8; /* Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A */ 2126 uint8_t reserved3d9; /* Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A */ 2127 uint8_t reserved3da; /* Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A */ 2128 uint8_t reserved3db; /* Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A */ 2129 uint8_t reserved3dc; /* Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A */ 2130 uint8_t reserved3dd; /* Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A */ 2131 uint8_t reserved3de; /* Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A */ 2132 uint8_t reserved3df; /* Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A */ 2133 uint8_t reserved3e0; /* Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A */ 2134 uint8_t reserved3e1; /* Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A */ 2135 uint8_t reserved3e2; /* Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A */ 2136 uint8_t reserved3e3; /* Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A */ 2137 uint8_t reserved3e4; /* Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A */ 2138 uint8_t reserved3e5; /* Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A */ 2139 uint8_t reserved3e6; /* Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A */ 2140 uint8_t reserved3e7; /* Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A */ 2141 uint8_t reserved3e8; /* Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A */ 2142 uint8_t reserved3e9; /* Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A */ 2143 uint8_t reserved3ea; /* Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A */ 2144 uint8_t reserved3eb; /* Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A */ 2145 uint8_t reserved3ec; /* Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A */ 2146 uint8_t reserved3ed; /* Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A */ 2147 uint8_t reserved3ee; /* Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A */ 2148 uint8_t reserved3ef; /* Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A */ 2149 uint8_t reserved3f0; /* Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A */ 2150 uint8_t reserved3f1; /* Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A */ 2151 uint8_t reserved3f2; /* Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A */ 2152 uint8_t reserved3f3; /* Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A */ 2153 uint8_t reserved3f4; /* Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A */ 2154 uint8_t reserved3f5; /* Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A */ 2155 uint16_t alt_cas_l; /* 2156 * Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in 2157 * This field must be populated if RdDBI is enabled 2158 * (applicable when mr5[A12] == 1). 2159 * RdDBI is dynamically disabled in certain training steps, 2160 * and so the [RdDBI disabled] CAS Latency must be provided 2161 * in this field. 2162 * The required encoding is as follows: 2163 * alt_cas_l[0] == 0: use value in mr0 2164 * alt_cas_l[0] == 1: use value in alt_cas_l, i.e., 2165 * mr0{A[12],A[6],A[5],A[4],A[2]} = alt_cas_l[12,6,5,4,2] 2166 * Other bits are ignored 2167 */ 2168 uint8_t alt_wcas_l; /* 2169 * Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In 2170 * This field must be populated if 2tCK write preambles are 2171 * enabled (applicable when mr4[A12] == 1). 2172 * 2tCK write prambles are dynamically disabled in certain 2173 * training steps, and so the [1tCK write preamble] WCAS 2174 * Latency must be provided in this field. 2175 * The required encoding is as follows: 2176 * alt_wcas_l[0] == 0: use value in mr2 2177 * alt_wcas_l[0] == 1: use value in alt_wcas_l, i.e., 2178 * mr2{A[5],A[4],A[3]} = alt_wcas_l[5,4,3] 2179 * Other bits are ignored 2180 */ 2181 uint8_t d4misc; /* 2182 * Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In 2183 * Contains various options for training DDR4 Devices. 2184 * 2185 * Bit fields: 2186 * 2187 * d4misc[7:5,2,1] RFU, must be zero 2188 * 2189 * d4misc[0] = protect memory reset 2190 * 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to 2191 * devices after training. 2192 * 0x0 = dfi_resert_n can control BP_MEMRESERT_L to 2193 * devices after training 2194 * 2195 * d4misc[3]: reserved 2196 * 2197 * d4misc[4]: DRAM reset mode 2198 * 0x1 = Do not reset DRAM during devinit 2199 * 0x0 = Reset DRAM during devinit 2200 */ 2201 } __packed __aligned(2); 2202 2203 #endif /* MNPMUSRAMMSGBLOCK_DDR4_H */ 2204