1 /* 2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <drivers/delay_timer.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/st/stm32mp_clkfunc.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_clkfunc.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <dt-bindings/clock/stm32mp1-clksrc.h> 26 #include <lib/mmio.h> 27 #include <lib/spinlock.h> 28 #include <lib/utils_def.h> 29 #include <plat/common/platform.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 enum stm32mp1_parent_id { 44 /* Oscillators are defined in enum stm32mp_osc_id */ 45 46 /* Other parent source */ 47 _HSI_KER = NB_OSC, 48 _HSE_KER, 49 _HSE_KER_DIV2, 50 _CSI_KER, 51 _PLL1_P, 52 _PLL1_Q, 53 _PLL1_R, 54 _PLL2_P, 55 _PLL2_Q, 56 _PLL2_R, 57 _PLL3_P, 58 _PLL3_Q, 59 _PLL3_R, 60 _PLL4_P, 61 _PLL4_Q, 62 _PLL4_R, 63 _ACLK, 64 _PCLK1, 65 _PCLK2, 66 _PCLK3, 67 _PCLK4, 68 _PCLK5, 69 _HCLK6, 70 _HCLK2, 71 _CK_PER, 72 _CK_MPU, 73 _CK_MCU, 74 _USB_PHY_48, 75 _PARENT_NB, 76 _UNKNOWN_ID = 0xff, 77 }; 78 79 /* Lists only the parent clock we are interested in */ 80 enum stm32mp1_parent_sel { 81 _I2C12_SEL, 82 _I2C35_SEL, 83 _STGEN_SEL, 84 _I2C46_SEL, 85 _SPI6_SEL, 86 _USART1_SEL, 87 _RNG1_SEL, 88 _UART6_SEL, 89 _UART24_SEL, 90 _UART35_SEL, 91 _UART78_SEL, 92 _SDMMC12_SEL, 93 _SDMMC3_SEL, 94 _QSPI_SEL, 95 _FMC_SEL, 96 _ASS_SEL, 97 _MSS_SEL, 98 _USBPHY_SEL, 99 _USBO_SEL, 100 _PARENT_SEL_NB, 101 _UNKNOWN_SEL = 0xff, 102 }; 103 104 enum stm32mp1_pll_id { 105 _PLL1, 106 _PLL2, 107 _PLL3, 108 _PLL4, 109 _PLL_NB 110 }; 111 112 enum stm32mp1_div_id { 113 _DIV_P, 114 _DIV_Q, 115 _DIV_R, 116 _DIV_NB, 117 }; 118 119 enum stm32mp1_clksrc_id { 120 CLKSRC_MPU, 121 CLKSRC_AXI, 122 CLKSRC_MCU, 123 CLKSRC_PLL12, 124 CLKSRC_PLL3, 125 CLKSRC_PLL4, 126 CLKSRC_RTC, 127 CLKSRC_MCO1, 128 CLKSRC_MCO2, 129 CLKSRC_NB 130 }; 131 132 enum stm32mp1_clkdiv_id { 133 CLKDIV_MPU, 134 CLKDIV_AXI, 135 CLKDIV_MCU, 136 CLKDIV_APB1, 137 CLKDIV_APB2, 138 CLKDIV_APB3, 139 CLKDIV_APB4, 140 CLKDIV_APB5, 141 CLKDIV_RTC, 142 CLKDIV_MCO1, 143 CLKDIV_MCO2, 144 CLKDIV_NB 145 }; 146 147 enum stm32mp1_pllcfg { 148 PLLCFG_M, 149 PLLCFG_N, 150 PLLCFG_P, 151 PLLCFG_Q, 152 PLLCFG_R, 153 PLLCFG_O, 154 PLLCFG_NB 155 }; 156 157 enum stm32mp1_pllcsg { 158 PLLCSG_MOD_PER, 159 PLLCSG_INC_STEP, 160 PLLCSG_SSCG_MODE, 161 PLLCSG_NB 162 }; 163 164 enum stm32mp1_plltype { 165 PLL_800, 166 PLL_1600, 167 PLL_TYPE_NB 168 }; 169 170 struct stm32mp1_pll { 171 uint8_t refclk_min; 172 uint8_t refclk_max; 173 uint8_t divn_max; 174 }; 175 176 struct stm32mp1_clk_gate { 177 uint16_t offset; 178 uint8_t bit; 179 uint8_t index; 180 uint8_t set_clr; 181 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 182 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 183 }; 184 185 struct stm32mp1_clk_sel { 186 uint16_t offset; 187 uint8_t src; 188 uint8_t msk; 189 uint8_t nb_parent; 190 const uint8_t *parent; 191 }; 192 193 #define REFCLK_SIZE 4 194 struct stm32mp1_clk_pll { 195 enum stm32mp1_plltype plltype; 196 uint16_t rckxselr; 197 uint16_t pllxcfgr1; 198 uint16_t pllxcfgr2; 199 uint16_t pllxfracr; 200 uint16_t pllxcr; 201 uint16_t pllxcsgr; 202 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 203 }; 204 205 /* Clocks with selectable source and non set/clr register access */ 206 #define _CLK_SELEC(off, b, idx, s) \ 207 { \ 208 .offset = (off), \ 209 .bit = (b), \ 210 .index = (idx), \ 211 .set_clr = 0, \ 212 .sel = (s), \ 213 .fixed = _UNKNOWN_ID, \ 214 } 215 216 /* Clocks with fixed source and non set/clr register access */ 217 #define _CLK_FIXED(off, b, idx, f) \ 218 { \ 219 .offset = (off), \ 220 .bit = (b), \ 221 .index = (idx), \ 222 .set_clr = 0, \ 223 .sel = _UNKNOWN_SEL, \ 224 .fixed = (f), \ 225 } 226 227 /* Clocks with selectable source and set/clr register access */ 228 #define _CLK_SC_SELEC(off, b, idx, s) \ 229 { \ 230 .offset = (off), \ 231 .bit = (b), \ 232 .index = (idx), \ 233 .set_clr = 1, \ 234 .sel = (s), \ 235 .fixed = _UNKNOWN_ID, \ 236 } 237 238 /* Clocks with fixed source and set/clr register access */ 239 #define _CLK_SC_FIXED(off, b, idx, f) \ 240 { \ 241 .offset = (off), \ 242 .bit = (b), \ 243 .index = (idx), \ 244 .set_clr = 1, \ 245 .sel = _UNKNOWN_SEL, \ 246 .fixed = (f), \ 247 } 248 249 #define _CLK_PARENT(idx, off, s, m, p) \ 250 [(idx)] = { \ 251 .offset = (off), \ 252 .src = (s), \ 253 .msk = (m), \ 254 .parent = (p), \ 255 .nb_parent = ARRAY_SIZE(p) \ 256 } 257 258 #define _CLK_PLL(idx, type, off1, off2, off3, \ 259 off4, off5, off6, \ 260 p1, p2, p3, p4) \ 261 [(idx)] = { \ 262 .plltype = (type), \ 263 .rckxselr = (off1), \ 264 .pllxcfgr1 = (off2), \ 265 .pllxcfgr2 = (off3), \ 266 .pllxfracr = (off4), \ 267 .pllxcr = (off5), \ 268 .pllxcsgr = (off6), \ 269 .refclk[0] = (p1), \ 270 .refclk[1] = (p2), \ 271 .refclk[2] = (p3), \ 272 .refclk[3] = (p4), \ 273 } 274 275 static const uint8_t stm32mp1_clks[][2] = { 276 { CK_PER, _CK_PER }, 277 { CK_MPU, _CK_MPU }, 278 { CK_AXI, _ACLK }, 279 { CK_MCU, _CK_MCU }, 280 { CK_HSE, _HSE }, 281 { CK_CSI, _CSI }, 282 { CK_LSI, _LSI }, 283 { CK_LSE, _LSE }, 284 { CK_HSI, _HSI }, 285 { CK_HSE_DIV2, _HSE_KER_DIV2 }, 286 }; 287 288 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 289 290 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 291 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 292 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 293 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 294 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 295 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 296 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 297 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 298 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 299 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 300 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 301 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 302 303 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 304 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 305 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 306 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 307 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 308 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 309 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 310 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 311 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 312 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 313 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 314 315 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 316 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 317 318 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 319 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 320 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 321 322 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 323 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 324 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 325 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _USART1_SEL), 326 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 327 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 328 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 329 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 330 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 331 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 332 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 333 334 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 335 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 336 337 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 338 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 339 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 340 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 341 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 342 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 343 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 344 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 345 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 346 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 347 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 348 349 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 350 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 351 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 352 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 353 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 354 355 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 356 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 357 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 358 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 359 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 360 361 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 362 }; 363 364 static const uint8_t i2c12_parents[] = { 365 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 366 }; 367 368 static const uint8_t i2c35_parents[] = { 369 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 370 }; 371 372 static const uint8_t stgen_parents[] = { 373 _HSI_KER, _HSE_KER 374 }; 375 376 static const uint8_t i2c46_parents[] = { 377 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 378 }; 379 380 static const uint8_t spi6_parents[] = { 381 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 382 }; 383 384 static const uint8_t usart1_parents[] = { 385 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 386 }; 387 388 static const uint8_t rng1_parents[] = { 389 _CSI, _PLL4_R, _LSE, _LSI 390 }; 391 392 static const uint8_t uart6_parents[] = { 393 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 394 }; 395 396 static const uint8_t uart234578_parents[] = { 397 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 398 }; 399 400 static const uint8_t sdmmc12_parents[] = { 401 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 402 }; 403 404 static const uint8_t sdmmc3_parents[] = { 405 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 406 }; 407 408 static const uint8_t qspi_parents[] = { 409 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 410 }; 411 412 static const uint8_t fmc_parents[] = { 413 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 414 }; 415 416 static const uint8_t ass_parents[] = { 417 _HSI, _HSE, _PLL2 418 }; 419 420 static const uint8_t mss_parents[] = { 421 _HSI, _HSE, _CSI, _PLL3 422 }; 423 424 static const uint8_t usbphy_parents[] = { 425 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 426 }; 427 428 static const uint8_t usbo_parents[] = { 429 _PLL4_R, _USB_PHY_48 430 }; 431 432 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 433 _CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), 434 _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 435 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 436 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 437 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 438 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 439 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 440 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 441 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 442 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 443 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 444 _CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, sdmmc12_parents), 445 _CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, sdmmc3_parents), 446 _CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 447 _CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 448 _CLK_PARENT(_ASS_SEL, RCC_ASSCKSELR, 0, 0x3, ass_parents), 449 _CLK_PARENT(_MSS_SEL, RCC_MSSCKSELR, 0, 0x3, mss_parents), 450 _CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 451 _CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 452 }; 453 454 /* Define characteristic of PLL according type */ 455 #define DIVN_MIN 24 456 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 457 [PLL_800] = { 458 .refclk_min = 4, 459 .refclk_max = 16, 460 .divn_max = 99, 461 }, 462 [PLL_1600] = { 463 .refclk_min = 8, 464 .refclk_max = 16, 465 .divn_max = 199, 466 }, 467 }; 468 469 /* PLLNCFGR2 register divider by output */ 470 static const uint8_t pllncfgr2[_DIV_NB] = { 471 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 472 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 473 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 474 }; 475 476 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 477 _CLK_PLL(_PLL1, PLL_1600, 478 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 479 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 480 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 481 _CLK_PLL(_PLL2, PLL_1600, 482 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 483 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 484 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 485 _CLK_PLL(_PLL3, PLL_800, 486 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 487 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 488 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 489 _CLK_PLL(_PLL4, PLL_800, 490 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 491 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 492 _HSI, _HSE, _CSI, _I2S_CKIN), 493 }; 494 495 /* Prescaler table lookups for clock computation */ 496 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 497 static const uint8_t stm32mp1_mcu_div[16] = { 498 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 499 }; 500 501 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 502 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 503 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 504 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 505 0, 1, 2, 3, 4, 4, 4, 4 506 }; 507 508 /* div = /1 /2 /3 /4 */ 509 static const uint8_t stm32mp1_axi_div[8] = { 510 1, 2, 3, 4, 4, 4, 4, 4 511 }; 512 513 /* RCC clock device driver private */ 514 static unsigned long stm32mp1_osc[NB_OSC]; 515 static struct spinlock reg_lock; 516 static unsigned int gate_refcounts[NB_GATES]; 517 static struct spinlock refcount_lock; 518 519 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 520 { 521 return &stm32mp1_clk_gate[idx]; 522 } 523 524 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 525 { 526 return &stm32mp1_clk_sel[idx]; 527 } 528 529 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 530 { 531 return &stm32mp1_clk_pll[idx]; 532 } 533 534 static int stm32mp1_lock_available(void) 535 { 536 /* The spinlocks are used only when MMU is enabled */ 537 return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT); 538 } 539 540 static void stm32mp1_clk_lock(struct spinlock *lock) 541 { 542 if (stm32mp1_lock_available() == 0U) { 543 return; 544 } 545 546 /* Assume interrupts are masked */ 547 spin_lock(lock); 548 } 549 550 static void stm32mp1_clk_unlock(struct spinlock *lock) 551 { 552 if (stm32mp1_lock_available() == 0U) { 553 return; 554 } 555 556 spin_unlock(lock); 557 } 558 559 bool stm32mp1_rcc_is_secure(void) 560 { 561 uintptr_t rcc_base = stm32mp_rcc_base(); 562 563 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; 564 } 565 566 bool stm32mp1_rcc_is_mckprot(void) 567 { 568 uintptr_t rcc_base = stm32mp_rcc_base(); 569 570 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; 571 } 572 573 void stm32mp1_clk_rcc_regs_lock(void) 574 { 575 stm32mp1_clk_lock(®_lock); 576 } 577 578 void stm32mp1_clk_rcc_regs_unlock(void) 579 { 580 stm32mp1_clk_unlock(®_lock); 581 } 582 583 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 584 { 585 if (idx >= NB_OSC) { 586 return 0; 587 } 588 589 return stm32mp1_osc[idx]; 590 } 591 592 static int stm32mp1_clk_get_gated_id(unsigned long id) 593 { 594 unsigned int i; 595 596 for (i = 0U; i < NB_GATES; i++) { 597 if (gate_ref(i)->index == id) { 598 return i; 599 } 600 } 601 602 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 603 604 return -EINVAL; 605 } 606 607 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 608 { 609 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 610 } 611 612 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 613 { 614 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 615 } 616 617 static int stm32mp1_clk_get_parent(unsigned long id) 618 { 619 const struct stm32mp1_clk_sel *sel; 620 uint32_t j, p_sel; 621 int i; 622 enum stm32mp1_parent_id p; 623 enum stm32mp1_parent_sel s; 624 uintptr_t rcc_base = stm32mp_rcc_base(); 625 626 for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) { 627 if (stm32mp1_clks[j][0] == id) { 628 return (int)stm32mp1_clks[j][1]; 629 } 630 } 631 632 i = stm32mp1_clk_get_gated_id(id); 633 if (i < 0) { 634 panic(); 635 } 636 637 p = stm32mp1_clk_get_fixed_parent(i); 638 if (p < _PARENT_NB) { 639 return (int)p; 640 } 641 642 s = stm32mp1_clk_get_sel(i); 643 if (s == _UNKNOWN_SEL) { 644 return -EINVAL; 645 } 646 if (s >= _PARENT_SEL_NB) { 647 panic(); 648 } 649 650 sel = clk_sel_ref(s); 651 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & sel->msk; 652 if (p_sel < sel->nb_parent) { 653 return (int)sel->parent[p_sel]; 654 } 655 656 return -EINVAL; 657 } 658 659 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 660 { 661 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 662 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 663 664 return stm32mp1_clk_get_fixed(pll->refclk[src]); 665 } 666 667 /* 668 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 669 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 670 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 671 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 672 */ 673 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 674 { 675 unsigned long refclk, fvco; 676 uint32_t cfgr1, fracr, divm, divn; 677 uintptr_t rcc_base = stm32mp_rcc_base(); 678 679 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 680 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 681 682 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 683 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 684 685 refclk = stm32mp1_pll_get_fref(pll); 686 687 /* 688 * With FRACV : 689 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 690 * Without FRACV 691 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 692 */ 693 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 694 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 695 RCC_PLLNFRACR_FRACV_SHIFT; 696 unsigned long long numerator, denominator; 697 698 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 699 numerator = refclk * numerator; 700 denominator = ((unsigned long long)divm + 1U) << 13; 701 fvco = (unsigned long)(numerator / denominator); 702 } else { 703 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 704 } 705 706 return fvco; 707 } 708 709 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 710 enum stm32mp1_div_id div_id) 711 { 712 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 713 unsigned long dfout; 714 uint32_t cfgr2, divy; 715 716 if (div_id >= _DIV_NB) { 717 return 0; 718 } 719 720 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 721 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 722 723 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 724 725 return dfout; 726 } 727 728 static unsigned long get_clock_rate(int p) 729 { 730 uint32_t reg, clkdiv; 731 unsigned long clock = 0; 732 uintptr_t rcc_base = stm32mp_rcc_base(); 733 734 switch (p) { 735 case _CK_MPU: 736 /* MPU sub system */ 737 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 738 switch (reg & RCC_SELR_SRC_MASK) { 739 case RCC_MPCKSELR_HSI: 740 clock = stm32mp1_clk_get_fixed(_HSI); 741 break; 742 case RCC_MPCKSELR_HSE: 743 clock = stm32mp1_clk_get_fixed(_HSE); 744 break; 745 case RCC_MPCKSELR_PLL: 746 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 747 break; 748 case RCC_MPCKSELR_PLL_MPUDIV: 749 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 750 751 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 752 clkdiv = reg & RCC_MPUDIV_MASK; 753 if (clkdiv != 0U) { 754 clock /= stm32mp1_mpu_div[clkdiv]; 755 } 756 break; 757 default: 758 break; 759 } 760 break; 761 /* AXI sub system */ 762 case _ACLK: 763 case _HCLK2: 764 case _HCLK6: 765 case _PCLK4: 766 case _PCLK5: 767 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 768 switch (reg & RCC_SELR_SRC_MASK) { 769 case RCC_ASSCKSELR_HSI: 770 clock = stm32mp1_clk_get_fixed(_HSI); 771 break; 772 case RCC_ASSCKSELR_HSE: 773 clock = stm32mp1_clk_get_fixed(_HSE); 774 break; 775 case RCC_ASSCKSELR_PLL: 776 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 777 break; 778 default: 779 break; 780 } 781 782 /* System clock divider */ 783 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 784 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 785 786 switch (p) { 787 case _PCLK4: 788 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 789 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 790 break; 791 case _PCLK5: 792 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 793 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 794 break; 795 default: 796 break; 797 } 798 break; 799 /* MCU sub system */ 800 case _CK_MCU: 801 case _PCLK1: 802 case _PCLK2: 803 case _PCLK3: 804 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 805 switch (reg & RCC_SELR_SRC_MASK) { 806 case RCC_MSSCKSELR_HSI: 807 clock = stm32mp1_clk_get_fixed(_HSI); 808 break; 809 case RCC_MSSCKSELR_HSE: 810 clock = stm32mp1_clk_get_fixed(_HSE); 811 break; 812 case RCC_MSSCKSELR_CSI: 813 clock = stm32mp1_clk_get_fixed(_CSI); 814 break; 815 case RCC_MSSCKSELR_PLL: 816 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 817 break; 818 default: 819 break; 820 } 821 822 /* MCU clock divider */ 823 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 824 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 825 826 switch (p) { 827 case _PCLK1: 828 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 829 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 830 break; 831 case _PCLK2: 832 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 833 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 834 break; 835 case _PCLK3: 836 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 837 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 838 break; 839 case _CK_MCU: 840 default: 841 break; 842 } 843 break; 844 case _CK_PER: 845 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 846 switch (reg & RCC_SELR_SRC_MASK) { 847 case RCC_CPERCKSELR_HSI: 848 clock = stm32mp1_clk_get_fixed(_HSI); 849 break; 850 case RCC_CPERCKSELR_HSE: 851 clock = stm32mp1_clk_get_fixed(_HSE); 852 break; 853 case RCC_CPERCKSELR_CSI: 854 clock = stm32mp1_clk_get_fixed(_CSI); 855 break; 856 default: 857 break; 858 } 859 break; 860 case _HSI: 861 case _HSI_KER: 862 clock = stm32mp1_clk_get_fixed(_HSI); 863 break; 864 case _CSI: 865 case _CSI_KER: 866 clock = stm32mp1_clk_get_fixed(_CSI); 867 break; 868 case _HSE: 869 case _HSE_KER: 870 clock = stm32mp1_clk_get_fixed(_HSE); 871 break; 872 case _HSE_KER_DIV2: 873 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 874 break; 875 case _LSI: 876 clock = stm32mp1_clk_get_fixed(_LSI); 877 break; 878 case _LSE: 879 clock = stm32mp1_clk_get_fixed(_LSE); 880 break; 881 /* PLL */ 882 case _PLL1_P: 883 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 884 break; 885 case _PLL1_Q: 886 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 887 break; 888 case _PLL1_R: 889 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 890 break; 891 case _PLL2_P: 892 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 893 break; 894 case _PLL2_Q: 895 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 896 break; 897 case _PLL2_R: 898 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 899 break; 900 case _PLL3_P: 901 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 902 break; 903 case _PLL3_Q: 904 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 905 break; 906 case _PLL3_R: 907 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 908 break; 909 case _PLL4_P: 910 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 911 break; 912 case _PLL4_Q: 913 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 914 break; 915 case _PLL4_R: 916 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 917 break; 918 /* Other */ 919 case _USB_PHY_48: 920 clock = USB_PHY_48_MHZ; 921 break; 922 default: 923 break; 924 } 925 926 return clock; 927 } 928 929 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 930 { 931 uintptr_t rcc_base = stm32mp_rcc_base(); 932 933 if (gate->set_clr != 0U) { 934 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 935 } else { 936 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 937 } 938 939 VERBOSE("Clock %d has been enabled", gate->index); 940 } 941 942 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 943 { 944 uintptr_t rcc_base = stm32mp_rcc_base(); 945 946 if (gate->set_clr != 0U) { 947 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 948 BIT(gate->bit)); 949 } else { 950 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 951 } 952 953 VERBOSE("Clock %d has been disabled", gate->index); 954 } 955 956 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 957 { 958 uintptr_t rcc_base = stm32mp_rcc_base(); 959 960 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 961 } 962 963 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 964 { 965 int i = stm32mp1_clk_get_gated_id(id); 966 967 if (i < 0) { 968 panic(); 969 } 970 971 return gate_refcounts[i]; 972 } 973 974 void __stm32mp1_clk_enable(unsigned long id, bool secure) 975 { 976 const struct stm32mp1_clk_gate *gate; 977 int i = stm32mp1_clk_get_gated_id(id); 978 unsigned int *refcnt; 979 980 if (i < 0) { 981 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 982 panic(); 983 } 984 985 gate = gate_ref(i); 986 refcnt = &gate_refcounts[i]; 987 988 stm32mp1_clk_lock(&refcount_lock); 989 990 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 991 __clk_enable(gate); 992 } 993 994 stm32mp1_clk_unlock(&refcount_lock); 995 } 996 997 void __stm32mp1_clk_disable(unsigned long id, bool secure) 998 { 999 const struct stm32mp1_clk_gate *gate; 1000 int i = stm32mp1_clk_get_gated_id(id); 1001 unsigned int *refcnt; 1002 1003 if (i < 0) { 1004 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1005 panic(); 1006 } 1007 1008 gate = gate_ref(i); 1009 refcnt = &gate_refcounts[i]; 1010 1011 stm32mp1_clk_lock(&refcount_lock); 1012 1013 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1014 __clk_disable(gate); 1015 } 1016 1017 stm32mp1_clk_unlock(&refcount_lock); 1018 } 1019 1020 void stm32mp_clk_enable(unsigned long id) 1021 { 1022 __stm32mp1_clk_enable(id, true); 1023 } 1024 1025 void stm32mp_clk_disable(unsigned long id) 1026 { 1027 __stm32mp1_clk_disable(id, true); 1028 } 1029 1030 bool stm32mp_clk_is_enabled(unsigned long id) 1031 { 1032 int i = stm32mp1_clk_get_gated_id(id); 1033 1034 if (i < 0) { 1035 panic(); 1036 } 1037 1038 return __clk_is_enabled(gate_ref(i)); 1039 } 1040 1041 unsigned long stm32mp_clk_get_rate(unsigned long id) 1042 { 1043 int p = stm32mp1_clk_get_parent(id); 1044 1045 if (p < 0) { 1046 return 0; 1047 } 1048 1049 return get_clock_rate(p); 1050 } 1051 1052 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1053 { 1054 uintptr_t address = stm32mp_rcc_base() + offset; 1055 1056 if (enable) { 1057 mmio_setbits_32(address, mask_on); 1058 } else { 1059 mmio_clrbits_32(address, mask_on); 1060 } 1061 } 1062 1063 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1064 { 1065 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1066 uintptr_t address = stm32mp_rcc_base() + offset; 1067 1068 mmio_write_32(address, mask_on); 1069 } 1070 1071 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1072 { 1073 uint64_t timeout; 1074 uint32_t mask_test; 1075 uintptr_t address = stm32mp_rcc_base() + offset; 1076 1077 if (enable) { 1078 mask_test = mask_rdy; 1079 } else { 1080 mask_test = 0; 1081 } 1082 1083 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1084 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1085 if (timeout_elapsed(timeout)) { 1086 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1087 mask_rdy, address, enable, mmio_read_32(address)); 1088 return -ETIMEDOUT; 1089 } 1090 } 1091 1092 return 0; 1093 } 1094 1095 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1096 { 1097 uint32_t value; 1098 uintptr_t rcc_base = stm32mp_rcc_base(); 1099 1100 if (digbyp) { 1101 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1102 } 1103 1104 if (bypass || digbyp) { 1105 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1106 } 1107 1108 /* 1109 * Warning: not recommended to switch directly from "high drive" 1110 * to "medium low drive", and vice-versa. 1111 */ 1112 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1113 RCC_BDCR_LSEDRV_SHIFT; 1114 1115 while (value != lsedrv) { 1116 if (value > lsedrv) { 1117 value--; 1118 } else { 1119 value++; 1120 } 1121 1122 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1123 RCC_BDCR_LSEDRV_MASK, 1124 value << RCC_BDCR_LSEDRV_SHIFT); 1125 } 1126 1127 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1128 } 1129 1130 static void stm32mp1_lse_wait(void) 1131 { 1132 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1133 VERBOSE("%s: failed\n", __func__); 1134 } 1135 } 1136 1137 static void stm32mp1_lsi_set(bool enable) 1138 { 1139 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1140 1141 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1142 VERBOSE("%s: failed\n", __func__); 1143 } 1144 } 1145 1146 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1147 { 1148 uintptr_t rcc_base = stm32mp_rcc_base(); 1149 1150 if (digbyp) { 1151 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1152 } 1153 1154 if (bypass || digbyp) { 1155 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1156 } 1157 1158 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1159 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1160 VERBOSE("%s: failed\n", __func__); 1161 } 1162 1163 if (css) { 1164 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1165 } 1166 } 1167 1168 static void stm32mp1_csi_set(bool enable) 1169 { 1170 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1171 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1172 VERBOSE("%s: failed\n", __func__); 1173 } 1174 } 1175 1176 static void stm32mp1_hsi_set(bool enable) 1177 { 1178 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1179 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1180 VERBOSE("%s: failed\n", __func__); 1181 } 1182 } 1183 1184 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1185 { 1186 uint64_t timeout; 1187 uintptr_t rcc_base = stm32mp_rcc_base(); 1188 uintptr_t address = rcc_base + RCC_OCRDYR; 1189 1190 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1191 RCC_HSICFGR_HSIDIV_MASK, 1192 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1193 1194 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1195 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1196 if (timeout_elapsed(timeout)) { 1197 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1198 address, mmio_read_32(address)); 1199 return -ETIMEDOUT; 1200 } 1201 } 1202 1203 return 0; 1204 } 1205 1206 static int stm32mp1_hsidiv(unsigned long hsifreq) 1207 { 1208 uint8_t hsidiv; 1209 uint32_t hsidivfreq = MAX_HSI_HZ; 1210 1211 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1212 if (hsidivfreq == hsifreq) { 1213 break; 1214 } 1215 1216 hsidivfreq /= 2U; 1217 } 1218 1219 if (hsidiv == 4U) { 1220 ERROR("Invalid clk-hsi frequency\n"); 1221 return -1; 1222 } 1223 1224 if (hsidiv != 0U) { 1225 return stm32mp1_set_hsidiv(hsidiv); 1226 } 1227 1228 return 0; 1229 } 1230 1231 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1232 unsigned int clksrc, 1233 uint32_t *pllcfg, int plloff) 1234 { 1235 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1236 uintptr_t rcc_base = stm32mp_rcc_base(); 1237 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1238 enum stm32mp1_plltype type = pll->plltype; 1239 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1240 unsigned long refclk; 1241 uint32_t ifrge = 0U; 1242 uint32_t src, value, fracv; 1243 1244 /* Check PLL output */ 1245 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1246 return false; 1247 } 1248 1249 /* Check current clksrc */ 1250 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1251 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1252 return false; 1253 } 1254 1255 /* Check Div */ 1256 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1257 1258 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1259 (pllcfg[PLLCFG_M] + 1U); 1260 1261 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1262 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1263 return false; 1264 } 1265 1266 if ((type == PLL_800) && (refclk >= 8000000U)) { 1267 ifrge = 1U; 1268 } 1269 1270 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1271 RCC_PLLNCFGR1_DIVN_MASK; 1272 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1273 RCC_PLLNCFGR1_DIVM_MASK; 1274 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1275 RCC_PLLNCFGR1_IFRGE_MASK; 1276 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1277 return false; 1278 } 1279 1280 /* Fractional configuration */ 1281 fracv = fdt_read_uint32_default(plloff, "frac", 0); 1282 1283 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1284 value |= RCC_PLLNFRACR_FRACLE; 1285 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1286 return false; 1287 } 1288 1289 /* Output config */ 1290 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1291 RCC_PLLNCFGR2_DIVP_MASK; 1292 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1293 RCC_PLLNCFGR2_DIVQ_MASK; 1294 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1295 RCC_PLLNCFGR2_DIVR_MASK; 1296 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1297 return false; 1298 } 1299 1300 return true; 1301 } 1302 1303 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1304 { 1305 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1306 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1307 1308 mmio_write_32(pllxcr, RCC_PLLNCR_PLLON); 1309 } 1310 1311 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1312 { 1313 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1314 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1315 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1316 1317 /* Wait PLL lock */ 1318 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1319 if (timeout_elapsed(timeout)) { 1320 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1321 pll_id, pllxcr, mmio_read_32(pllxcr)); 1322 return -ETIMEDOUT; 1323 } 1324 } 1325 1326 /* Start the requested output */ 1327 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1328 1329 return 0; 1330 } 1331 1332 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1333 { 1334 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1335 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1336 uint64_t timeout; 1337 1338 /* Stop all output */ 1339 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1340 RCC_PLLNCR_DIVREN); 1341 1342 /* Stop PLL */ 1343 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1344 1345 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1346 /* Wait PLL stopped */ 1347 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1348 if (timeout_elapsed(timeout)) { 1349 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1350 pll_id, pllxcr, mmio_read_32(pllxcr)); 1351 return -ETIMEDOUT; 1352 } 1353 } 1354 1355 return 0; 1356 } 1357 1358 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1359 uint32_t *pllcfg) 1360 { 1361 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1362 uintptr_t rcc_base = stm32mp_rcc_base(); 1363 uint32_t value; 1364 1365 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1366 RCC_PLLNCFGR2_DIVP_MASK; 1367 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1368 RCC_PLLNCFGR2_DIVQ_MASK; 1369 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1370 RCC_PLLNCFGR2_DIVR_MASK; 1371 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1372 } 1373 1374 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1375 uint32_t *pllcfg, uint32_t fracv) 1376 { 1377 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1378 uintptr_t rcc_base = stm32mp_rcc_base(); 1379 enum stm32mp1_plltype type = pll->plltype; 1380 unsigned long refclk; 1381 uint32_t ifrge = 0; 1382 uint32_t src, value; 1383 1384 src = mmio_read_32(rcc_base + pll->rckxselr) & 1385 RCC_SELR_REFCLK_SRC_MASK; 1386 1387 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1388 (pllcfg[PLLCFG_M] + 1U); 1389 1390 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1391 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1392 return -EINVAL; 1393 } 1394 1395 if ((type == PLL_800) && (refclk >= 8000000U)) { 1396 ifrge = 1U; 1397 } 1398 1399 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1400 RCC_PLLNCFGR1_DIVN_MASK; 1401 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1402 RCC_PLLNCFGR1_DIVM_MASK; 1403 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1404 RCC_PLLNCFGR1_IFRGE_MASK; 1405 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1406 1407 /* Fractional configuration */ 1408 value = 0; 1409 mmio_write_32(rcc_base + pll->pllxfracr, value); 1410 1411 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1412 mmio_write_32(rcc_base + pll->pllxfracr, value); 1413 1414 value |= RCC_PLLNFRACR_FRACLE; 1415 mmio_write_32(rcc_base + pll->pllxfracr, value); 1416 1417 stm32mp1_pll_config_output(pll_id, pllcfg); 1418 1419 return 0; 1420 } 1421 1422 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1423 { 1424 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1425 uint32_t pllxcsg = 0; 1426 1427 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1428 RCC_PLLNCSGR_MOD_PER_MASK; 1429 1430 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1431 RCC_PLLNCSGR_INC_STEP_MASK; 1432 1433 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1434 RCC_PLLNCSGR_SSCG_MODE_MASK; 1435 1436 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1437 } 1438 1439 static int stm32mp1_set_clksrc(unsigned int clksrc) 1440 { 1441 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1442 uint64_t timeout; 1443 1444 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1445 clksrc & RCC_SELR_SRC_MASK); 1446 1447 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1448 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1449 if (timeout_elapsed(timeout)) { 1450 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1451 clksrc_address, mmio_read_32(clksrc_address)); 1452 return -ETIMEDOUT; 1453 } 1454 } 1455 1456 return 0; 1457 } 1458 1459 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1460 { 1461 uint64_t timeout; 1462 1463 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1464 clkdiv & RCC_DIVR_DIV_MASK); 1465 1466 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1467 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1468 if (timeout_elapsed(timeout)) { 1469 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1470 clkdiv, address, mmio_read_32(address)); 1471 return -ETIMEDOUT; 1472 } 1473 } 1474 1475 return 0; 1476 } 1477 1478 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1479 { 1480 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1481 1482 /* 1483 * Binding clksrc : 1484 * bit15-4 offset 1485 * bit3: disable 1486 * bit2-0: MCOSEL[2:0] 1487 */ 1488 if ((clksrc & 0x8U) != 0U) { 1489 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1490 } else { 1491 mmio_clrsetbits_32(clksrc_address, 1492 RCC_MCOCFG_MCOSRC_MASK, 1493 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1494 mmio_clrsetbits_32(clksrc_address, 1495 RCC_MCOCFG_MCODIV_MASK, 1496 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1497 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1498 } 1499 } 1500 1501 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1502 { 1503 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1504 1505 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1506 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1507 mmio_clrsetbits_32(address, 1508 RCC_BDCR_RTCSRC_MASK, 1509 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1510 1511 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1512 } 1513 1514 if (lse_css) { 1515 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1516 } 1517 } 1518 1519 #define CNTCVL_OFF 0x008 1520 #define CNTCVU_OFF 0x00C 1521 1522 static void stm32mp1_stgen_config(void) 1523 { 1524 uintptr_t stgen; 1525 uint32_t cntfid0; 1526 unsigned long rate; 1527 unsigned long long counter; 1528 1529 stgen = fdt_get_stgen_base(); 1530 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1531 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1532 1533 if (cntfid0 == rate) { 1534 return; 1535 } 1536 1537 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1538 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); 1539 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; 1540 counter = (counter * rate / cntfid0); 1541 1542 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1543 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1544 mmio_write_32(stgen + CNTFID_OFF, rate); 1545 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1546 1547 write_cntfrq((u_register_t)rate); 1548 1549 /* Need to update timer with new frequency */ 1550 generic_delay_timer_init(); 1551 } 1552 1553 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1554 { 1555 uintptr_t stgen; 1556 unsigned long long cnt; 1557 1558 stgen = fdt_get_stgen_base(); 1559 1560 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1561 mmio_read_32(stgen + CNTCVL_OFF); 1562 1563 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1564 1565 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1566 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1567 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1568 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1569 } 1570 1571 static void stm32mp1_pkcs_config(uint32_t pkcs) 1572 { 1573 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1574 uint32_t value = pkcs & 0xFU; 1575 uint32_t mask = 0xFU; 1576 1577 if ((pkcs & BIT(31)) != 0U) { 1578 mask <<= 4; 1579 value <<= 4; 1580 } 1581 1582 mmio_clrsetbits_32(address, mask, value); 1583 } 1584 1585 int stm32mp1_clk_init(void) 1586 { 1587 uintptr_t rcc_base = stm32mp_rcc_base(); 1588 unsigned int clksrc[CLKSRC_NB]; 1589 unsigned int clkdiv[CLKDIV_NB]; 1590 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1591 int plloff[_PLL_NB]; 1592 int ret, len; 1593 enum stm32mp1_pll_id i; 1594 bool lse_css = false; 1595 bool pll3_preserve = false; 1596 bool pll4_preserve = false; 1597 bool pll4_bootrom = false; 1598 const fdt32_t *pkcs_cell; 1599 1600 /* Check status field to disable security */ 1601 if (!fdt_get_rcc_secure_status()) { 1602 mmio_write_32(rcc_base + RCC_TZCR, 0); 1603 } 1604 1605 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, 1606 (uint32_t)CLKSRC_NB); 1607 if (ret < 0) { 1608 return -FDT_ERR_NOTFOUND; 1609 } 1610 1611 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, 1612 (uint32_t)CLKDIV_NB); 1613 if (ret < 0) { 1614 return -FDT_ERR_NOTFOUND; 1615 } 1616 1617 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1618 char name[12]; 1619 1620 snprintf(name, sizeof(name), "st,pll@%d", i); 1621 plloff[i] = fdt_rcc_subnode_offset(name); 1622 1623 if (!fdt_check_node(plloff[i])) { 1624 continue; 1625 } 1626 1627 ret = fdt_read_uint32_array(plloff[i], "cfg", 1628 pllcfg[i], (int)PLLCFG_NB); 1629 if (ret < 0) { 1630 return -FDT_ERR_NOTFOUND; 1631 } 1632 } 1633 1634 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1635 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1636 1637 /* 1638 * Switch ON oscillator found in device-tree. 1639 * Note: HSI already ON after BootROM stage. 1640 */ 1641 if (stm32mp1_osc[_LSI] != 0U) { 1642 stm32mp1_lsi_set(true); 1643 } 1644 if (stm32mp1_osc[_LSE] != 0U) { 1645 bool bypass, digbyp; 1646 uint32_t lsedrv; 1647 1648 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1649 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1650 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1651 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1652 LSEDRV_MEDIUM_HIGH); 1653 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1654 } 1655 if (stm32mp1_osc[_HSE] != 0U) { 1656 bool bypass, digbyp, css; 1657 1658 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1659 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1660 css = fdt_osc_read_bool(_HSE, "st,css"); 1661 stm32mp1_hse_enable(bypass, digbyp, css); 1662 } 1663 /* 1664 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1665 * => switch on CSI even if node is not present in device tree 1666 */ 1667 stm32mp1_csi_set(true); 1668 1669 /* Come back to HSI */ 1670 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1671 if (ret != 0) { 1672 return ret; 1673 } 1674 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1675 if (ret != 0) { 1676 return ret; 1677 } 1678 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1679 if (ret != 0) { 1680 return ret; 1681 } 1682 1683 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1684 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1685 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1686 clksrc[CLKSRC_PLL3], 1687 pllcfg[_PLL3], 1688 plloff[_PLL3]); 1689 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1690 clksrc[CLKSRC_PLL4], 1691 pllcfg[_PLL4], 1692 plloff[_PLL4]); 1693 } 1694 1695 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1696 if (((i == _PLL3) && pll3_preserve) || 1697 ((i == _PLL4) && pll4_preserve)) { 1698 continue; 1699 } 1700 1701 ret = stm32mp1_pll_stop(i); 1702 if (ret != 0) { 1703 return ret; 1704 } 1705 } 1706 1707 /* Configure HSIDIV */ 1708 if (stm32mp1_osc[_HSI] != 0U) { 1709 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1710 if (ret != 0) { 1711 return ret; 1712 } 1713 stm32mp1_stgen_config(); 1714 } 1715 1716 /* Select DIV */ 1717 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1718 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1719 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1720 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1721 if (ret != 0) { 1722 return ret; 1723 } 1724 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1725 if (ret != 0) { 1726 return ret; 1727 } 1728 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1729 if (ret != 0) { 1730 return ret; 1731 } 1732 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1733 if (ret != 0) { 1734 return ret; 1735 } 1736 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1737 if (ret != 0) { 1738 return ret; 1739 } 1740 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1741 if (ret != 0) { 1742 return ret; 1743 } 1744 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1745 if (ret != 0) { 1746 return ret; 1747 } 1748 1749 /* No ready bit for RTC */ 1750 mmio_write_32(rcc_base + RCC_RTCDIVR, 1751 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1752 1753 /* Configure PLLs source */ 1754 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1755 if (ret != 0) { 1756 return ret; 1757 } 1758 1759 if (!pll3_preserve) { 1760 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1761 if (ret != 0) { 1762 return ret; 1763 } 1764 } 1765 1766 if (!pll4_preserve) { 1767 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1768 if (ret != 0) { 1769 return ret; 1770 } 1771 } 1772 1773 /* Configure and start PLLs */ 1774 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1775 uint32_t fracv; 1776 uint32_t csg[PLLCSG_NB]; 1777 1778 if (((i == _PLL3) && pll3_preserve) || 1779 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1780 continue; 1781 } 1782 1783 if (!fdt_check_node(plloff[i])) { 1784 continue; 1785 } 1786 1787 if ((i == _PLL4) && pll4_bootrom) { 1788 /* Set output divider if not done by the Bootrom */ 1789 stm32mp1_pll_config_output(i, pllcfg[i]); 1790 continue; 1791 } 1792 1793 fracv = fdt_read_uint32_default(plloff[i], "frac", 0); 1794 1795 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1796 if (ret != 0) { 1797 return ret; 1798 } 1799 ret = fdt_read_uint32_array(plloff[i], "csg", csg, 1800 (uint32_t)PLLCSG_NB); 1801 if (ret == 0) { 1802 stm32mp1_pll_csg(i, csg); 1803 } else if (ret != -FDT_ERR_NOTFOUND) { 1804 return ret; 1805 } 1806 1807 stm32mp1_pll_start(i); 1808 } 1809 /* Wait and start PLLs ouptut when ready */ 1810 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1811 if (!fdt_check_node(plloff[i])) { 1812 continue; 1813 } 1814 1815 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1816 if (ret != 0) { 1817 return ret; 1818 } 1819 } 1820 /* Wait LSE ready before to use it */ 1821 if (stm32mp1_osc[_LSE] != 0U) { 1822 stm32mp1_lse_wait(); 1823 } 1824 1825 /* Configure with expected clock source */ 1826 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1827 if (ret != 0) { 1828 return ret; 1829 } 1830 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1831 if (ret != 0) { 1832 return ret; 1833 } 1834 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1835 if (ret != 0) { 1836 return ret; 1837 } 1838 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1839 1840 /* Configure PKCK */ 1841 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1842 if (pkcs_cell != NULL) { 1843 bool ckper_disabled = false; 1844 uint32_t j; 1845 1846 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1847 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1848 1849 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1850 ckper_disabled = true; 1851 continue; 1852 } 1853 stm32mp1_pkcs_config(pkcs); 1854 } 1855 1856 /* 1857 * CKPER is source for some peripheral clocks 1858 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1859 * only if previous clock is still ON 1860 * => deactivated CKPER only after switching clock 1861 */ 1862 if (ckper_disabled) { 1863 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 1864 } 1865 } 1866 1867 /* Switch OFF HSI if not found in device-tree */ 1868 if (stm32mp1_osc[_HSI] == 0U) { 1869 stm32mp1_hsi_set(false); 1870 } 1871 stm32mp1_stgen_config(); 1872 1873 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1874 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 1875 RCC_DDRITFCR_DDRCKMOD_MASK, 1876 RCC_DDRITFCR_DDRCKMOD_SSR << 1877 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1878 1879 return 0; 1880 } 1881 1882 static void stm32mp1_osc_clk_init(const char *name, 1883 enum stm32mp_osc_id index) 1884 { 1885 uint32_t frequency; 1886 1887 if (fdt_osc_read_freq(name, &frequency) == 0) { 1888 stm32mp1_osc[index] = frequency; 1889 } 1890 } 1891 1892 static void stm32mp1_osc_init(void) 1893 { 1894 enum stm32mp_osc_id i; 1895 1896 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1897 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 1898 } 1899 } 1900 1901 int stm32mp1_clk_probe(void) 1902 { 1903 stm32mp1_osc_init(); 1904 1905 return 0; 1906 } 1907