1 /* 2 * Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <drivers/st/stm32mp1_rcc.h> 21 #include <dt-bindings/clock/stm32mp1-clksrc.h> 22 #include <lib/mmio.h> 23 #include <lib/spinlock.h> 24 #include <lib/utils_def.h> 25 #include <libfdt.h> 26 #include <plat/common/platform.h> 27 28 #include <platform_def.h> 29 30 #define MAX_HSI_HZ 64000000 31 #define USB_PHY_48_MHZ 48000000 32 33 #define TIMEOUT_US_200MS U(200000) 34 #define TIMEOUT_US_1S U(1000000) 35 36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 41 42 const char *stm32mp_osc_node_label[NB_OSC] = { 43 [_LSI] = "clk-lsi", 44 [_LSE] = "clk-lse", 45 [_HSI] = "clk-hsi", 46 [_HSE] = "clk-hse", 47 [_CSI] = "clk-csi", 48 [_I2S_CKIN] = "i2s_ckin", 49 }; 50 51 enum stm32mp1_parent_id { 52 /* Oscillators are defined in enum stm32mp_osc_id */ 53 54 /* Other parent source */ 55 _HSI_KER = NB_OSC, 56 _HSE_KER, 57 _HSE_KER_DIV2, 58 _HSE_RTC, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _MPU_SEL, 110 _CKPER_SEL, 111 _RTC_SEL, 112 _PARENT_SEL_NB, 113 _UNKNOWN_SEL = 0xff, 114 }; 115 116 /* State the parent clock ID straight related to a clock */ 117 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 118 [_HSE] = CK_HSE, 119 [_HSI] = CK_HSI, 120 [_CSI] = CK_CSI, 121 [_LSE] = CK_LSE, 122 [_LSI] = CK_LSI, 123 [_I2S_CKIN] = _UNKNOWN_ID, 124 [_USB_PHY_48] = _UNKNOWN_ID, 125 [_HSI_KER] = CK_HSI, 126 [_HSE_KER] = CK_HSE, 127 [_HSE_KER_DIV2] = CK_HSE_DIV2, 128 [_HSE_RTC] = _UNKNOWN_ID, 129 [_CSI_KER] = CK_CSI, 130 [_PLL1_P] = PLL1_P, 131 [_PLL1_Q] = PLL1_Q, 132 [_PLL1_R] = PLL1_R, 133 [_PLL2_P] = PLL2_P, 134 [_PLL2_Q] = PLL2_Q, 135 [_PLL2_R] = PLL2_R, 136 [_PLL3_P] = PLL3_P, 137 [_PLL3_Q] = PLL3_Q, 138 [_PLL3_R] = PLL3_R, 139 [_PLL4_P] = PLL4_P, 140 [_PLL4_Q] = PLL4_Q, 141 [_PLL4_R] = PLL4_R, 142 [_ACLK] = CK_AXI, 143 [_PCLK1] = CK_AXI, 144 [_PCLK2] = CK_AXI, 145 [_PCLK3] = CK_AXI, 146 [_PCLK4] = CK_AXI, 147 [_PCLK5] = CK_AXI, 148 [_CK_PER] = CK_PER, 149 [_CK_MPU] = CK_MPU, 150 [_CK_MCU] = CK_MCU, 151 }; 152 153 static unsigned int clock_id2parent_id(unsigned long id) 154 { 155 unsigned int n; 156 157 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 158 if (parent_id_clock_id[n] == id) { 159 return n; 160 } 161 } 162 163 return _UNKNOWN_ID; 164 } 165 166 enum stm32mp1_pll_id { 167 _PLL1, 168 _PLL2, 169 _PLL3, 170 _PLL4, 171 _PLL_NB 172 }; 173 174 enum stm32mp1_div_id { 175 _DIV_P, 176 _DIV_Q, 177 _DIV_R, 178 _DIV_NB, 179 }; 180 181 enum stm32mp1_clksrc_id { 182 CLKSRC_MPU, 183 CLKSRC_AXI, 184 CLKSRC_MCU, 185 CLKSRC_PLL12, 186 CLKSRC_PLL3, 187 CLKSRC_PLL4, 188 CLKSRC_RTC, 189 CLKSRC_MCO1, 190 CLKSRC_MCO2, 191 CLKSRC_NB 192 }; 193 194 enum stm32mp1_clkdiv_id { 195 CLKDIV_MPU, 196 CLKDIV_AXI, 197 CLKDIV_MCU, 198 CLKDIV_APB1, 199 CLKDIV_APB2, 200 CLKDIV_APB3, 201 CLKDIV_APB4, 202 CLKDIV_APB5, 203 CLKDIV_RTC, 204 CLKDIV_MCO1, 205 CLKDIV_MCO2, 206 CLKDIV_NB 207 }; 208 209 enum stm32mp1_pllcfg { 210 PLLCFG_M, 211 PLLCFG_N, 212 PLLCFG_P, 213 PLLCFG_Q, 214 PLLCFG_R, 215 PLLCFG_O, 216 PLLCFG_NB 217 }; 218 219 enum stm32mp1_pllcsg { 220 PLLCSG_MOD_PER, 221 PLLCSG_INC_STEP, 222 PLLCSG_SSCG_MODE, 223 PLLCSG_NB 224 }; 225 226 enum stm32mp1_plltype { 227 PLL_800, 228 PLL_1600, 229 PLL_TYPE_NB 230 }; 231 232 struct stm32mp1_pll { 233 uint8_t refclk_min; 234 uint8_t refclk_max; 235 }; 236 237 struct stm32mp1_clk_gate { 238 uint16_t offset; 239 uint8_t bit; 240 uint8_t index; 241 uint8_t set_clr; 242 uint8_t secure; 243 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 244 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 245 }; 246 247 struct stm32mp1_clk_sel { 248 uint16_t offset; 249 uint8_t src; 250 uint8_t msk; 251 uint8_t nb_parent; 252 const uint8_t *parent; 253 }; 254 255 #define REFCLK_SIZE 4 256 struct stm32mp1_clk_pll { 257 enum stm32mp1_plltype plltype; 258 uint16_t rckxselr; 259 uint16_t pllxcfgr1; 260 uint16_t pllxcfgr2; 261 uint16_t pllxfracr; 262 uint16_t pllxcr; 263 uint16_t pllxcsgr; 264 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 265 }; 266 267 /* Clocks with selectable source and non set/clr register access */ 268 #define _CLK_SELEC(sec, off, b, idx, s) \ 269 { \ 270 .offset = (off), \ 271 .bit = (b), \ 272 .index = (idx), \ 273 .set_clr = 0, \ 274 .secure = (sec), \ 275 .sel = (s), \ 276 .fixed = _UNKNOWN_ID, \ 277 } 278 279 /* Clocks with fixed source and non set/clr register access */ 280 #define _CLK_FIXED(sec, off, b, idx, f) \ 281 { \ 282 .offset = (off), \ 283 .bit = (b), \ 284 .index = (idx), \ 285 .set_clr = 0, \ 286 .secure = (sec), \ 287 .sel = _UNKNOWN_SEL, \ 288 .fixed = (f), \ 289 } 290 291 /* Clocks with selectable source and set/clr register access */ 292 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 293 { \ 294 .offset = (off), \ 295 .bit = (b), \ 296 .index = (idx), \ 297 .set_clr = 1, \ 298 .secure = (sec), \ 299 .sel = (s), \ 300 .fixed = _UNKNOWN_ID, \ 301 } 302 303 /* Clocks with fixed source and set/clr register access */ 304 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 305 { \ 306 .offset = (off), \ 307 .bit = (b), \ 308 .index = (idx), \ 309 .set_clr = 1, \ 310 .secure = (sec), \ 311 .sel = _UNKNOWN_SEL, \ 312 .fixed = (f), \ 313 } 314 315 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 316 [_ ## _label ## _SEL] = { \ 317 .offset = _rcc_selr, \ 318 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 319 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 320 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 321 .parent = (_parents), \ 322 .nb_parent = ARRAY_SIZE(_parents) \ 323 } 324 325 #define _CLK_PLL(idx, type, off1, off2, off3, \ 326 off4, off5, off6, \ 327 p1, p2, p3, p4) \ 328 [(idx)] = { \ 329 .plltype = (type), \ 330 .rckxselr = (off1), \ 331 .pllxcfgr1 = (off2), \ 332 .pllxcfgr2 = (off3), \ 333 .pllxfracr = (off4), \ 334 .pllxcr = (off5), \ 335 .pllxcsgr = (off6), \ 336 .refclk[0] = (p1), \ 337 .refclk[1] = (p2), \ 338 .refclk[2] = (p3), \ 339 .refclk[3] = (p4), \ 340 } 341 342 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 343 344 #define SEC 1 345 #define N_S 0 346 347 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 357 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 358 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 359 360 #if defined(IMAGE_BL32) 361 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 362 #endif 363 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 373 374 #if defined(IMAGE_BL32) 375 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 376 #endif 377 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 378 379 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 380 381 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 382 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 383 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 384 385 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 387 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 388 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 389 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 393 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 394 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 395 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 396 397 #if defined(IMAGE_BL32) 398 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 399 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 400 #endif 401 402 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 409 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 410 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 411 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 412 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 413 414 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 415 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 416 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 417 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 418 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 419 420 #if defined(IMAGE_BL2) 421 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 422 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 423 #endif 424 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 425 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 426 #if defined(IMAGE_BL32) 427 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 428 #endif 429 430 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 431 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 432 }; 433 434 static const uint8_t i2c12_parents[] = { 435 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 436 }; 437 438 static const uint8_t i2c35_parents[] = { 439 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 440 }; 441 442 static const uint8_t stgen_parents[] = { 443 _HSI_KER, _HSE_KER 444 }; 445 446 static const uint8_t i2c46_parents[] = { 447 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 448 }; 449 450 static const uint8_t spi6_parents[] = { 451 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 452 }; 453 454 static const uint8_t usart1_parents[] = { 455 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 456 }; 457 458 static const uint8_t rng1_parents[] = { 459 _CSI, _PLL4_R, _LSE, _LSI 460 }; 461 462 static const uint8_t uart6_parents[] = { 463 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 464 }; 465 466 static const uint8_t uart234578_parents[] = { 467 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 468 }; 469 470 static const uint8_t sdmmc12_parents[] = { 471 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 472 }; 473 474 static const uint8_t sdmmc3_parents[] = { 475 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 476 }; 477 478 static const uint8_t qspi_parents[] = { 479 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 480 }; 481 482 static const uint8_t fmc_parents[] = { 483 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 484 }; 485 486 static const uint8_t axiss_parents[] = { 487 _HSI, _HSE, _PLL2_P 488 }; 489 490 static const uint8_t mcuss_parents[] = { 491 _HSI, _HSE, _CSI, _PLL3_P 492 }; 493 494 static const uint8_t usbphy_parents[] = { 495 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 496 }; 497 498 static const uint8_t usbo_parents[] = { 499 _PLL4_R, _USB_PHY_48 500 }; 501 502 static const uint8_t mpu_parents[] = { 503 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 504 }; 505 506 static const uint8_t per_parents[] = { 507 _HSI, _HSE, _CSI, 508 }; 509 510 static const uint8_t rtc_parents[] = { 511 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 512 }; 513 514 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 515 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 516 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 517 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 518 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 519 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 520 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 521 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 522 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 523 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 524 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 525 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 526 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 527 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 528 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 529 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 530 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 531 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 532 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 533 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 534 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 535 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 536 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 537 }; 538 539 /* Define characteristic of PLL according type */ 540 #define DIVN_MIN 24 541 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 542 [PLL_800] = { 543 .refclk_min = 4, 544 .refclk_max = 16, 545 }, 546 [PLL_1600] = { 547 .refclk_min = 8, 548 .refclk_max = 16, 549 }, 550 }; 551 552 /* PLLNCFGR2 register divider by output */ 553 static const uint8_t pllncfgr2[_DIV_NB] = { 554 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 555 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 556 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 557 }; 558 559 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 560 _CLK_PLL(_PLL1, PLL_1600, 561 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 562 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 563 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 564 _CLK_PLL(_PLL2, PLL_1600, 565 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 566 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 567 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 568 _CLK_PLL(_PLL3, PLL_800, 569 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 570 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 571 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 572 _CLK_PLL(_PLL4, PLL_800, 573 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 574 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 575 _HSI, _HSE, _CSI, _I2S_CKIN), 576 }; 577 578 /* Prescaler table lookups for clock computation */ 579 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 580 static const uint8_t stm32mp1_mcu_div[16] = { 581 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 582 }; 583 584 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 585 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 586 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 587 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 588 0, 1, 2, 3, 4, 4, 4, 4 589 }; 590 591 /* div = /1 /2 /3 /4 */ 592 static const uint8_t stm32mp1_axi_div[8] = { 593 1, 2, 3, 4, 4, 4, 4, 4 594 }; 595 596 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 597 [_HSI] = "HSI", 598 [_HSE] = "HSE", 599 [_CSI] = "CSI", 600 [_LSI] = "LSI", 601 [_LSE] = "LSE", 602 [_I2S_CKIN] = "I2S_CKIN", 603 [_HSI_KER] = "HSI_KER", 604 [_HSE_KER] = "HSE_KER", 605 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 606 [_HSE_RTC] = "HSE_RTC", 607 [_CSI_KER] = "CSI_KER", 608 [_PLL1_P] = "PLL1_P", 609 [_PLL1_Q] = "PLL1_Q", 610 [_PLL1_R] = "PLL1_R", 611 [_PLL2_P] = "PLL2_P", 612 [_PLL2_Q] = "PLL2_Q", 613 [_PLL2_R] = "PLL2_R", 614 [_PLL3_P] = "PLL3_P", 615 [_PLL3_Q] = "PLL3_Q", 616 [_PLL3_R] = "PLL3_R", 617 [_PLL4_P] = "PLL4_P", 618 [_PLL4_Q] = "PLL4_Q", 619 [_PLL4_R] = "PLL4_R", 620 [_ACLK] = "ACLK", 621 [_PCLK1] = "PCLK1", 622 [_PCLK2] = "PCLK2", 623 [_PCLK3] = "PCLK3", 624 [_PCLK4] = "PCLK4", 625 [_PCLK5] = "PCLK5", 626 [_HCLK6] = "KCLK6", 627 [_HCLK2] = "HCLK2", 628 [_CK_PER] = "CK_PER", 629 [_CK_MPU] = "CK_MPU", 630 [_CK_MCU] = "CK_MCU", 631 [_USB_PHY_48] = "USB_PHY_48", 632 }; 633 634 /* RCC clock device driver private */ 635 static unsigned long stm32mp1_osc[NB_OSC]; 636 static struct spinlock reg_lock; 637 static unsigned int gate_refcounts[NB_GATES]; 638 static struct spinlock refcount_lock; 639 640 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 641 { 642 return &stm32mp1_clk_gate[idx]; 643 } 644 645 #if defined(IMAGE_BL32) 646 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 647 { 648 return gate->secure == N_S; 649 } 650 #endif 651 652 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 653 { 654 return &stm32mp1_clk_sel[idx]; 655 } 656 657 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 658 { 659 return &stm32mp1_clk_pll[idx]; 660 } 661 662 static void stm32mp1_clk_lock(struct spinlock *lock) 663 { 664 if (stm32mp_lock_available()) { 665 /* Assume interrupts are masked */ 666 spin_lock(lock); 667 } 668 } 669 670 static void stm32mp1_clk_unlock(struct spinlock *lock) 671 { 672 if (stm32mp_lock_available()) { 673 spin_unlock(lock); 674 } 675 } 676 677 bool stm32mp1_rcc_is_secure(void) 678 { 679 uintptr_t rcc_base = stm32mp_rcc_base(); 680 uint32_t mask = RCC_TZCR_TZEN; 681 682 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 683 } 684 685 bool stm32mp1_rcc_is_mckprot(void) 686 { 687 uintptr_t rcc_base = stm32mp_rcc_base(); 688 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 689 690 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 691 } 692 693 void stm32mp1_clk_rcc_regs_lock(void) 694 { 695 stm32mp1_clk_lock(®_lock); 696 } 697 698 void stm32mp1_clk_rcc_regs_unlock(void) 699 { 700 stm32mp1_clk_unlock(®_lock); 701 } 702 703 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 704 { 705 if (idx >= NB_OSC) { 706 return 0; 707 } 708 709 return stm32mp1_osc[idx]; 710 } 711 712 static int stm32mp1_clk_get_gated_id(unsigned long id) 713 { 714 unsigned int i; 715 716 for (i = 0U; i < NB_GATES; i++) { 717 if (gate_ref(i)->index == id) { 718 return i; 719 } 720 } 721 722 ERROR("%s: clk id %lu not found\n", __func__, id); 723 724 return -EINVAL; 725 } 726 727 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 728 { 729 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 730 } 731 732 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 733 { 734 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 735 } 736 737 static int stm32mp1_clk_get_parent(unsigned long id) 738 { 739 const struct stm32mp1_clk_sel *sel; 740 uint32_t p_sel; 741 int i; 742 enum stm32mp1_parent_id p; 743 enum stm32mp1_parent_sel s; 744 uintptr_t rcc_base = stm32mp_rcc_base(); 745 746 /* Few non gateable clock have a static parent ID, find them */ 747 i = (int)clock_id2parent_id(id); 748 if (i != _UNKNOWN_ID) { 749 return i; 750 } 751 752 i = stm32mp1_clk_get_gated_id(id); 753 if (i < 0) { 754 panic(); 755 } 756 757 p = stm32mp1_clk_get_fixed_parent(i); 758 if (p < _PARENT_NB) { 759 return (int)p; 760 } 761 762 s = stm32mp1_clk_get_sel(i); 763 if (s == _UNKNOWN_SEL) { 764 return -EINVAL; 765 } 766 if (s >= _PARENT_SEL_NB) { 767 panic(); 768 } 769 770 sel = clk_sel_ref(s); 771 p_sel = (mmio_read_32(rcc_base + sel->offset) & 772 (sel->msk << sel->src)) >> sel->src; 773 if (p_sel < sel->nb_parent) { 774 return (int)sel->parent[p_sel]; 775 } 776 777 return -EINVAL; 778 } 779 780 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 781 { 782 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 783 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 784 785 return stm32mp1_clk_get_fixed(pll->refclk[src]); 786 } 787 788 /* 789 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 790 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 791 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 792 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 793 */ 794 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 795 { 796 unsigned long refclk, fvco; 797 uint32_t cfgr1, fracr, divm, divn; 798 uintptr_t rcc_base = stm32mp_rcc_base(); 799 800 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 801 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 802 803 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 804 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 805 806 refclk = stm32mp1_pll_get_fref(pll); 807 808 /* 809 * With FRACV : 810 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 811 * Without FRACV 812 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 813 */ 814 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 815 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 816 RCC_PLLNFRACR_FRACV_SHIFT; 817 unsigned long long numerator, denominator; 818 819 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 820 numerator = refclk * numerator; 821 denominator = ((unsigned long long)divm + 1U) << 13; 822 fvco = (unsigned long)(numerator / denominator); 823 } else { 824 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 825 } 826 827 return fvco; 828 } 829 830 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 831 enum stm32mp1_div_id div_id) 832 { 833 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 834 unsigned long dfout; 835 uint32_t cfgr2, divy; 836 837 if (div_id >= _DIV_NB) { 838 return 0; 839 } 840 841 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 842 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 843 844 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 845 846 return dfout; 847 } 848 849 static unsigned long get_clock_rate(int p) 850 { 851 uint32_t reg, clkdiv; 852 unsigned long clock = 0; 853 uintptr_t rcc_base = stm32mp_rcc_base(); 854 855 switch (p) { 856 case _CK_MPU: 857 /* MPU sub system */ 858 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 859 switch (reg & RCC_SELR_SRC_MASK) { 860 case RCC_MPCKSELR_HSI: 861 clock = stm32mp1_clk_get_fixed(_HSI); 862 break; 863 case RCC_MPCKSELR_HSE: 864 clock = stm32mp1_clk_get_fixed(_HSE); 865 break; 866 case RCC_MPCKSELR_PLL: 867 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 868 break; 869 case RCC_MPCKSELR_PLL_MPUDIV: 870 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 871 872 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 873 clkdiv = reg & RCC_MPUDIV_MASK; 874 clock >>= stm32mp1_mpu_div[clkdiv]; 875 break; 876 default: 877 break; 878 } 879 break; 880 /* AXI sub system */ 881 case _ACLK: 882 case _HCLK2: 883 case _HCLK6: 884 case _PCLK4: 885 case _PCLK5: 886 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 887 switch (reg & RCC_SELR_SRC_MASK) { 888 case RCC_ASSCKSELR_HSI: 889 clock = stm32mp1_clk_get_fixed(_HSI); 890 break; 891 case RCC_ASSCKSELR_HSE: 892 clock = stm32mp1_clk_get_fixed(_HSE); 893 break; 894 case RCC_ASSCKSELR_PLL: 895 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 896 break; 897 default: 898 break; 899 } 900 901 /* System clock divider */ 902 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 903 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 904 905 switch (p) { 906 case _PCLK4: 907 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 908 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 909 break; 910 case _PCLK5: 911 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 912 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 913 break; 914 default: 915 break; 916 } 917 break; 918 /* MCU sub system */ 919 case _CK_MCU: 920 case _PCLK1: 921 case _PCLK2: 922 case _PCLK3: 923 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 924 switch (reg & RCC_SELR_SRC_MASK) { 925 case RCC_MSSCKSELR_HSI: 926 clock = stm32mp1_clk_get_fixed(_HSI); 927 break; 928 case RCC_MSSCKSELR_HSE: 929 clock = stm32mp1_clk_get_fixed(_HSE); 930 break; 931 case RCC_MSSCKSELR_CSI: 932 clock = stm32mp1_clk_get_fixed(_CSI); 933 break; 934 case RCC_MSSCKSELR_PLL: 935 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 936 break; 937 default: 938 break; 939 } 940 941 /* MCU clock divider */ 942 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 943 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 944 945 switch (p) { 946 case _PCLK1: 947 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 948 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 949 break; 950 case _PCLK2: 951 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 952 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 953 break; 954 case _PCLK3: 955 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 956 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 957 break; 958 case _CK_MCU: 959 default: 960 break; 961 } 962 break; 963 case _CK_PER: 964 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 965 switch (reg & RCC_SELR_SRC_MASK) { 966 case RCC_CPERCKSELR_HSI: 967 clock = stm32mp1_clk_get_fixed(_HSI); 968 break; 969 case RCC_CPERCKSELR_HSE: 970 clock = stm32mp1_clk_get_fixed(_HSE); 971 break; 972 case RCC_CPERCKSELR_CSI: 973 clock = stm32mp1_clk_get_fixed(_CSI); 974 break; 975 default: 976 break; 977 } 978 break; 979 case _HSI: 980 case _HSI_KER: 981 clock = stm32mp1_clk_get_fixed(_HSI); 982 break; 983 case _CSI: 984 case _CSI_KER: 985 clock = stm32mp1_clk_get_fixed(_CSI); 986 break; 987 case _HSE: 988 case _HSE_KER: 989 clock = stm32mp1_clk_get_fixed(_HSE); 990 break; 991 case _HSE_KER_DIV2: 992 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 993 break; 994 case _HSE_RTC: 995 clock = stm32mp1_clk_get_fixed(_HSE); 996 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 997 break; 998 case _LSI: 999 clock = stm32mp1_clk_get_fixed(_LSI); 1000 break; 1001 case _LSE: 1002 clock = stm32mp1_clk_get_fixed(_LSE); 1003 break; 1004 /* PLL */ 1005 case _PLL1_P: 1006 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1007 break; 1008 case _PLL1_Q: 1009 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1010 break; 1011 case _PLL1_R: 1012 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1013 break; 1014 case _PLL2_P: 1015 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1016 break; 1017 case _PLL2_Q: 1018 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1019 break; 1020 case _PLL2_R: 1021 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1022 break; 1023 case _PLL3_P: 1024 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1025 break; 1026 case _PLL3_Q: 1027 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1028 break; 1029 case _PLL3_R: 1030 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1031 break; 1032 case _PLL4_P: 1033 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1034 break; 1035 case _PLL4_Q: 1036 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1037 break; 1038 case _PLL4_R: 1039 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1040 break; 1041 /* Other */ 1042 case _USB_PHY_48: 1043 clock = USB_PHY_48_MHZ; 1044 break; 1045 default: 1046 break; 1047 } 1048 1049 return clock; 1050 } 1051 1052 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1053 { 1054 uintptr_t rcc_base = stm32mp_rcc_base(); 1055 1056 VERBOSE("Enable clock %u\n", gate->index); 1057 1058 if (gate->set_clr != 0U) { 1059 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1060 } else { 1061 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1062 } 1063 } 1064 1065 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1066 { 1067 uintptr_t rcc_base = stm32mp_rcc_base(); 1068 1069 VERBOSE("Disable clock %u\n", gate->index); 1070 1071 if (gate->set_clr != 0U) { 1072 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1073 BIT(gate->bit)); 1074 } else { 1075 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1076 } 1077 } 1078 1079 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1080 { 1081 uintptr_t rcc_base = stm32mp_rcc_base(); 1082 1083 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1084 } 1085 1086 /* Oscillators and PLLs are not gated at runtime */ 1087 static bool clock_is_always_on(unsigned long id) 1088 { 1089 switch (id) { 1090 case CK_HSE: 1091 case CK_CSI: 1092 case CK_LSI: 1093 case CK_LSE: 1094 case CK_HSI: 1095 case CK_HSE_DIV2: 1096 case PLL1_Q: 1097 case PLL1_R: 1098 case PLL2_P: 1099 case PLL2_Q: 1100 case PLL2_R: 1101 case PLL3_P: 1102 case PLL3_Q: 1103 case PLL3_R: 1104 case CK_AXI: 1105 case CK_MPU: 1106 case CK_MCU: 1107 case RTC: 1108 return true; 1109 default: 1110 return false; 1111 } 1112 } 1113 1114 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1115 { 1116 const struct stm32mp1_clk_gate *gate; 1117 int i; 1118 1119 if (clock_is_always_on(id)) { 1120 return; 1121 } 1122 1123 i = stm32mp1_clk_get_gated_id(id); 1124 if (i < 0) { 1125 ERROR("Clock %lu can't be enabled\n", id); 1126 panic(); 1127 } 1128 1129 gate = gate_ref(i); 1130 1131 if (!with_refcnt) { 1132 __clk_enable(gate); 1133 return; 1134 } 1135 1136 #if defined(IMAGE_BL32) 1137 if (gate_is_non_secure(gate)) { 1138 /* Enable non-secure clock w/o any refcounting */ 1139 __clk_enable(gate); 1140 return; 1141 } 1142 #endif 1143 1144 stm32mp1_clk_lock(&refcount_lock); 1145 1146 if (gate_refcounts[i] == 0U) { 1147 __clk_enable(gate); 1148 } 1149 1150 gate_refcounts[i]++; 1151 if (gate_refcounts[i] == UINT_MAX) { 1152 ERROR("Clock %lu refcount reached max value\n", id); 1153 panic(); 1154 } 1155 1156 stm32mp1_clk_unlock(&refcount_lock); 1157 } 1158 1159 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1160 { 1161 const struct stm32mp1_clk_gate *gate; 1162 int i; 1163 1164 if (clock_is_always_on(id)) { 1165 return; 1166 } 1167 1168 i = stm32mp1_clk_get_gated_id(id); 1169 if (i < 0) { 1170 ERROR("Clock %lu can't be disabled\n", id); 1171 panic(); 1172 } 1173 1174 gate = gate_ref(i); 1175 1176 if (!with_refcnt) { 1177 __clk_disable(gate); 1178 return; 1179 } 1180 1181 #if defined(IMAGE_BL32) 1182 if (gate_is_non_secure(gate)) { 1183 /* Don't disable non-secure clocks */ 1184 return; 1185 } 1186 #endif 1187 1188 stm32mp1_clk_lock(&refcount_lock); 1189 1190 if (gate_refcounts[i] == 0U) { 1191 ERROR("Clock %lu refcount reached 0\n", id); 1192 panic(); 1193 } 1194 gate_refcounts[i]--; 1195 1196 if (gate_refcounts[i] == 0U) { 1197 __clk_disable(gate); 1198 } 1199 1200 stm32mp1_clk_unlock(&refcount_lock); 1201 } 1202 1203 static int stm32mp_clk_enable(unsigned long id) 1204 { 1205 __stm32mp1_clk_enable(id, true); 1206 1207 return 0; 1208 } 1209 1210 static void stm32mp_clk_disable(unsigned long id) 1211 { 1212 __stm32mp1_clk_disable(id, true); 1213 } 1214 1215 static bool stm32mp_clk_is_enabled(unsigned long id) 1216 { 1217 int i; 1218 1219 if (clock_is_always_on(id)) { 1220 return true; 1221 } 1222 1223 i = stm32mp1_clk_get_gated_id(id); 1224 if (i < 0) { 1225 panic(); 1226 } 1227 1228 return __clk_is_enabled(gate_ref(i)); 1229 } 1230 1231 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1232 { 1233 uintptr_t rcc_base = stm32mp_rcc_base(); 1234 int p = stm32mp1_clk_get_parent(id); 1235 uint32_t prescaler, timpre; 1236 unsigned long parent_rate; 1237 1238 if (p < 0) { 1239 return 0; 1240 } 1241 1242 parent_rate = get_clock_rate(p); 1243 1244 switch (id) { 1245 case TIM2_K: 1246 case TIM3_K: 1247 case TIM4_K: 1248 case TIM5_K: 1249 case TIM6_K: 1250 case TIM7_K: 1251 case TIM12_K: 1252 case TIM13_K: 1253 case TIM14_K: 1254 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1255 RCC_APBXDIV_MASK; 1256 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1257 RCC_TIMGXPRER_TIMGXPRE; 1258 break; 1259 1260 case TIM1_K: 1261 case TIM8_K: 1262 case TIM15_K: 1263 case TIM16_K: 1264 case TIM17_K: 1265 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1266 RCC_APBXDIV_MASK; 1267 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1268 RCC_TIMGXPRER_TIMGXPRE; 1269 break; 1270 1271 default: 1272 return parent_rate; 1273 } 1274 1275 if (prescaler == 0U) { 1276 return parent_rate; 1277 } 1278 1279 return parent_rate * (timpre + 1U) * 2U; 1280 } 1281 1282 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1283 { 1284 uintptr_t address = stm32mp_rcc_base() + offset; 1285 1286 if (enable) { 1287 mmio_setbits_32(address, mask_on); 1288 } else { 1289 mmio_clrbits_32(address, mask_on); 1290 } 1291 } 1292 1293 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1294 { 1295 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1296 uintptr_t address = stm32mp_rcc_base() + offset; 1297 1298 mmio_write_32(address, mask_on); 1299 } 1300 1301 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1302 { 1303 uint64_t timeout; 1304 uint32_t mask_test; 1305 uintptr_t address = stm32mp_rcc_base() + offset; 1306 1307 if (enable) { 1308 mask_test = mask_rdy; 1309 } else { 1310 mask_test = 0; 1311 } 1312 1313 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1314 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1315 if (timeout_elapsed(timeout)) { 1316 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1317 mask_rdy, address, enable, mmio_read_32(address)); 1318 return -ETIMEDOUT; 1319 } 1320 } 1321 1322 return 0; 1323 } 1324 1325 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1326 { 1327 uint32_t value; 1328 uintptr_t rcc_base = stm32mp_rcc_base(); 1329 1330 /* Do not reconfigure LSE if it is already ON */ 1331 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { 1332 return; 1333 } 1334 1335 if (digbyp) { 1336 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1337 } 1338 1339 if (bypass || digbyp) { 1340 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1341 } 1342 1343 /* 1344 * Warning: not recommended to switch directly from "high drive" 1345 * to "medium low drive", and vice-versa. 1346 */ 1347 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1348 RCC_BDCR_LSEDRV_SHIFT; 1349 1350 while (value != lsedrv) { 1351 if (value > lsedrv) { 1352 value--; 1353 } else { 1354 value++; 1355 } 1356 1357 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1358 RCC_BDCR_LSEDRV_MASK, 1359 value << RCC_BDCR_LSEDRV_SHIFT); 1360 } 1361 1362 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1363 } 1364 1365 static void stm32mp1_lse_wait(void) 1366 { 1367 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1368 VERBOSE("%s: failed\n", __func__); 1369 } 1370 } 1371 1372 static void stm32mp1_lsi_set(bool enable) 1373 { 1374 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1375 1376 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1377 VERBOSE("%s: failed\n", __func__); 1378 } 1379 } 1380 1381 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1382 { 1383 uintptr_t rcc_base = stm32mp_rcc_base(); 1384 1385 if (digbyp) { 1386 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1387 } 1388 1389 if (bypass || digbyp) { 1390 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1391 } 1392 1393 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1394 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1395 VERBOSE("%s: failed\n", __func__); 1396 } 1397 1398 if (css) { 1399 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1400 } 1401 1402 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1403 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1404 (!(digbyp || bypass))) { 1405 panic(); 1406 } 1407 #endif 1408 } 1409 1410 static void stm32mp1_csi_set(bool enable) 1411 { 1412 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1413 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1414 VERBOSE("%s: failed\n", __func__); 1415 } 1416 } 1417 1418 static void stm32mp1_hsi_set(bool enable) 1419 { 1420 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1421 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1422 VERBOSE("%s: failed\n", __func__); 1423 } 1424 } 1425 1426 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1427 { 1428 uint64_t timeout; 1429 uintptr_t rcc_base = stm32mp_rcc_base(); 1430 uintptr_t address = rcc_base + RCC_OCRDYR; 1431 1432 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1433 RCC_HSICFGR_HSIDIV_MASK, 1434 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1435 1436 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1437 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1438 if (timeout_elapsed(timeout)) { 1439 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1440 address, mmio_read_32(address)); 1441 return -ETIMEDOUT; 1442 } 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int stm32mp1_hsidiv(unsigned long hsifreq) 1449 { 1450 uint8_t hsidiv; 1451 uint32_t hsidivfreq = MAX_HSI_HZ; 1452 1453 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1454 if (hsidivfreq == hsifreq) { 1455 break; 1456 } 1457 1458 hsidivfreq /= 2U; 1459 } 1460 1461 if (hsidiv == 4U) { 1462 ERROR("Invalid clk-hsi frequency\n"); 1463 return -1; 1464 } 1465 1466 if (hsidiv != 0U) { 1467 return stm32mp1_set_hsidiv(hsidiv); 1468 } 1469 1470 return 0; 1471 } 1472 1473 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1474 unsigned int clksrc, 1475 uint32_t *pllcfg, int plloff) 1476 { 1477 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1478 uintptr_t rcc_base = stm32mp_rcc_base(); 1479 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1480 enum stm32mp1_plltype type = pll->plltype; 1481 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1482 unsigned long refclk; 1483 uint32_t ifrge = 0U; 1484 uint32_t src, value, fracv = 0; 1485 void *fdt; 1486 1487 /* Check PLL output */ 1488 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1489 return false; 1490 } 1491 1492 /* Check current clksrc */ 1493 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1494 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1495 return false; 1496 } 1497 1498 /* Check Div */ 1499 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1500 1501 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1502 (pllcfg[PLLCFG_M] + 1U); 1503 1504 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1505 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1506 return false; 1507 } 1508 1509 if ((type == PLL_800) && (refclk >= 8000000U)) { 1510 ifrge = 1U; 1511 } 1512 1513 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1514 RCC_PLLNCFGR1_DIVN_MASK; 1515 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1516 RCC_PLLNCFGR1_DIVM_MASK; 1517 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1518 RCC_PLLNCFGR1_IFRGE_MASK; 1519 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1520 return false; 1521 } 1522 1523 /* Fractional configuration */ 1524 if (fdt_get_address(&fdt) == 1) { 1525 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1526 } 1527 1528 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1529 value |= RCC_PLLNFRACR_FRACLE; 1530 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1531 return false; 1532 } 1533 1534 /* Output config */ 1535 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1536 RCC_PLLNCFGR2_DIVP_MASK; 1537 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1538 RCC_PLLNCFGR2_DIVQ_MASK; 1539 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1540 RCC_PLLNCFGR2_DIVR_MASK; 1541 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1542 return false; 1543 } 1544 1545 return true; 1546 } 1547 1548 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1549 { 1550 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1551 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1552 1553 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1554 mmio_clrsetbits_32(pllxcr, 1555 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1556 RCC_PLLNCR_DIVREN, 1557 RCC_PLLNCR_PLLON); 1558 } 1559 1560 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1561 { 1562 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1563 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1564 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1565 1566 /* Wait PLL lock */ 1567 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1568 if (timeout_elapsed(timeout)) { 1569 ERROR("PLL%u start failed @ 0x%lx: 0x%x\n", 1570 pll_id, pllxcr, mmio_read_32(pllxcr)); 1571 return -ETIMEDOUT; 1572 } 1573 } 1574 1575 /* Start the requested output */ 1576 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1577 1578 return 0; 1579 } 1580 1581 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1582 { 1583 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1584 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1585 uint64_t timeout; 1586 1587 /* Stop all output */ 1588 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1589 RCC_PLLNCR_DIVREN); 1590 1591 /* Stop PLL */ 1592 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1593 1594 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1595 /* Wait PLL stopped */ 1596 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1597 if (timeout_elapsed(timeout)) { 1598 ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n", 1599 pll_id, pllxcr, mmio_read_32(pllxcr)); 1600 return -ETIMEDOUT; 1601 } 1602 } 1603 1604 return 0; 1605 } 1606 1607 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1608 uint32_t *pllcfg) 1609 { 1610 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1611 uintptr_t rcc_base = stm32mp_rcc_base(); 1612 uint32_t value; 1613 1614 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1615 RCC_PLLNCFGR2_DIVP_MASK; 1616 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1617 RCC_PLLNCFGR2_DIVQ_MASK; 1618 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1619 RCC_PLLNCFGR2_DIVR_MASK; 1620 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1621 } 1622 1623 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1624 uint32_t *pllcfg, uint32_t fracv) 1625 { 1626 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1627 uintptr_t rcc_base = stm32mp_rcc_base(); 1628 enum stm32mp1_plltype type = pll->plltype; 1629 unsigned long refclk; 1630 uint32_t ifrge = 0; 1631 uint32_t src, value; 1632 1633 src = mmio_read_32(rcc_base + pll->rckxselr) & 1634 RCC_SELR_REFCLK_SRC_MASK; 1635 1636 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1637 (pllcfg[PLLCFG_M] + 1U); 1638 1639 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1640 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1641 return -EINVAL; 1642 } 1643 1644 if ((type == PLL_800) && (refclk >= 8000000U)) { 1645 ifrge = 1U; 1646 } 1647 1648 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1649 RCC_PLLNCFGR1_DIVN_MASK; 1650 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1651 RCC_PLLNCFGR1_DIVM_MASK; 1652 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1653 RCC_PLLNCFGR1_IFRGE_MASK; 1654 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1655 1656 /* Fractional configuration */ 1657 value = 0; 1658 mmio_write_32(rcc_base + pll->pllxfracr, value); 1659 1660 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1661 mmio_write_32(rcc_base + pll->pllxfracr, value); 1662 1663 value |= RCC_PLLNFRACR_FRACLE; 1664 mmio_write_32(rcc_base + pll->pllxfracr, value); 1665 1666 stm32mp1_pll_config_output(pll_id, pllcfg); 1667 1668 return 0; 1669 } 1670 1671 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1672 { 1673 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1674 uint32_t pllxcsg = 0; 1675 1676 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1677 RCC_PLLNCSGR_MOD_PER_MASK; 1678 1679 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1680 RCC_PLLNCSGR_INC_STEP_MASK; 1681 1682 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1683 RCC_PLLNCSGR_SSCG_MODE_MASK; 1684 1685 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1686 1687 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1688 RCC_PLLNCR_SSCG_CTRL); 1689 } 1690 1691 static int stm32mp1_set_clksrc(unsigned int clksrc) 1692 { 1693 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1694 uint64_t timeout; 1695 1696 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1697 clksrc & RCC_SELR_SRC_MASK); 1698 1699 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1700 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1701 if (timeout_elapsed(timeout)) { 1702 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1703 clksrc_address, mmio_read_32(clksrc_address)); 1704 return -ETIMEDOUT; 1705 } 1706 } 1707 1708 return 0; 1709 } 1710 1711 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1712 { 1713 uint64_t timeout; 1714 1715 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1716 clkdiv & RCC_DIVR_DIV_MASK); 1717 1718 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1719 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1720 if (timeout_elapsed(timeout)) { 1721 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1722 clkdiv, address, mmio_read_32(address)); 1723 return -ETIMEDOUT; 1724 } 1725 } 1726 1727 return 0; 1728 } 1729 1730 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1731 { 1732 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1733 1734 /* 1735 * Binding clksrc : 1736 * bit15-4 offset 1737 * bit3: disable 1738 * bit2-0: MCOSEL[2:0] 1739 */ 1740 if ((clksrc & 0x8U) != 0U) { 1741 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1742 } else { 1743 mmio_clrsetbits_32(clksrc_address, 1744 RCC_MCOCFG_MCOSRC_MASK, 1745 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1746 mmio_clrsetbits_32(clksrc_address, 1747 RCC_MCOCFG_MCODIV_MASK, 1748 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1749 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1750 } 1751 } 1752 1753 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1754 { 1755 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1756 1757 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1758 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1759 mmio_clrsetbits_32(address, 1760 RCC_BDCR_RTCSRC_MASK, 1761 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1762 1763 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1764 } 1765 1766 if (lse_css) { 1767 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1768 } 1769 } 1770 1771 static void stm32mp1_pkcs_config(uint32_t pkcs) 1772 { 1773 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1774 uint32_t value = pkcs & 0xFU; 1775 uint32_t mask = 0xFU; 1776 1777 if ((pkcs & BIT(31)) != 0U) { 1778 mask <<= 4; 1779 value <<= 4; 1780 } 1781 1782 mmio_clrsetbits_32(address, mask, value); 1783 } 1784 1785 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1786 uint32_t *fracv, uint32_t *csg, 1787 bool *csg_set) 1788 { 1789 void *fdt; 1790 int ret; 1791 1792 if (fdt_get_address(&fdt) == 0) { 1793 return -FDT_ERR_NOTFOUND; 1794 } 1795 1796 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1797 pllcfg); 1798 if (ret < 0) { 1799 return -FDT_ERR_NOTFOUND; 1800 } 1801 1802 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1803 1804 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1805 csg); 1806 1807 *csg_set = (ret == 0); 1808 1809 if (ret == -FDT_ERR_NOTFOUND) { 1810 ret = 0; 1811 } 1812 1813 return ret; 1814 } 1815 1816 int stm32mp1_clk_init(void) 1817 { 1818 uintptr_t rcc_base = stm32mp_rcc_base(); 1819 uint32_t pllfracv[_PLL_NB]; 1820 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1821 unsigned int clksrc[CLKSRC_NB]; 1822 unsigned int clkdiv[CLKDIV_NB]; 1823 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1824 int plloff[_PLL_NB]; 1825 int ret, len; 1826 enum stm32mp1_pll_id i; 1827 bool pllcsg_set[_PLL_NB]; 1828 bool pllcfg_valid[_PLL_NB]; 1829 bool lse_css = false; 1830 bool pll3_preserve = false; 1831 bool pll4_preserve = false; 1832 bool pll4_bootrom = false; 1833 const fdt32_t *pkcs_cell; 1834 void *fdt; 1835 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1836 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1837 1838 if (fdt_get_address(&fdt) == 0) { 1839 return -FDT_ERR_NOTFOUND; 1840 } 1841 1842 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1843 clksrc); 1844 if (ret < 0) { 1845 return -FDT_ERR_NOTFOUND; 1846 } 1847 1848 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1849 clkdiv); 1850 if (ret < 0) { 1851 return -FDT_ERR_NOTFOUND; 1852 } 1853 1854 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1855 char name[12]; 1856 1857 snprintf(name, sizeof(name), "st,pll@%u", i); 1858 plloff[i] = fdt_rcc_subnode_offset(name); 1859 1860 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1861 if (!pllcfg_valid[i]) { 1862 continue; 1863 } 1864 1865 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1866 &pllfracv[i], pllcsg[i], 1867 &pllcsg_set[i]); 1868 if (ret != 0) { 1869 return ret; 1870 } 1871 } 1872 1873 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1874 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1875 1876 /* 1877 * Switch ON oscillator found in device-tree. 1878 * Note: HSI already ON after BootROM stage. 1879 */ 1880 if (stm32mp1_osc[_LSI] != 0U) { 1881 stm32mp1_lsi_set(true); 1882 } 1883 if (stm32mp1_osc[_LSE] != 0U) { 1884 const char *name = stm32mp_osc_node_label[_LSE]; 1885 bool bypass, digbyp; 1886 uint32_t lsedrv; 1887 1888 bypass = fdt_clk_read_bool(name, "st,bypass"); 1889 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1890 lse_css = fdt_clk_read_bool(name, "st,css"); 1891 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 1892 LSEDRV_MEDIUM_HIGH); 1893 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1894 } 1895 if (stm32mp1_osc[_HSE] != 0U) { 1896 const char *name = stm32mp_osc_node_label[_HSE]; 1897 bool bypass, digbyp, css; 1898 1899 bypass = fdt_clk_read_bool(name, "st,bypass"); 1900 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1901 css = fdt_clk_read_bool(name, "st,css"); 1902 stm32mp1_hse_enable(bypass, digbyp, css); 1903 } 1904 /* 1905 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1906 * => switch on CSI even if node is not present in device tree 1907 */ 1908 stm32mp1_csi_set(true); 1909 1910 /* Come back to HSI */ 1911 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1912 if (ret != 0) { 1913 return ret; 1914 } 1915 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1916 if (ret != 0) { 1917 return ret; 1918 } 1919 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1920 if (ret != 0) { 1921 return ret; 1922 } 1923 1924 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1925 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1926 if (pllcfg_valid[_PLL3]) { 1927 pll3_preserve = 1928 stm32mp1_check_pll_conf(_PLL3, 1929 clksrc[CLKSRC_PLL3], 1930 pllcfg[_PLL3], 1931 plloff[_PLL3]); 1932 } 1933 1934 if (pllcfg_valid[_PLL4]) { 1935 pll4_preserve = 1936 stm32mp1_check_pll_conf(_PLL4, 1937 clksrc[CLKSRC_PLL4], 1938 pllcfg[_PLL4], 1939 plloff[_PLL4]); 1940 } 1941 } 1942 /* Don't initialize PLL4, when used by BOOTROM */ 1943 if ((stm32mp_get_boot_itf_selected() == 1944 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1945 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1946 pll4_bootrom = true; 1947 pll4_preserve = true; 1948 } 1949 1950 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1951 if (((i == _PLL3) && pll3_preserve) || 1952 ((i == _PLL4) && pll4_preserve)) { 1953 continue; 1954 } 1955 1956 ret = stm32mp1_pll_stop(i); 1957 if (ret != 0) { 1958 return ret; 1959 } 1960 } 1961 1962 /* Configure HSIDIV */ 1963 if (stm32mp1_osc[_HSI] != 0U) { 1964 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1965 if (ret != 0) { 1966 return ret; 1967 } 1968 1969 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 1970 } 1971 1972 /* Select DIV */ 1973 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1974 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1975 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1976 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1977 if (ret != 0) { 1978 return ret; 1979 } 1980 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1981 if (ret != 0) { 1982 return ret; 1983 } 1984 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1985 if (ret != 0) { 1986 return ret; 1987 } 1988 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1989 if (ret != 0) { 1990 return ret; 1991 } 1992 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1993 if (ret != 0) { 1994 return ret; 1995 } 1996 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1997 if (ret != 0) { 1998 return ret; 1999 } 2000 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 2001 if (ret != 0) { 2002 return ret; 2003 } 2004 2005 /* No ready bit for RTC */ 2006 mmio_write_32(rcc_base + RCC_RTCDIVR, 2007 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 2008 2009 /* Configure PLLs source */ 2010 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2011 if (ret != 0) { 2012 return ret; 2013 } 2014 2015 if (!pll3_preserve) { 2016 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2017 if (ret != 0) { 2018 return ret; 2019 } 2020 } 2021 2022 if (!pll4_preserve) { 2023 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2024 if (ret != 0) { 2025 return ret; 2026 } 2027 } 2028 2029 /* Configure and start PLLs */ 2030 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2031 if (((i == _PLL3) && pll3_preserve) || 2032 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2033 continue; 2034 } 2035 2036 if (!pllcfg_valid[i]) { 2037 continue; 2038 } 2039 2040 if ((i == _PLL4) && pll4_bootrom) { 2041 /* Set output divider if not done by the Bootrom */ 2042 stm32mp1_pll_config_output(i, pllcfg[i]); 2043 continue; 2044 } 2045 2046 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2047 if (ret != 0) { 2048 return ret; 2049 } 2050 2051 if (pllcsg_set[i]) { 2052 stm32mp1_pll_csg(i, pllcsg[i]); 2053 } 2054 2055 stm32mp1_pll_start(i); 2056 } 2057 /* Wait and start PLLs output when ready */ 2058 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2059 if (!pllcfg_valid[i]) { 2060 continue; 2061 } 2062 2063 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2064 if (ret != 0) { 2065 return ret; 2066 } 2067 } 2068 /* Wait LSE ready before to use it */ 2069 if (stm32mp1_osc[_LSE] != 0U) { 2070 stm32mp1_lse_wait(); 2071 } 2072 2073 /* Configure with expected clock source */ 2074 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2075 if (ret != 0) { 2076 return ret; 2077 } 2078 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2079 if (ret != 0) { 2080 return ret; 2081 } 2082 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2083 if (ret != 0) { 2084 return ret; 2085 } 2086 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2087 2088 /* Configure PKCK */ 2089 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2090 if (pkcs_cell != NULL) { 2091 bool ckper_disabled = false; 2092 uint32_t j; 2093 uint32_t usbreg_bootrom = 0U; 2094 2095 if (pll4_bootrom) { 2096 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2097 } 2098 2099 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2100 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2101 2102 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2103 ckper_disabled = true; 2104 continue; 2105 } 2106 stm32mp1_pkcs_config(pkcs); 2107 } 2108 2109 /* 2110 * CKPER is source for some peripheral clocks 2111 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2112 * only if previous clock is still ON 2113 * => deactivated CKPER only after switching clock 2114 */ 2115 if (ckper_disabled) { 2116 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2117 } 2118 2119 if (pll4_bootrom) { 2120 uint32_t usbreg_value, usbreg_mask; 2121 const struct stm32mp1_clk_sel *sel; 2122 2123 sel = clk_sel_ref(_USBPHY_SEL); 2124 usbreg_mask = (uint32_t)sel->msk << sel->src; 2125 sel = clk_sel_ref(_USBO_SEL); 2126 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2127 2128 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2129 usbreg_mask; 2130 usbreg_bootrom &= usbreg_mask; 2131 if (usbreg_bootrom != usbreg_value) { 2132 VERBOSE("forbidden new USB clk path\n"); 2133 VERBOSE("vs bootrom on USB boot\n"); 2134 return -FDT_ERR_BADVALUE; 2135 } 2136 } 2137 } 2138 2139 /* Switch OFF HSI if not found in device-tree */ 2140 if (stm32mp1_osc[_HSI] == 0U) { 2141 stm32mp1_hsi_set(false); 2142 } 2143 2144 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2145 2146 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2147 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2148 RCC_DDRITFCR_DDRCKMOD_MASK, 2149 RCC_DDRITFCR_DDRCKMOD_SSR << 2150 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2151 2152 return 0; 2153 } 2154 2155 static void stm32mp1_osc_clk_init(const char *name, 2156 enum stm32mp_osc_id index) 2157 { 2158 uint32_t frequency; 2159 2160 if (fdt_osc_read_freq(name, &frequency) == 0) { 2161 stm32mp1_osc[index] = frequency; 2162 } 2163 } 2164 2165 static void stm32mp1_osc_init(void) 2166 { 2167 enum stm32mp_osc_id i; 2168 2169 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2170 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2171 } 2172 } 2173 2174 #ifdef STM32MP_SHARED_RESOURCES 2175 /* 2176 * Get the parent ID of the target parent clock, for tagging as secure 2177 * shared clock dependencies. 2178 */ 2179 static int get_parent_id_parent(unsigned int parent_id) 2180 { 2181 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2182 enum stm32mp1_pll_id pll_id; 2183 uint32_t p_sel; 2184 uintptr_t rcc_base = stm32mp_rcc_base(); 2185 2186 switch (parent_id) { 2187 case _ACLK: 2188 case _PCLK4: 2189 case _PCLK5: 2190 s = _AXIS_SEL; 2191 break; 2192 case _PLL1_P: 2193 case _PLL1_Q: 2194 case _PLL1_R: 2195 pll_id = _PLL1; 2196 break; 2197 case _PLL2_P: 2198 case _PLL2_Q: 2199 case _PLL2_R: 2200 pll_id = _PLL2; 2201 break; 2202 case _PLL3_P: 2203 case _PLL3_Q: 2204 case _PLL3_R: 2205 pll_id = _PLL3; 2206 break; 2207 case _PLL4_P: 2208 case _PLL4_Q: 2209 case _PLL4_R: 2210 pll_id = _PLL4; 2211 break; 2212 case _PCLK1: 2213 case _PCLK2: 2214 case _HCLK2: 2215 case _HCLK6: 2216 case _CK_PER: 2217 case _CK_MPU: 2218 case _CK_MCU: 2219 case _USB_PHY_48: 2220 /* We do not expect to access these */ 2221 panic(); 2222 break; 2223 default: 2224 /* Other parents have no parent */ 2225 return -1; 2226 } 2227 2228 if (s != _UNKNOWN_SEL) { 2229 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2230 2231 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2232 sel->msk; 2233 2234 if (p_sel < sel->nb_parent) { 2235 return (int)sel->parent[p_sel]; 2236 } 2237 } else { 2238 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2239 2240 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2241 RCC_SELR_REFCLK_SRC_MASK; 2242 2243 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2244 return (int)pll->refclk[p_sel]; 2245 } 2246 } 2247 2248 VERBOSE("No parent selected for %s\n", 2249 stm32mp1_clk_parent_name[parent_id]); 2250 2251 return -1; 2252 } 2253 2254 static void secure_parent_clocks(unsigned long parent_id) 2255 { 2256 int grandparent_id; 2257 2258 switch (parent_id) { 2259 case _PLL3_P: 2260 case _PLL3_Q: 2261 case _PLL3_R: 2262 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2263 break; 2264 2265 /* These clocks are always secure when RCC is secure */ 2266 case _ACLK: 2267 case _HCLK2: 2268 case _HCLK6: 2269 case _PCLK4: 2270 case _PCLK5: 2271 case _PLL1_P: 2272 case _PLL1_Q: 2273 case _PLL1_R: 2274 case _PLL2_P: 2275 case _PLL2_Q: 2276 case _PLL2_R: 2277 case _HSI: 2278 case _HSI_KER: 2279 case _LSI: 2280 case _CSI: 2281 case _CSI_KER: 2282 case _HSE: 2283 case _HSE_KER: 2284 case _HSE_KER_DIV2: 2285 case _HSE_RTC: 2286 case _LSE: 2287 break; 2288 2289 default: 2290 VERBOSE("Cannot secure parent clock %s\n", 2291 stm32mp1_clk_parent_name[parent_id]); 2292 panic(); 2293 } 2294 2295 grandparent_id = get_parent_id_parent(parent_id); 2296 if (grandparent_id >= 0) { 2297 secure_parent_clocks(grandparent_id); 2298 } 2299 } 2300 2301 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2302 { 2303 int parent_id; 2304 2305 if (!stm32mp1_rcc_is_secure()) { 2306 return; 2307 } 2308 2309 switch (clock_id) { 2310 case PLL1: 2311 case PLL2: 2312 /* PLL1/PLL2 are always secure: nothing to do */ 2313 break; 2314 case PLL3: 2315 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2316 break; 2317 case PLL4: 2318 ERROR("PLL4 cannot be secured\n"); 2319 panic(); 2320 break; 2321 default: 2322 /* Others are expected gateable clock */ 2323 parent_id = stm32mp1_clk_get_parent(clock_id); 2324 if (parent_id < 0) { 2325 INFO("No parent found for clock %lu\n", clock_id); 2326 } else { 2327 secure_parent_clocks(parent_id); 2328 } 2329 break; 2330 } 2331 } 2332 #endif /* STM32MP_SHARED_RESOURCES */ 2333 2334 void stm32mp1_clk_mcuss_protect(bool enable) 2335 { 2336 uintptr_t rcc_base = stm32mp_rcc_base(); 2337 2338 if (enable) { 2339 mmio_setbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2340 } else { 2341 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2342 } 2343 } 2344 2345 static void sync_earlyboot_clocks_state(void) 2346 { 2347 unsigned int idx; 2348 const unsigned long secure_enable[] = { 2349 AXIDCG, 2350 BSEC, 2351 DDRC1, DDRC1LP, 2352 DDRC2, DDRC2LP, 2353 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2354 DDRPHYC, DDRPHYCLP, 2355 RTCAPB, 2356 TZC1, TZC2, 2357 TZPC, 2358 STGEN_K, 2359 }; 2360 2361 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2362 stm32mp_clk_enable(secure_enable[idx]); 2363 } 2364 } 2365 2366 static const struct clk_ops stm32mp_clk_ops = { 2367 .enable = stm32mp_clk_enable, 2368 .disable = stm32mp_clk_disable, 2369 .is_enabled = stm32mp_clk_is_enabled, 2370 .get_rate = stm32mp_clk_get_rate, 2371 .get_parent = stm32mp1_clk_get_parent, 2372 }; 2373 2374 int stm32mp1_clk_probe(void) 2375 { 2376 #if defined(IMAGE_BL32) 2377 if (!fdt_get_rcc_secure_state()) { 2378 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U); 2379 } 2380 #endif 2381 2382 stm32mp1_osc_init(); 2383 2384 sync_earlyboot_clocks_state(); 2385 2386 clk_register(&stm32mp_clk_ops); 2387 2388 return 0; 2389 } 2390