1f4db9216SBiju Das /* 2f4db9216SBiju Das * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3f4db9216SBiju Das * 4f4db9216SBiju Das * SPDX-License-Identifier: BSD-3-Clause 5f4db9216SBiju Das */ 6f4db9216SBiju Das 7f4db9216SBiju Das #ifndef QOS_COMMON_H 8f4db9216SBiju Das #define QOS_COMMON_H 9f4db9216SBiju Das 10f4db9216SBiju Das #define RCAR_REF_DEFAULT 0U 11f4db9216SBiju Das 12f4db9216SBiju Das /* define used for get_refperiod. */ 13f4db9216SBiju Das /* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */ 14f4db9216SBiju Das #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */ 15f4db9216SBiju Das #define REFPERIOD_CYCLE /* unit:ns */ \ 16f4db9216SBiju Das ((126U * BASE_SUB_SLOT_NUM * 1000U) / 400U) 17f4db9216SBiju Das #else /* REF option */ 18f4db9216SBiju Das #define REFPERIOD_CYCLE /* unit:ns */ \ 19f4db9216SBiju Das ((252U * BASE_SUB_SLOT_NUM * 1000U) / 400U) 20f4db9216SBiju Das #endif 21f4db9216SBiju Das 22f4db9216SBiju Das #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) 23f4db9216SBiju Das /* define used for G2M */ 24f4db9216SBiju Das #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 25f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_11 0x7EU /* 126 */ 26f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_30 0x7EU /* 126 */ 27f4db9216SBiju Das #else /* REF 3.9usec */ 28f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_11 0xFCU /* 252 */ 29f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_30 0xFCU /* 252 */ 30f4db9216SBiju Das #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 31f4db9216SBiju Das 32f4db9216SBiju Das #define SL_INIT_SSLOTCLK_G2M_11 (SUB_SLOT_CYCLE_G2M_11 - 1U) 33f4db9216SBiju Das #define SL_INIT_SSLOTCLK_G2M_30 (SUB_SLOT_CYCLE_G2M_30 - 1U) 34f4db9216SBiju Das #define QOSWT_WTSET0_CYCLE_G2M_11 /* unit:ns */ \ 35f4db9216SBiju Das ((SUB_SLOT_CYCLE_G2M_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 36f4db9216SBiju Das #define QOSWT_WTSET0_CYCLE_G2M_30 /* unit:ns */ \ 37f4db9216SBiju Das ((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 38f4db9216SBiju Das #endif 39f4db9216SBiju Das 40*f8ecfd68SLad Prabhakar #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) 41*f8ecfd68SLad Prabhakar /* define used for G2N */ 42*f8ecfd68SLad Prabhakar #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 43*f8ecfd68SLad Prabhakar #define SUB_SLOT_CYCLE_G2N 0x7EU /* 126 */ 44*f8ecfd68SLad Prabhakar #else /* REF 3.9usec */ 45*f8ecfd68SLad Prabhakar #define SUB_SLOT_CYCLE_G2N 0xFCU /* 252 */ 46*f8ecfd68SLad Prabhakar #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 47*f8ecfd68SLad Prabhakar 48*f8ecfd68SLad Prabhakar #define SL_INIT_SSLOTCLK_G2N (SUB_SLOT_CYCLE_G2N - 1U) 49*f8ecfd68SLad Prabhakar #define QOSWT_WTSET0_CYCLE_G2N /* unit:ns */ \ 50*f8ecfd68SLad Prabhakar ((SUB_SLOT_CYCLE_G2N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 51*f8ecfd68SLad Prabhakar #endif /* (RCAR_LSI == RZ_G2N) */ 52*f8ecfd68SLad Prabhakar 5386c3cc30SLad Prabhakar #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) 5486c3cc30SLad Prabhakar /* define used for G2H */ 5586c3cc30SLad Prabhakar #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 5686c3cc30SLad Prabhakar #define SUB_SLOT_CYCLE_G2H 0x7EU /* 126 */ 5786c3cc30SLad Prabhakar #else /* REF 3.9usec */ 5886c3cc30SLad Prabhakar #define SUB_SLOT_CYCLE_G2H 0xFCU /* 252 */ 5986c3cc30SLad Prabhakar #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 6086c3cc30SLad Prabhakar 6186c3cc30SLad Prabhakar #define SL_INIT_SSLOTCLK_G2H (SUB_SLOT_CYCLE_G2H - 1U) 6286c3cc30SLad Prabhakar #define QOSWT_WTSET0_CYCLE_G2H /* unit:ns */ \ 6386c3cc30SLad Prabhakar ((SUB_SLOT_CYCLE_G2H * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 6486c3cc30SLad Prabhakar #endif 6586c3cc30SLad Prabhakar 66f4db9216SBiju Das #define OPERATING_FREQ 400U /* MHz */ 67f4db9216SBiju Das #define BASE_SUB_SLOT_NUM 0x6U 68f4db9216SBiju Das #define SUB_SLOT_CYCLE 0x7EU /* 126 */ 69f4db9216SBiju Das 70f4db9216SBiju Das #define QOSWT_WTSET0_CYCLE /* unit:ns */ \ 71f4db9216SBiju Das ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 72f4db9216SBiju Das 73f4db9216SBiju Das #define SL_INIT_REFFSSLOT (0x3U << 24U) 74f4db9216SBiju Das #define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U) 75f4db9216SBiju Das #define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U) 76f4db9216SBiju Das 77f4db9216SBiju Das typedef struct { 78f4db9216SBiju Das uintptr_t addr; 79f4db9216SBiju Das uint64_t value; 80f4db9216SBiju Das } mstat_slot_t; 81f4db9216SBiju Das 82f4db9216SBiju Das struct rcar_gen3_dbsc_qos_settings { 83f4db9216SBiju Das uint32_t reg; 84f4db9216SBiju Das uint32_t val; 85f4db9216SBiju Das }; 86f4db9216SBiju Das 87f4db9216SBiju Das extern uint32_t qos_init_ddr_ch; 88f4db9216SBiju Das extern uint8_t qos_init_ddr_phyvalid; 89f4db9216SBiju Das 90f4db9216SBiju Das void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos, 91f4db9216SBiju Das unsigned int qos_size, bool dbsc_wren); 92f4db9216SBiju Das 93f4db9216SBiju Das #endif /* QOS_COMMON_H */ 94