1*f4db9216SBiju Das /* 2*f4db9216SBiju Das * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3*f4db9216SBiju Das * 4*f4db9216SBiju Das * SPDX-License-Identifier: BSD-3-Clause 5*f4db9216SBiju Das */ 6*f4db9216SBiju Das 7*f4db9216SBiju Das #ifndef QOS_COMMON_H 8*f4db9216SBiju Das #define QOS_COMMON_H 9*f4db9216SBiju Das 10*f4db9216SBiju Das #define RCAR_REF_DEFAULT 0U 11*f4db9216SBiju Das 12*f4db9216SBiju Das /* define used for get_refperiod. */ 13*f4db9216SBiju Das /* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */ 14*f4db9216SBiju Das #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */ 15*f4db9216SBiju Das #define REFPERIOD_CYCLE /* unit:ns */ \ 16*f4db9216SBiju Das ((126U * BASE_SUB_SLOT_NUM * 1000U) / 400U) 17*f4db9216SBiju Das #else /* REF option */ 18*f4db9216SBiju Das #define REFPERIOD_CYCLE /* unit:ns */ \ 19*f4db9216SBiju Das ((252U * BASE_SUB_SLOT_NUM * 1000U) / 400U) 20*f4db9216SBiju Das #endif 21*f4db9216SBiju Das 22*f4db9216SBiju Das #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) 23*f4db9216SBiju Das /* define used for G2M */ 24*f4db9216SBiju Das #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 25*f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_11 0x7EU /* 126 */ 26*f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_30 0x7EU /* 126 */ 27*f4db9216SBiju Das #else /* REF 3.9usec */ 28*f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_11 0xFCU /* 252 */ 29*f4db9216SBiju Das #define SUB_SLOT_CYCLE_G2M_30 0xFCU /* 252 */ 30*f4db9216SBiju Das #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 31*f4db9216SBiju Das 32*f4db9216SBiju Das #define SL_INIT_SSLOTCLK_G2M_11 (SUB_SLOT_CYCLE_G2M_11 - 1U) 33*f4db9216SBiju Das #define SL_INIT_SSLOTCLK_G2M_30 (SUB_SLOT_CYCLE_G2M_30 - 1U) 34*f4db9216SBiju Das #define QOSWT_WTSET0_CYCLE_G2M_11 /* unit:ns */ \ 35*f4db9216SBiju Das ((SUB_SLOT_CYCLE_G2M_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 36*f4db9216SBiju Das #define QOSWT_WTSET0_CYCLE_G2M_30 /* unit:ns */ \ 37*f4db9216SBiju Das ((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 38*f4db9216SBiju Das #endif 39*f4db9216SBiju Das 40*f4db9216SBiju Das #define OPERATING_FREQ 400U /* MHz */ 41*f4db9216SBiju Das #define BASE_SUB_SLOT_NUM 0x6U 42*f4db9216SBiju Das #define SUB_SLOT_CYCLE 0x7EU /* 126 */ 43*f4db9216SBiju Das 44*f4db9216SBiju Das #define QOSWT_WTSET0_CYCLE /* unit:ns */ \ 45*f4db9216SBiju Das ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 46*f4db9216SBiju Das 47*f4db9216SBiju Das #define SL_INIT_REFFSSLOT (0x3U << 24U) 48*f4db9216SBiju Das #define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U) 49*f4db9216SBiju Das #define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U) 50*f4db9216SBiju Das 51*f4db9216SBiju Das typedef struct { 52*f4db9216SBiju Das uintptr_t addr; 53*f4db9216SBiju Das uint64_t value; 54*f4db9216SBiju Das } mstat_slot_t; 55*f4db9216SBiju Das 56*f4db9216SBiju Das struct rcar_gen3_dbsc_qos_settings { 57*f4db9216SBiju Das uint32_t reg; 58*f4db9216SBiju Das uint32_t val; 59*f4db9216SBiju Das }; 60*f4db9216SBiju Das 61*f4db9216SBiju Das extern uint32_t qos_init_ddr_ch; 62*f4db9216SBiju Das extern uint8_t qos_init_ddr_phyvalid; 63*f4db9216SBiju Das 64*f4db9216SBiju Das void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos, 65*f4db9216SBiju Das unsigned int qos_size, bool dbsc_wren); 66*f4db9216SBiju Das 67*f4db9216SBiju Das #endif /* QOS_COMMON_H */ 68