1 /* 2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 #include <lib/mmio.h> 11 12 #include "../qos_common.h" 13 #include "qos_init_g2m_v11.h" 14 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 15 #if RCAR_REF_INT == RCAR_REF_DEFAULT 16 #include "qos_init_g2m_v11_mstat195.h" 17 #else /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 18 #include "qos_init_g2m_v11_mstat390.h" 19 #endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 20 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 21 #if RCAR_REF_INT == RCAR_REF_DEFAULT 22 #include "qos_init_g2m_v11_qoswt195.h" 23 #else /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 24 #include "qos_init_g2m_v11_qoswt390.h" 25 #endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 26 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 27 #endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */ 28 #include "qos_reg.h" 29 30 #define RCAR_QOS_VERSION "rev.0.19" 31 32 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */ 33 34 #define QOSWT_WTEN_ENABLE 0x1U 35 36 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2M_11 (SL_INIT_SSLOTCLK_G2M_11 - 0x5U) 37 38 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U 39 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U 40 #define QOSWT_WTREF_SLOT0_EN \ 41 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 42 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 43 #define QOSWT_WTREF_SLOT1_EN \ 44 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 45 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 46 47 #define QOSWT_WTSET0_REQ_SSLOT0 5U 48 #define WT_BASE_SUB_SLOT_NUM0 12U 49 #define QOSWT_WTSET0_PERIOD0_G2M_11 \ 50 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2M_11) - 1U) 51 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 52 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U) 53 54 #define QOSWT_WTSET1_PERIOD1_G2M_11 \ 55 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2M_11) - 1U) 56 #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 57 #define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U) 58 59 static const struct rcar_gen3_dbsc_qos_settings g2m_v11_qos[] = { 60 /* BUFCAM settings */ 61 { DBSC_DBCAM0CNF1, 0x00043218U }, 62 { DBSC_DBCAM0CNF2, 0x000000F4U }, 63 { DBSC_DBCAM0CNF3, 0x00000000U }, 64 { DBSC_DBSCHCNT0, 0x000F0037U }, 65 { DBSC_DBSCHSZ0, 0x00000001U }, 66 { DBSC_DBSCHRW0, 0x22421111U }, 67 68 /* DDR3 */ 69 { DBSC_SCFCTST2, 0x012F1123U }, 70 71 /* QoS settings */ 72 { DBSC_DBSCHQOS00, 0x00000F00U }, 73 { DBSC_DBSCHQOS01, 0x00000B00U }, 74 { DBSC_DBSCHQOS02, 0x00000000U }, 75 { DBSC_DBSCHQOS03, 0x00000000U }, 76 { DBSC_DBSCHQOS40, 0x00000300U }, 77 { DBSC_DBSCHQOS41, 0x000002F0U }, 78 { DBSC_DBSCHQOS42, 0x00000200U }, 79 { DBSC_DBSCHQOS43, 0x00000100U }, 80 { DBSC_DBSCHQOS90, 0x00000100U }, 81 { DBSC_DBSCHQOS91, 0x000000F0U }, 82 { DBSC_DBSCHQOS92, 0x000000A0U }, 83 { DBSC_DBSCHQOS93, 0x00000040U }, 84 { DBSC_DBSCHQOS120, 0x00000040U }, 85 { DBSC_DBSCHQOS121, 0x00000030U }, 86 { DBSC_DBSCHQOS122, 0x00000020U }, 87 { DBSC_DBSCHQOS123, 0x00000010U }, 88 { DBSC_DBSCHQOS130, 0x00000100U }, 89 { DBSC_DBSCHQOS131, 0x000000F0U }, 90 { DBSC_DBSCHQOS132, 0x000000A0U }, 91 { DBSC_DBSCHQOS133, 0x00000040U }, 92 { DBSC_DBSCHQOS140, 0x000000C0U }, 93 { DBSC_DBSCHQOS141, 0x000000B0U }, 94 { DBSC_DBSCHQOS142, 0x00000080U }, 95 { DBSC_DBSCHQOS143, 0x00000040U }, 96 { DBSC_DBSCHQOS150, 0x00000040U }, 97 { DBSC_DBSCHQOS151, 0x00000030U }, 98 { DBSC_DBSCHQOS152, 0x00000020U }, 99 { DBSC_DBSCHQOS153, 0x00000010U }, 100 }; 101 102 void qos_init_g2m_v11(void) 103 { 104 uint32_t i; 105 106 rzg_qos_dbsc_setting(g2m_v11_qos, ARRAY_SIZE(g2m_v11_qos), false); 107 108 /* DRAM Split Address mapping */ 109 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH 110 #if RCAR_LSI == RZ_G2M 111 #error "Don't set DRAM Split 4ch(G2M)" 112 #else /* RCAR_LSI == RZ_G2M */ 113 ERROR("DRAM Split 4ch not supported.(G2M)"); 114 panic(); 115 #endif /* RCAR_LSI == RZ_G2M */ 116 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ 117 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) 118 NOTICE("BL2: DRAM Split is 2ch\n"); 119 mmio_write_32(AXI_ADSPLCR0, 0x00000000U); 120 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | 121 ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(0x1CU) | 122 ADSPLCR0_SWP); 123 mmio_write_32(AXI_ADSPLCR2, 0x00001004U); 124 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); 125 #else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */ 126 NOTICE("BL2: DRAM Split is OFF\n"); 127 #endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */ 128 129 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) 130 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 131 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); 132 #endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */ 133 134 #if RCAR_REF_INT == RCAR_REF_DEFAULT 135 NOTICE("BL2: DRAM refresh interval 1.95 usec\n"); 136 #else /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 137 NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); 138 #endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 139 140 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 141 NOTICE("BL2: Periodic Write DQ Training\n"); 142 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 143 144 mmio_write_32(QOSCTRL_RAS, 0x00000044U); 145 mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL); 146 mmio_write_32(QOSCTRL_DANT, 0x0020100AU); 147 mmio_write_32(QOSCTRL_INSFC, 0x06330001U); 148 mmio_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ 149 150 mmio_write_32(QOSCTRL_SL_INIT, 151 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | 152 SL_INIT_SSLOTCLK_G2M_11); 153 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 154 mmio_write_32(QOSCTRL_REF_ARS, 155 QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2M_11 << 16); 156 #else /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 157 mmio_write_32(QOSCTRL_REF_ARS, 0x00330000U); 158 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 159 160 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { 161 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); 162 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); 163 } 164 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { 165 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); 166 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); 167 } 168 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 169 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { 170 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); 171 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); 172 } 173 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { 174 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); 175 mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]); 176 } 177 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 178 179 /* 3DG bus Leaf setting */ 180 mmio_write_32(GPU_ACT_GRD, 0x00001234U); 181 mmio_write_32(GPU_ACT0, 0x00000000U); 182 mmio_write_32(GPU_ACT1, 0x00000000U); 183 mmio_write_32(GPU_ACT2, 0x00000000U); 184 mmio_write_32(GPU_ACT3, 0x00000000U); 185 186 /* RT bus Leaf setting */ 187 mmio_write_32(RT_ACT0, 0x00000000U); 188 mmio_write_32(RT_ACT1, 0x00000000U); 189 190 /* CCI bus Leaf setting */ 191 mmio_write_32(CPU_ACT0, 0x00000003U); 192 mmio_write_32(CPU_ACT1, 0x00000003U); 193 mmio_write_32(CPU_ACT2, 0x00000003U); 194 mmio_write_32(CPU_ACT3, 0x00000003U); 195 196 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 197 198 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 199 /* re-write training setting */ 200 mmio_write_32(QOSWT_WTREF, 201 (QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN); 202 mmio_write_32(QOSWT_WTSET0, 203 (QOSWT_WTSET0_PERIOD0_G2M_11 << 16) | 204 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0); 205 mmio_write_32(QOSWT_WTSET1, 206 (QOSWT_WTSET1_PERIOD1_G2M_11 << 16) | 207 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1); 208 209 mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE); 210 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 211 212 mmio_write_32(QOSCTRL_STATQC, 0x00000001U); 213 #else /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 214 NOTICE("BL2: QoS is None\n"); 215 216 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 217 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 218 } 219