1 /* 2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 #include <lib/mmio.h> 11 12 #include "qos_init_g2h_v30.h" 13 #include "../qos_common.h" 14 #include "../qos_reg.h" 15 16 #define RCAR_QOS_VERSION "rev.0.07" 17 18 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */ 19 #define QOSWT_WTEN_ENABLE 0x1U 20 21 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H (SL_INIT_SSLOTCLK_G2H - 0x5U) 22 23 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U 24 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U 25 #define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 26 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 27 #define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 28 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 29 30 #define QOSWT_WTSET0_REQ_SSLOT0 5U 31 #define WT_BASE_SUB_SLOT_NUM0 12U 32 #define QOSWT_WTSET0_PERIOD0_G2H ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2H) - 1U) 33 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 34 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U) 35 36 #define QOSWT_WTSET1_PERIOD1_G2H (QOSWT_WTSET0_PERIOD0_G2H) 37 #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0) 38 #define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0) 39 40 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 41 #if RCAR_REF_INT == RCAR_REF_DEFAULT 42 #include "qos_init_g2h_mstat195.h" 43 #else 44 #include "qos_init_g2h_mstat390.h" 45 #endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 46 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 47 #if RCAR_REF_INT == RCAR_REF_DEFAULT 48 #include "qos_init_g2h_qoswt195.h" 49 #else 50 #include "qos_init_g2h_qoswt390.h" 51 #endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */ 52 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 53 #endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */ 54 55 static const struct rcar_gen3_dbsc_qos_settings g2h_v30_qos[] = { 56 /* BUFCAM settings */ 57 { DBSC_DBCAM0CNF1, 0x00043218U }, 58 { DBSC_DBCAM0CNF2, 0x000000F4U }, 59 { DBSC_DBCAM0CNF3, 0x00000000U }, 60 { DBSC_DBSCHCNT0, 0x000F0037U }, 61 { DBSC_DBSCHSZ0, 0x00000001U }, 62 { DBSC_DBSCHRW0, 0x22421111U }, 63 64 /* DDR3 */ 65 { DBSC_SCFCTST2, 0x012F1123U }, 66 67 /* QoS Settings */ 68 { DBSC_DBSCHQOS00, 0x00000F00U }, 69 { DBSC_DBSCHQOS01, 0x00000B00U }, 70 { DBSC_DBSCHQOS02, 0x00000000U }, 71 { DBSC_DBSCHQOS03, 0x00000000U }, 72 { DBSC_DBSCHQOS40, 0x00000300U }, 73 { DBSC_DBSCHQOS41, 0x000002F0U }, 74 { DBSC_DBSCHQOS42, 0x00000200U }, 75 { DBSC_DBSCHQOS43, 0x00000100U }, 76 { DBSC_DBSCHQOS90, 0x00000100U }, 77 { DBSC_DBSCHQOS91, 0x000000F0U }, 78 { DBSC_DBSCHQOS92, 0x000000A0U }, 79 { DBSC_DBSCHQOS93, 0x00000040U }, 80 { DBSC_DBSCHQOS120, 0x00000040U }, 81 { DBSC_DBSCHQOS121, 0x00000030U }, 82 { DBSC_DBSCHQOS122, 0x00000020U }, 83 { DBSC_DBSCHQOS123, 0x00000010U }, 84 { DBSC_DBSCHQOS130, 0x00000100U }, 85 { DBSC_DBSCHQOS131, 0x000000F0U }, 86 { DBSC_DBSCHQOS132, 0x000000A0U }, 87 { DBSC_DBSCHQOS133, 0x00000040U }, 88 { DBSC_DBSCHQOS140, 0x000000C0U }, 89 { DBSC_DBSCHQOS141, 0x000000B0U }, 90 { DBSC_DBSCHQOS142, 0x00000080U }, 91 { DBSC_DBSCHQOS143, 0x00000040U }, 92 { DBSC_DBSCHQOS150, 0x00000040U }, 93 { DBSC_DBSCHQOS151, 0x00000030U }, 94 { DBSC_DBSCHQOS152, 0x00000020U }, 95 { DBSC_DBSCHQOS153, 0x00000010U }, 96 }; 97 98 void qos_init_g2h_v30(void) 99 { 100 unsigned int split_area; 101 102 rzg_qos_dbsc_setting(g2h_v30_qos, ARRAY_SIZE(g2h_v30_qos), true); 103 104 /* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for G2H */ 105 split_area = 0x1CU; 106 107 /* DRAM split address mapping */ 108 #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) 109 #if RCAR_LSI == RZ_G2H 110 #error "Don't set DRAM Split 4ch(G2H)" 111 #else /* RCAR_LSI == RZ_G2H */ 112 ERROR("DRAM split 4ch not supported.(G2H)"); 113 panic(); 114 #endif /* RCAR_LSI == RZ_G2H */ 115 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ 116 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) 117 NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid); 118 119 mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area)); 120 mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | 121 ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(split_area) | 122 ADSPLCR0_SWP); 123 mmio_write_32(AXI_ADSPLCR2, 0x00001004U); 124 mmio_write_32(AXI_ADSPLCR3, 0x00000000U); 125 #else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */ 126 mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area)); 127 NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid); 128 #endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */ 129 130 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) 131 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 132 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); 133 #endif 134 135 #if RCAR_REF_INT == RCAR_REF_DEFAULT 136 NOTICE("BL2: DRAM refresh interval 1.95 usec\n"); 137 #else 138 NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); 139 #endif 140 141 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 142 NOTICE("BL2: Periodic Write DQ Training\n"); 143 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 144 145 mmio_write_32(QOSCTRL_RAS, 0x00000044U); 146 mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL); 147 mmio_write_32(QOSCTRL_DANT, 0x0020100AU); 148 mmio_write_32(QOSCTRL_FSS, 0x0000000AU); 149 mmio_write_32(QOSCTRL_INSFC, 0x06330001U); 150 mmio_write_32(QOSCTRL_RACNT0, 0x00010003U); 151 152 /* GPU Boost Mode */ 153 mmio_write_32(QOSCTRL_STATGEN0, 0x00000001U); 154 155 mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | 156 SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2H); 157 mmio_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H << 16))); 158 159 uint32_t i; 160 161 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { 162 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); 163 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); 164 } 165 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { 166 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); 167 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); 168 } 169 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 170 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { 171 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); 172 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); 173 } 174 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { 175 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); 176 mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]); 177 } 178 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 179 180 /* AXI setting */ 181 mmio_write_32(AXI_MMCR, 0x00010008U); 182 mmio_write_32(AXI_TR3CR, 0x00010000U); 183 mmio_write_32(AXI_TR4CR, 0x00010000U); 184 185 /* RT bus Leaf setting */ 186 mmio_write_32(RT_ACT0, 0x00000000U); 187 mmio_write_32(RT_ACT1, 0x00000000U); 188 189 /* CCI bus Leaf setting */ 190 mmio_write_32(CPU_ACT0, 0x00000003U); 191 mmio_write_32(CPU_ACT1, 0x00000003U); 192 mmio_write_32(CPU_ACT2, 0x00000003U); 193 mmio_write_32(CPU_ACT3, 0x00000003U); 194 195 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 196 197 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 198 /* re-write training setting */ 199 mmio_write_32(QOSWT_WTREF, 200 ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN)); 201 mmio_write_32(QOSWT_WTSET0, 202 ((QOSWT_WTSET0_PERIOD0_G2H << 16) | 203 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0)); 204 mmio_write_32(QOSWT_WTSET1, 205 ((QOSWT_WTSET1_PERIOD1_G2H << 16) | 206 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1)); 207 208 mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE); 209 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 210 211 mmio_write_32(QOSCTRL_STATQC, 0x00000001U); 212 #else 213 NOTICE("BL2: QoS is None\n"); 214 215 mmio_write_32(QOSCTRL_RAEN, 0x00000001U); 216 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 217 } 218