1 /* 2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <lib/mmio.h> 10 11 #include "pfc_init_g2h.h" 12 #include "rcar_def.h" 13 #include "../pfc_regs.h" 14 15 #define GPSR0_D15 BIT(15) 16 #define GPSR0_D14 BIT(14) 17 #define GPSR0_D13 BIT(13) 18 #define GPSR0_D12 BIT(12) 19 #define GPSR0_D11 BIT(11) 20 #define GPSR0_D10 BIT(10) 21 #define GPSR0_D9 BIT(9) 22 #define GPSR0_D8 BIT(8) 23 #define GPSR0_D7 BIT(7) 24 #define GPSR0_D6 BIT(6) 25 #define GPSR0_D5 BIT(5) 26 #define GPSR0_D4 BIT(4) 27 #define GPSR0_D3 BIT(3) 28 #define GPSR0_D2 BIT(2) 29 #define GPSR0_D1 BIT(1) 30 #define GPSR0_D0 BIT(0) 31 #define GPSR1_CLKOUT BIT(28) 32 #define GPSR1_EX_WAIT0_A BIT(27) 33 #define GPSR1_WE1 BIT(26) 34 #define GPSR1_WE0 BIT(25) 35 #define GPSR1_RD_WR BIT(24) 36 #define GPSR1_RD BIT(23) 37 #define GPSR1_BS BIT(22) 38 #define GPSR1_CS1_A26 BIT(21) 39 #define GPSR1_CS0 BIT(20) 40 #define GPSR1_A19 BIT(19) 41 #define GPSR1_A18 BIT(18) 42 #define GPSR1_A17 BIT(17) 43 #define GPSR1_A16 BIT(16) 44 #define GPSR1_A15 BIT(15) 45 #define GPSR1_A14 BIT(14) 46 #define GPSR1_A13 BIT(13) 47 #define GPSR1_A12 BIT(12) 48 #define GPSR1_A11 BIT(11) 49 #define GPSR1_A10 BIT(10) 50 #define GPSR1_A9 BIT(9) 51 #define GPSR1_A8 BIT(8) 52 #define GPSR1_A7 BIT(7) 53 #define GPSR1_A6 BIT(6) 54 #define GPSR1_A5 BIT(5) 55 #define GPSR1_A4 BIT(4) 56 #define GPSR1_A3 BIT(3) 57 #define GPSR1_A2 BIT(2) 58 #define GPSR1_A1 BIT(1) 59 #define GPSR1_A0 BIT(0) 60 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14) 61 #define GPSR2_AVB_AVTP_MATCH_A BIT(13) 62 #define GPSR2_AVB_LINK BIT(12) 63 #define GPSR2_AVB_PHY_INT BIT(11) 64 #define GPSR2_AVB_MAGIC BIT(10) 65 #define GPSR2_AVB_MDC BIT(9) 66 #define GPSR2_PWM2_A BIT(8) 67 #define GPSR2_PWM1_A BIT(7) 68 #define GPSR2_PWM0 BIT(6) 69 #define GPSR2_IRQ5 BIT(5) 70 #define GPSR2_IRQ4 BIT(4) 71 #define GPSR2_IRQ3 BIT(3) 72 #define GPSR2_IRQ2 BIT(2) 73 #define GPSR2_IRQ1 BIT(1) 74 #define GPSR2_IRQ0 BIT(0) 75 #define GPSR3_SD1_WP BIT(15) 76 #define GPSR3_SD1_CD BIT(14) 77 #define GPSR3_SD0_WP BIT(13) 78 #define GPSR3_SD0_CD BIT(12) 79 #define GPSR3_SD1_DAT3 BIT(11) 80 #define GPSR3_SD1_DAT2 BIT(10) 81 #define GPSR3_SD1_DAT1 BIT(9) 82 #define GPSR3_SD1_DAT0 BIT(8) 83 #define GPSR3_SD1_CMD BIT(7) 84 #define GPSR3_SD1_CLK BIT(6) 85 #define GPSR3_SD0_DAT3 BIT(5) 86 #define GPSR3_SD0_DAT2 BIT(4) 87 #define GPSR3_SD0_DAT1 BIT(3) 88 #define GPSR3_SD0_DAT0 BIT(2) 89 #define GPSR3_SD0_CMD BIT(1) 90 #define GPSR3_SD0_CLK BIT(0) 91 #define GPSR4_SD3_DS BIT(17) 92 #define GPSR4_SD3_DAT7 BIT(16) 93 #define GPSR4_SD3_DAT6 BIT(15) 94 #define GPSR4_SD3_DAT5 BIT(14) 95 #define GPSR4_SD3_DAT4 BIT(13) 96 #define GPSR4_SD3_DAT3 BIT(12) 97 #define GPSR4_SD3_DAT2 BIT(11) 98 #define GPSR4_SD3_DAT1 BIT(10) 99 #define GPSR4_SD3_DAT0 BIT(9) 100 #define GPSR4_SD3_CMD BIT(8) 101 #define GPSR4_SD3_CLK BIT(7) 102 #define GPSR4_SD2_DS BIT(6) 103 #define GPSR4_SD2_DAT3 BIT(5) 104 #define GPSR4_SD2_DAT2 BIT(4) 105 #define GPSR4_SD2_DAT1 BIT(3) 106 #define GPSR4_SD2_DAT0 BIT(2) 107 #define GPSR4_SD2_CMD BIT(1) 108 #define GPSR4_SD2_CLK BIT(0) 109 #define GPSR5_MLB_DAT BIT(25) 110 #define GPSR5_MLB_SIG BIT(24) 111 #define GPSR5_MLB_CLK BIT(23) 112 #define GPSR5_MSIOF0_RXD BIT(22) 113 #define GPSR5_MSIOF0_SS2 BIT(21) 114 #define GPSR5_MSIOF0_TXD BIT(20) 115 #define GPSR5_MSIOF0_SS1 BIT(19) 116 #define GPSR5_MSIOF0_SYNC BIT(18) 117 #define GPSR5_MSIOF0_SCK BIT(17) 118 #define GPSR5_HRTS0 BIT(16) 119 #define GPSR5_HCTS0 BIT(15) 120 #define GPSR5_HTX0 BIT(14) 121 #define GPSR5_HRX0 BIT(13) 122 #define GPSR5_HSCK0 BIT(12) 123 #define GPSR5_RX2_A BIT(11) 124 #define GPSR5_TX2_A BIT(10) 125 #define GPSR5_SCK2 BIT(9) 126 #define GPSR5_RTS1 BIT(8) 127 #define GPSR5_CTS1 BIT(7) 128 #define GPSR5_TX1_A BIT(6) 129 #define GPSR5_RX1_A BIT(5) 130 #define GPSR5_RTS0 BIT(4) 131 #define GPSR5_CTS0 BIT(3) 132 #define GPSR5_TX0 BIT(2) 133 #define GPSR5_RX0 BIT(1) 134 #define GPSR5_SCK0 BIT(0) 135 #define GPSR6_USB31_OVC BIT(31) 136 #define GPSR6_USB31_PWEN BIT(30) 137 #define GPSR6_USB30_OVC BIT(29) 138 #define GPSR6_USB30_PWEN BIT(28) 139 #define GPSR6_USB1_OVC BIT(27) 140 #define GPSR6_USB1_PWEN BIT(26) 141 #define GPSR6_USB0_OVC BIT(25) 142 #define GPSR6_USB0_PWEN BIT(24) 143 #define GPSR6_AUDIO_CLKB_B BIT(23) 144 #define GPSR6_AUDIO_CLKA_A BIT(22) 145 #define GPSR6_SSI_SDATA9_A BIT(21) 146 #define GPSR6_SSI_SDATA8 BIT(20) 147 #define GPSR6_SSI_SDATA7 BIT(19) 148 #define GPSR6_SSI_WS78 BIT(18) 149 #define GPSR6_SSI_SCK78 BIT(17) 150 #define GPSR6_SSI_SDATA6 BIT(16) 151 #define GPSR6_SSI_WS6 BIT(15) 152 #define GPSR6_SSI_SCK6 BIT(14) 153 #define GPSR6_SSI_SDATA5 BIT(13) 154 #define GPSR6_SSI_WS5 BIT(12) 155 #define GPSR6_SSI_SCK5 BIT(11) 156 #define GPSR6_SSI_SDATA4 BIT(10) 157 #define GPSR6_SSI_WS4 BIT(9) 158 #define GPSR6_SSI_SCK4 BIT(8) 159 #define GPSR6_SSI_SDATA3 BIT(7) 160 #define GPSR6_SSI_WS34 BIT(6) 161 #define GPSR6_SSI_SCK34 BIT(5) 162 #define GPSR6_SSI_SDATA2_A BIT(4) 163 #define GPSR6_SSI_SDATA1_A BIT(3) 164 #define GPSR6_SSI_SDATA0 BIT(2) 165 #define GPSR6_SSI_WS0129 BIT(1) 166 #define GPSR6_SSI_SCK0129 BIT(0) 167 #define GPSR7_AVS2 BIT(1) 168 #define GPSR7_AVS1 BIT(0) 169 170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) 171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) 172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) 173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) 174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) 175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) 176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) 177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) 178 179 #define POC_SD3_DS_33V BIT(29) 180 #define POC_SD3_DAT7_33V BIT(28) 181 #define POC_SD3_DAT6_33V BIT(27) 182 #define POC_SD3_DAT5_33V BIT(26) 183 #define POC_SD3_DAT4_33V BIT(25) 184 #define POC_SD3_DAT3_33V BIT(24) 185 #define POC_SD3_DAT2_33V BIT(23) 186 #define POC_SD3_DAT1_33V BIT(22) 187 #define POC_SD3_DAT0_33V BIT(21) 188 #define POC_SD3_CMD_33V BIT(20) 189 #define POC_SD3_CLK_33V BIT(19) 190 #define POC_SD2_DS_33V BIT(18) 191 #define POC_SD2_DAT3_33V BIT(17) 192 #define POC_SD2_DAT2_33V BIT(16) 193 #define POC_SD2_DAT1_33V BIT(15) 194 #define POC_SD2_DAT0_33V BIT(14) 195 #define POC_SD2_CMD_33V BIT(13) 196 #define POC_SD2_CLK_33V BIT(12) 197 #define POC_SD1_DAT3_33V BIT(11) 198 #define POC_SD1_DAT2_33V BIT(10) 199 #define POC_SD1_DAT1_33V BIT(9) 200 #define POC_SD1_DAT0_33V BIT(8) 201 #define POC_SD1_CMD_33V BIT(7) 202 #define POC_SD1_CLK_33V BIT(6) 203 #define POC_SD0_DAT3_33V BIT(5) 204 #define POC_SD0_DAT2_33V BIT(4) 205 #define POC_SD0_DAT1_33V BIT(3) 206 #define POC_SD0_DAT0_33V BIT(2) 207 #define POC_SD0_CMD_33V BIT(1) 208 #define POC_SD0_CLK_33V BIT(0) 209 210 #define DRVCTRL0_MASK (0xCCCCCCCCU) 211 #define DRVCTRL1_MASK (0xCCCCCCC8U) 212 #define DRVCTRL2_MASK (0x88888888U) 213 #define DRVCTRL3_MASK (0x88888888U) 214 #define DRVCTRL4_MASK (0x88888888U) 215 #define DRVCTRL5_MASK (0x88888888U) 216 #define DRVCTRL6_MASK (0x88888888U) 217 #define DRVCTRL7_MASK (0x88888888U) 218 #define DRVCTRL8_MASK (0x88888888U) 219 #define DRVCTRL9_MASK (0x88888888U) 220 #define DRVCTRL10_MASK (0x88888888U) 221 #define DRVCTRL11_MASK (0x888888CCU) 222 #define DRVCTRL12_MASK (0xCCCFFFCFU) 223 #define DRVCTRL13_MASK (0xCC888888U) 224 #define DRVCTRL14_MASK (0x88888888U) 225 #define DRVCTRL15_MASK (0x88888888U) 226 #define DRVCTRL16_MASK (0x88888888U) 227 #define DRVCTRL17_MASK (0x88888888U) 228 #define DRVCTRL18_MASK (0x88888888U) 229 #define DRVCTRL19_MASK (0x88888888U) 230 #define DRVCTRL20_MASK (0x88888888U) 231 #define DRVCTRL21_MASK (0x88888888U) 232 #define DRVCTRL22_MASK (0x88888888U) 233 #define DRVCTRL23_MASK (0x88888888U) 234 #define DRVCTRL24_MASK (0x8888888FU) 235 236 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) 237 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) 238 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) 239 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) 240 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) 241 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) 242 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) 243 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) 244 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) 245 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) 246 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) 247 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) 248 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) 249 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) 250 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) 251 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) 252 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) 253 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) 254 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) 255 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) 256 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) 257 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) 258 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) 259 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) 260 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) 261 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) 262 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) 263 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) 264 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) 265 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) 266 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) 267 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) 268 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) 269 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) 270 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) 271 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) 272 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) 273 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) 274 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) 275 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) 276 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) 277 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) 278 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) 279 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) 280 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) 281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) 282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) 283 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) 284 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) 285 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) 286 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) 287 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) 288 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) 289 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) 290 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) 291 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) 292 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) 293 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) 294 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) 295 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) 296 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) 297 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) 298 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) 299 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) 300 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) 301 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) 302 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) 303 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) 304 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) 305 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) 306 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) 307 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) 308 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) 309 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) 310 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) 311 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) 312 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) 313 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) 314 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) 315 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) 316 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) 317 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) 318 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) 319 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) 320 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) 321 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) 322 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) 323 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) 324 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) 325 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) 326 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) 327 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) 328 #define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U) 329 #define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U) 330 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) 331 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) 332 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) 333 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) 334 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) 335 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) 336 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) 337 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) 338 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) 339 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) 340 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) 341 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) 342 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) 343 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) 344 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) 345 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) 346 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) 347 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) 348 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) 349 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) 350 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) 351 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) 352 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) 353 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) 354 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) 355 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) 356 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) 357 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) 358 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) 359 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) 360 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) 361 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) 362 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) 363 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) 364 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) 365 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) 366 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) 367 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) 368 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) 369 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) 370 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) 371 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) 372 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) 373 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) 374 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) 375 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) 376 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) 377 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) 378 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) 379 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) 380 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) 381 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) 382 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) 383 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) 384 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) 385 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) 386 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) 387 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) 388 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) 389 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) 390 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) 391 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) 392 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) 393 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) 394 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) 395 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) 396 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) 397 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) 398 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) 399 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) 400 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) 401 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) 402 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) 403 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) 404 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) 405 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) 406 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) 407 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) 408 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) 409 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) 410 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) 411 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) 412 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) 413 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) 414 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) 415 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) 416 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) 417 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) 418 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) 419 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) 420 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) 421 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) 422 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) 423 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) 424 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) 425 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) 426 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) 427 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) 428 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) 429 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) 430 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) 431 432 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) 433 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) 434 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) 435 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) 436 #define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U) 437 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) 438 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) 439 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) 440 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) 441 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) 442 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) 443 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) 444 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) 445 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) 446 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) 447 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) 448 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) 449 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) 450 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) 451 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) 452 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U) 453 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U) 454 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) 455 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) 456 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U) 457 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U) 458 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U) 459 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U) 460 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U) 461 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U) 462 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U) 463 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U) 464 #define MOD_SEL0_FSO_A ((uint32_t)0U << 15U) 465 #define MOD_SEL0_FSO_B ((uint32_t)1U << 15U) 466 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U) 467 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U) 468 #define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U) 469 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U) 470 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U) 471 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U) 472 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U) 473 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U) 474 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U) 475 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U) 476 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U) 477 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U) 478 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U) 479 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U) 480 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U) 481 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U) 482 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U) 483 #define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U) 484 #define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U) 485 #define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U) 486 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) 487 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) 488 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) 489 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) 490 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) 491 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) 492 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) 493 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) 494 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) 495 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) 496 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) 497 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) 498 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) 499 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) 500 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) 501 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) 502 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) 503 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) 504 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) 505 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) 506 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) 507 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) 508 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) 509 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) 510 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) 511 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) 512 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) 513 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) 514 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) 515 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) 516 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) 517 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) 518 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) 519 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) 520 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) 521 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) 522 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) 523 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) 524 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) 525 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) 526 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) 527 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) 528 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) 529 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) 530 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) 531 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) 532 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) 533 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) 534 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) 535 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) 536 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) 537 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) 538 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) 539 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) 540 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) 541 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) 542 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) 543 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) 544 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) 545 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) 546 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) 547 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) 548 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) 549 #define MOD_SEL2_FM_A ((uint32_t)0U << 27U) 550 #define MOD_SEL2_FM_B ((uint32_t)1U << 27U) 551 #define MOD_SEL2_FM_C ((uint32_t)2U << 27U) 552 #define MOD_SEL2_FM_D ((uint32_t)3U << 27U) 553 #define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U) 554 #define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U) 555 #define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U) 556 #define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U) 557 #define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U) 558 #define MOD_SEL2_NDF_A ((uint32_t)0U << 22U) 559 #define MOD_SEL2_NDF_B ((uint32_t)1U << 22U) 560 #define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U) 561 #define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U) 562 #define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U) 563 #define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U) 564 #define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U) 565 #define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U) 566 #define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U) 567 #define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U) 568 #define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U) 569 #define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U) 570 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) 571 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) 572 573 static void pfc_reg_write(uint32_t addr, uint32_t data) 574 { 575 mmio_write_32(PFC_PMMR, ~data); 576 mmio_write_32((uintptr_t)addr, data); 577 } 578 579 void pfc_init_g2h(void) 580 { 581 uint32_t reg; 582 583 /* initialize module select */ 584 pfc_reg_write(PFC_MOD_SEL0, 585 MOD_SEL0_MSIOF3_A | 586 MOD_SEL0_MSIOF2_A | 587 MOD_SEL0_MSIOF1_A | 588 MOD_SEL0_LBSC_A | 589 MOD_SEL0_IEBUS_A | 590 MOD_SEL0_I2C2_A | 591 MOD_SEL0_I2C1_A | 592 MOD_SEL0_HSCIF4_A | 593 MOD_SEL0_HSCIF3_A | 594 MOD_SEL0_HSCIF1_A | 595 MOD_SEL0_FSO_A | 596 MOD_SEL0_HSCIF2_A | 597 MOD_SEL0_ETHERAVB_A | 598 MOD_SEL0_DRIF3_A | 599 MOD_SEL0_DRIF2_A | 600 MOD_SEL0_DRIF1_A | 601 MOD_SEL0_DRIF0_A | 602 MOD_SEL0_CANFD0_A | 603 MOD_SEL0_ADG_A_A); 604 605 pfc_reg_write(PFC_MOD_SEL1, 606 MOD_SEL1_TSIF1_A | 607 MOD_SEL1_TSIF0_A | 608 MOD_SEL1_TIMER_TMU_A | 609 MOD_SEL1_SSP1_1_A | 610 MOD_SEL1_SSP1_0_A | 611 MOD_SEL1_SSI_A | 612 MOD_SEL1_SPEED_PULSE_IF_A | 613 MOD_SEL1_SIMCARD_A | 614 MOD_SEL1_SDHI2_A | 615 MOD_SEL1_SCIF4_A | 616 MOD_SEL1_SCIF3_A | 617 MOD_SEL1_SCIF2_A | 618 MOD_SEL1_SCIF1_A | 619 MOD_SEL1_SCIF_A | 620 MOD_SEL1_REMOCON_A | 621 MOD_SEL1_RCAN0_A | 622 MOD_SEL1_PWM6_A | 623 MOD_SEL1_PWM5_A | 624 MOD_SEL1_PWM4_A | 625 MOD_SEL1_PWM3_A | 626 MOD_SEL1_PWM2_A | 627 MOD_SEL1_PWM1_A); 628 629 pfc_reg_write(PFC_MOD_SEL2, 630 MOD_SEL2_I2C_5_B | 631 MOD_SEL2_I2C_3_B | 632 MOD_SEL2_I2C_0_B | 633 MOD_SEL2_FM_A | 634 MOD_SEL2_SCIF5_A | 635 MOD_SEL2_I2C6_A | 636 MOD_SEL2_NDF_A | 637 MOD_SEL2_SSI2_A | 638 MOD_SEL2_SSI9_A | 639 MOD_SEL2_TIMER_TMU2_A | 640 MOD_SEL2_ADG_B_A | 641 MOD_SEL2_ADG_C_A | 642 MOD_SEL2_VIN4_A); 643 644 /* initialize peripheral function select */ 645 pfc_reg_write(PFC_IPSR0, 646 IPSR_28_FUNC(0) | 647 IPSR_24_FUNC(0) | 648 IPSR_20_FUNC(0) | 649 IPSR_16_FUNC(0) | 650 IPSR_12_FUNC(0) | 651 IPSR_8_FUNC(0) | 652 IPSR_4_FUNC(0) | 653 IPSR_0_FUNC(0)); 654 655 pfc_reg_write(PFC_IPSR1, 656 IPSR_28_FUNC(6) | 657 IPSR_24_FUNC(0) | 658 IPSR_20_FUNC(0) | 659 IPSR_16_FUNC(0) | 660 IPSR_12_FUNC(3) | 661 IPSR_8_FUNC(3) | 662 IPSR_4_FUNC(3) | 663 IPSR_0_FUNC(3)); 664 665 pfc_reg_write(PFC_IPSR2, 666 IPSR_28_FUNC(0) | 667 IPSR_24_FUNC(6) | 668 IPSR_20_FUNC(6) | 669 IPSR_16_FUNC(6) | 670 IPSR_12_FUNC(6) | 671 IPSR_8_FUNC(6) | 672 IPSR_4_FUNC(6) | 673 IPSR_0_FUNC(6)); 674 675 pfc_reg_write(PFC_IPSR3, 676 IPSR_28_FUNC(6) | 677 IPSR_24_FUNC(6) | 678 IPSR_20_FUNC(6) | 679 IPSR_16_FUNC(6) | 680 IPSR_12_FUNC(6) | 681 IPSR_8_FUNC(0) | 682 IPSR_4_FUNC(0) | 683 IPSR_0_FUNC(0)); 684 685 pfc_reg_write(PFC_IPSR4, 686 IPSR_28_FUNC(0) | 687 IPSR_24_FUNC(0) | 688 IPSR_20_FUNC(0) | 689 IPSR_16_FUNC(0) | 690 IPSR_12_FUNC(0) | 691 IPSR_8_FUNC(6) | 692 IPSR_4_FUNC(6) | 693 IPSR_0_FUNC(6)); 694 695 pfc_reg_write(PFC_IPSR5, 696 IPSR_28_FUNC(0) | 697 IPSR_24_FUNC(0) | 698 IPSR_20_FUNC(0) | 699 IPSR_16_FUNC(0) | 700 IPSR_12_FUNC(0) | 701 IPSR_8_FUNC(6) | 702 IPSR_4_FUNC(0) | 703 IPSR_0_FUNC(0)); 704 705 pfc_reg_write(PFC_IPSR6, 706 IPSR_28_FUNC(6) | 707 IPSR_24_FUNC(6) | 708 IPSR_20_FUNC(6) | 709 IPSR_16_FUNC(6) | 710 IPSR_12_FUNC(6) | 711 IPSR_8_FUNC(0) | 712 IPSR_4_FUNC(0) | 713 IPSR_0_FUNC(0)); 714 715 pfc_reg_write(PFC_IPSR7, 716 IPSR_28_FUNC(0) | 717 IPSR_24_FUNC(0) | 718 IPSR_20_FUNC(0) | 719 IPSR_16_FUNC(0) | 720 IPSR_12_FUNC(0) | 721 IPSR_8_FUNC(6) | 722 IPSR_4_FUNC(6) | 723 IPSR_0_FUNC(6)); 724 725 pfc_reg_write(PFC_IPSR8, 726 IPSR_28_FUNC(1) | 727 IPSR_24_FUNC(1) | 728 IPSR_20_FUNC(1) | 729 IPSR_16_FUNC(1) | 730 IPSR_12_FUNC(0) | 731 IPSR_8_FUNC(0) | 732 IPSR_4_FUNC(0) | 733 IPSR_0_FUNC(0)); 734 735 pfc_reg_write(PFC_IPSR9, 736 IPSR_28_FUNC(0) | 737 IPSR_24_FUNC(0) | 738 IPSR_20_FUNC(0) | 739 IPSR_16_FUNC(0) | 740 IPSR_12_FUNC(0) | 741 IPSR_8_FUNC(0) | 742 IPSR_4_FUNC(0) | 743 IPSR_0_FUNC(0)); 744 745 pfc_reg_write(PFC_IPSR10, 746 IPSR_28_FUNC(0) | 747 IPSR_24_FUNC(0) | 748 IPSR_20_FUNC(0) | 749 IPSR_16_FUNC(0) | 750 IPSR_12_FUNC(0) | 751 IPSR_8_FUNC(0) | 752 IPSR_4_FUNC(0) | 753 IPSR_0_FUNC(0)); 754 755 pfc_reg_write(PFC_IPSR11, 756 IPSR_28_FUNC(0) | 757 IPSR_24_FUNC(4) | 758 IPSR_20_FUNC(0) | 759 IPSR_16_FUNC(0) | 760 IPSR_12_FUNC(0) | 761 IPSR_8_FUNC(0) | 762 IPSR_4_FUNC(0) | 763 IPSR_0_FUNC(0)); 764 765 pfc_reg_write(PFC_IPSR12, 766 IPSR_28_FUNC(0) | 767 IPSR_24_FUNC(0) | 768 IPSR_20_FUNC(0) | 769 IPSR_16_FUNC(0) | 770 IPSR_12_FUNC(0) | 771 IPSR_8_FUNC(4) | 772 IPSR_4_FUNC(0) | 773 IPSR_0_FUNC(0)); 774 775 pfc_reg_write(PFC_IPSR13, 776 IPSR_28_FUNC(8) | 777 IPSR_24_FUNC(0) | 778 IPSR_20_FUNC(0) | 779 IPSR_16_FUNC(0) | 780 IPSR_12_FUNC(0) | 781 IPSR_8_FUNC(3) | 782 IPSR_4_FUNC(0) | 783 IPSR_0_FUNC(0)); 784 785 pfc_reg_write(PFC_IPSR14, 786 IPSR_28_FUNC(0) | 787 IPSR_24_FUNC(0) | 788 IPSR_20_FUNC(0) | 789 IPSR_16_FUNC(0) | 790 IPSR_12_FUNC(0) | 791 IPSR_8_FUNC(0) | 792 IPSR_4_FUNC(3) | 793 IPSR_0_FUNC(8)); 794 795 pfc_reg_write(PFC_IPSR15, 796 IPSR_28_FUNC(0) | 797 IPSR_24_FUNC(0) | 798 IPSR_20_FUNC(0) | 799 IPSR_16_FUNC(0) | 800 IPSR_12_FUNC(0) | 801 IPSR_8_FUNC(0) | 802 IPSR_4_FUNC(0) | 803 IPSR_0_FUNC(0)); 804 805 pfc_reg_write(PFC_IPSR16, 806 IPSR_28_FUNC(0) | 807 IPSR_24_FUNC(0) | 808 IPSR_20_FUNC(0) | 809 IPSR_16_FUNC(0) | 810 IPSR_12_FUNC(0) | 811 IPSR_8_FUNC(0) | 812 IPSR_4_FUNC(0) | 813 IPSR_0_FUNC(0)); 814 815 pfc_reg_write(PFC_IPSR17, 816 IPSR_28_FUNC(0) | 817 IPSR_24_FUNC(0) | 818 IPSR_20_FUNC(0) | 819 IPSR_16_FUNC(0) | 820 IPSR_12_FUNC(0) | 821 IPSR_8_FUNC(0) | 822 IPSR_4_FUNC(1) | 823 IPSR_0_FUNC(0)); 824 825 pfc_reg_write(PFC_IPSR18, 826 IPSR_4_FUNC(0) | 827 IPSR_0_FUNC(0)); 828 829 /* initialize GPIO/peripheral function select */ 830 pfc_reg_write(PFC_GPSR0, 831 GPSR0_D15 | 832 GPSR0_D14 | 833 GPSR0_D13 | 834 GPSR0_D12 | 835 GPSR0_D11 | 836 GPSR0_D10 | 837 GPSR0_D9 | 838 GPSR0_D8 | 839 GPSR0_D7 | 840 GPSR0_D6 | 841 GPSR0_D5 | 842 GPSR0_D4 | 843 GPSR0_D3 | 844 GPSR0_D2 | 845 GPSR0_D0); 846 847 pfc_reg_write(PFC_GPSR1, 848 GPSR1_CLKOUT | 849 GPSR1_EX_WAIT0_A | 850 GPSR1_WE1 | 851 GPSR1_RD | 852 GPSR1_RD_WR | 853 GPSR1_CS0 | 854 GPSR1_A19 | 855 GPSR1_A18 | 856 GPSR1_A17 | 857 GPSR1_A16 | 858 GPSR1_A15 | 859 GPSR1_A14 | 860 GPSR1_A13 | 861 GPSR1_A12 | 862 GPSR1_A7 | 863 GPSR1_A6 | 864 GPSR1_A5 | 865 GPSR1_A4 | 866 GPSR1_A3 | 867 GPSR1_A2 | 868 GPSR1_A1 | 869 GPSR1_A0); 870 871 pfc_reg_write(PFC_GPSR2, 872 GPSR2_AVB_AVTP_CAPTURE_A | 873 GPSR2_AVB_AVTP_MATCH_A | 874 GPSR2_AVB_LINK | 875 GPSR2_AVB_PHY_INT | 876 GPSR2_AVB_MDC | 877 GPSR2_PWM2_A | 878 GPSR2_PWM1_A | 879 GPSR2_IRQ4 | 880 GPSR2_IRQ3 | 881 GPSR2_IRQ2 | 882 GPSR2_IRQ1 | 883 GPSR2_IRQ0); 884 885 pfc_reg_write(PFC_GPSR3, 886 GPSR3_SD0_CD | 887 GPSR3_SD1_DAT3 | 888 GPSR3_SD1_DAT2 | 889 GPSR3_SD1_DAT1 | 890 GPSR3_SD1_DAT0 | 891 GPSR3_SD0_DAT3 | 892 GPSR3_SD0_DAT2 | 893 GPSR3_SD0_DAT1 | 894 GPSR3_SD0_DAT0 | 895 GPSR3_SD0_CMD | 896 GPSR3_SD0_CLK); 897 898 pfc_reg_write(PFC_GPSR4, 899 GPSR4_SD3_DS | 900 GPSR4_SD3_DAT7 | 901 GPSR4_SD3_DAT6 | 902 GPSR4_SD3_DAT5 | 903 GPSR4_SD3_DAT4 | 904 GPSR4_SD3_DAT3 | 905 GPSR4_SD3_DAT2 | 906 GPSR4_SD3_DAT1 | 907 GPSR4_SD3_DAT0 | 908 GPSR4_SD3_CMD | 909 GPSR4_SD3_CLK | 910 GPSR4_SD2_DAT3 | 911 GPSR4_SD2_DAT2 | 912 GPSR4_SD2_DAT1 | 913 GPSR4_SD2_DAT0 | 914 GPSR4_SD2_CMD | 915 GPSR4_SD2_CLK); 916 917 pfc_reg_write(PFC_GPSR5, 918 GPSR5_MSIOF0_RXD | 919 GPSR5_MSIOF0_TXD | 920 GPSR5_MSIOF0_SYNC | 921 GPSR5_MSIOF0_SCK | 922 GPSR5_RX2_A | 923 GPSR5_TX2_A | 924 GPSR5_RTS1 | 925 GPSR5_CTS1 | 926 GPSR5_TX1_A | 927 GPSR5_RX1_A | 928 GPSR5_RTS0 | 929 GPSR5_SCK0); 930 931 pfc_reg_write(PFC_GPSR6, 932 GPSR6_AUDIO_CLKB_B | 933 GPSR6_AUDIO_CLKA_A | 934 GPSR6_SSI_WS6 | 935 GPSR6_SSI_SCK6 | 936 GPSR6_SSI_SDATA4 | 937 GPSR6_SSI_WS4 | 938 GPSR6_SSI_SCK4 | 939 GPSR6_SSI_SDATA1_A | 940 GPSR6_SSI_SDATA0 | 941 GPSR6_SSI_WS0129 | 942 GPSR6_SSI_SCK0129); 943 944 pfc_reg_write(PFC_GPSR7, 945 GPSR7_AVS2 | 946 GPSR7_AVS1); 947 948 /* initialize POC control register */ 949 pfc_reg_write(PFC_POCCTRL0, 950 POC_SD0_DAT3_33V | 951 POC_SD0_DAT2_33V | 952 POC_SD0_DAT1_33V | 953 POC_SD0_DAT0_33V | 954 POC_SD0_CMD_33V | 955 POC_SD0_CLK_33V); 956 957 /* initialize DRV control register */ 958 reg = mmio_read_32(PFC_DRVCTRL0); 959 reg = (reg & DRVCTRL0_MASK) | 960 DRVCTRL0_QSPI0_SPCLK(3) | 961 DRVCTRL0_QSPI0_MOSI_IO0(3) | 962 DRVCTRL0_QSPI0_MISO_IO1(3) | 963 DRVCTRL0_QSPI0_IO2(3) | 964 DRVCTRL0_QSPI0_IO3(3) | 965 DRVCTRL0_QSPI0_SSL(3) | 966 DRVCTRL0_QSPI1_SPCLK(3) | 967 DRVCTRL0_QSPI1_MOSI_IO0(3); 968 pfc_reg_write(PFC_DRVCTRL0, reg); 969 970 reg = mmio_read_32(PFC_DRVCTRL1); 971 reg = (reg & DRVCTRL1_MASK) | 972 DRVCTRL1_QSPI1_MISO_IO1(3) | 973 DRVCTRL1_QSPI1_IO2(3) | 974 DRVCTRL1_QSPI1_IO3(3) | 975 DRVCTRL1_QSPI1_SS(3) | 976 DRVCTRL1_RPC_INT(3) | 977 DRVCTRL1_RPC_WP(3) | 978 DRVCTRL1_RPC_RESET(3) | 979 DRVCTRL1_AVB_RX_CTL(7); 980 pfc_reg_write(PFC_DRVCTRL1, reg); 981 982 reg = mmio_read_32(PFC_DRVCTRL2); 983 reg = (reg & DRVCTRL2_MASK) | 984 DRVCTRL2_AVB_RXC(7) | 985 DRVCTRL2_AVB_RD0(7) | 986 DRVCTRL2_AVB_RD1(7) | 987 DRVCTRL2_AVB_RD2(7) | 988 DRVCTRL2_AVB_RD3(7) | 989 DRVCTRL2_AVB_TX_CTL(3) | 990 DRVCTRL2_AVB_TXC(3) | 991 DRVCTRL2_AVB_TD0(3); 992 pfc_reg_write(PFC_DRVCTRL2, reg); 993 994 reg = mmio_read_32(PFC_DRVCTRL3); 995 reg = (reg & DRVCTRL3_MASK) | 996 DRVCTRL3_AVB_TD1(3) | 997 DRVCTRL3_AVB_TD2(3) | 998 DRVCTRL3_AVB_TD3(3) | 999 DRVCTRL3_AVB_TXCREFCLK(7) | 1000 DRVCTRL3_AVB_MDIO(7) | 1001 DRVCTRL3_AVB_MDC(7) | 1002 DRVCTRL3_AVB_MAGIC(7) | 1003 DRVCTRL3_AVB_PHY_INT(7); 1004 pfc_reg_write(PFC_DRVCTRL3, reg); 1005 1006 reg = mmio_read_32(PFC_DRVCTRL4); 1007 reg = (reg & DRVCTRL4_MASK) | 1008 DRVCTRL4_AVB_LINK(7) | 1009 DRVCTRL4_AVB_AVTP_MATCH(7) | 1010 DRVCTRL4_AVB_AVTP_CAPTURE(7) | 1011 DRVCTRL4_IRQ0(7) | 1012 DRVCTRL4_IRQ1(7) | 1013 DRVCTRL4_IRQ2(7) | 1014 DRVCTRL4_IRQ3(7) | 1015 DRVCTRL4_IRQ4(7); 1016 pfc_reg_write(PFC_DRVCTRL4, reg); 1017 1018 reg = mmio_read_32(PFC_DRVCTRL5); 1019 reg = (reg & DRVCTRL5_MASK) | 1020 DRVCTRL5_IRQ5(7) | 1021 DRVCTRL5_PWM0(7) | 1022 DRVCTRL5_PWM1(7) | 1023 DRVCTRL5_PWM2(7) | 1024 DRVCTRL5_A0(3) | 1025 DRVCTRL5_A1(3) | 1026 DRVCTRL5_A2(3) | 1027 DRVCTRL5_A3(3); 1028 pfc_reg_write(PFC_DRVCTRL5, reg); 1029 1030 reg = mmio_read_32(PFC_DRVCTRL6); 1031 reg = (reg & DRVCTRL6_MASK) | 1032 DRVCTRL6_A4(3) | 1033 DRVCTRL6_A5(3) | 1034 DRVCTRL6_A6(3) | 1035 DRVCTRL6_A7(3) | 1036 DRVCTRL6_A8(7) | 1037 DRVCTRL6_A9(7) | 1038 DRVCTRL6_A10(7) | 1039 DRVCTRL6_A11(7); 1040 pfc_reg_write(PFC_DRVCTRL6, reg); 1041 1042 reg = mmio_read_32(PFC_DRVCTRL7); 1043 reg = (reg & DRVCTRL7_MASK) | 1044 DRVCTRL7_A12(3) | 1045 DRVCTRL7_A13(3) | 1046 DRVCTRL7_A14(3) | 1047 DRVCTRL7_A15(3) | 1048 DRVCTRL7_A16(3) | 1049 DRVCTRL7_A17(3) | 1050 DRVCTRL7_A18(3) | 1051 DRVCTRL7_A19(3); 1052 pfc_reg_write(PFC_DRVCTRL7, reg); 1053 1054 reg = mmio_read_32(PFC_DRVCTRL8); 1055 reg = (reg & DRVCTRL8_MASK) | 1056 DRVCTRL8_CLKOUT(7) | 1057 DRVCTRL8_CS0(7) | 1058 DRVCTRL8_CS1_A2(7) | 1059 DRVCTRL8_BS(7) | 1060 DRVCTRL8_RD(7) | 1061 DRVCTRL8_RD_W(7) | 1062 DRVCTRL8_WE0(7) | 1063 DRVCTRL8_WE1(7); 1064 pfc_reg_write(PFC_DRVCTRL8, reg); 1065 1066 reg = mmio_read_32(PFC_DRVCTRL9); 1067 reg = (reg & DRVCTRL9_MASK) | 1068 DRVCTRL9_EX_WAIT0(7) | 1069 DRVCTRL9_PRESETOU(7) | 1070 DRVCTRL9_D0(7) | 1071 DRVCTRL9_D1(7) | 1072 DRVCTRL9_D2(7) | 1073 DRVCTRL9_D3(7) | 1074 DRVCTRL9_D4(7) | 1075 DRVCTRL9_D5(7); 1076 pfc_reg_write(PFC_DRVCTRL9, reg); 1077 1078 reg = mmio_read_32(PFC_DRVCTRL10); 1079 reg = (reg & DRVCTRL10_MASK) | 1080 DRVCTRL10_D6(7) | 1081 DRVCTRL10_D7(7) | 1082 DRVCTRL10_D8(3) | 1083 DRVCTRL10_D9(3) | 1084 DRVCTRL10_D10(3) | 1085 DRVCTRL10_D11(3) | 1086 DRVCTRL10_D12(3) | 1087 DRVCTRL10_D13(3); 1088 pfc_reg_write(PFC_DRVCTRL10, reg); 1089 1090 reg = mmio_read_32(PFC_DRVCTRL11); 1091 reg = (reg & DRVCTRL11_MASK) | 1092 DRVCTRL11_D14(3) | 1093 DRVCTRL11_D15(3) | 1094 DRVCTRL11_AVS1(7) | 1095 DRVCTRL11_AVS2(7) | 1096 DRVCTRL11_GP7_02(7) | 1097 DRVCTRL11_GP7_03(7) | 1098 DRVCTRL11_DU_DOTCLKIN0(3) | 1099 DRVCTRL11_DU_DOTCLKIN1(3); 1100 pfc_reg_write(PFC_DRVCTRL11, reg); 1101 1102 reg = mmio_read_32(PFC_DRVCTRL12); 1103 reg = (reg & DRVCTRL12_MASK) | 1104 DRVCTRL12_DU_DOTCLKIN2(3) | 1105 DRVCTRL12_DU_DOTCLKIN3(3) | 1106 DRVCTRL12_DU_FSCLKST(3) | 1107 DRVCTRL12_DU_TMS(3); 1108 pfc_reg_write(PFC_DRVCTRL12, reg); 1109 1110 reg = mmio_read_32(PFC_DRVCTRL13); 1111 reg = (reg & DRVCTRL13_MASK) | 1112 DRVCTRL13_TDO(3) | 1113 DRVCTRL13_ASEBRK(3) | 1114 DRVCTRL13_SD0_CLK(7) | 1115 DRVCTRL13_SD0_CMD(7) | 1116 DRVCTRL13_SD0_DAT0(7) | 1117 DRVCTRL13_SD0_DAT1(7) | 1118 DRVCTRL13_SD0_DAT2(7) | 1119 DRVCTRL13_SD0_DAT3(7); 1120 pfc_reg_write(PFC_DRVCTRL13, reg); 1121 1122 reg = mmio_read_32(PFC_DRVCTRL14); 1123 reg = (reg & DRVCTRL14_MASK) | 1124 DRVCTRL14_SD1_CLK(7) | 1125 DRVCTRL14_SD1_CMD(7) | 1126 DRVCTRL14_SD1_DAT0(5) | 1127 DRVCTRL14_SD1_DAT1(5) | 1128 DRVCTRL14_SD1_DAT2(5) | 1129 DRVCTRL14_SD1_DAT3(5) | 1130 DRVCTRL14_SD2_CLK(5) | 1131 DRVCTRL14_SD2_CMD(5); 1132 pfc_reg_write(PFC_DRVCTRL14, reg); 1133 1134 reg = mmio_read_32(PFC_DRVCTRL15); 1135 reg = (reg & DRVCTRL15_MASK) | 1136 DRVCTRL15_SD2_DAT0(5) | 1137 DRVCTRL15_SD2_DAT1(5) | 1138 DRVCTRL15_SD2_DAT2(5) | 1139 DRVCTRL15_SD2_DAT3(5) | 1140 DRVCTRL15_SD2_DS(5) | 1141 DRVCTRL15_SD3_CLK(7) | 1142 DRVCTRL15_SD3_CMD(7) | 1143 DRVCTRL15_SD3_DAT0(7); 1144 pfc_reg_write(PFC_DRVCTRL15, reg); 1145 1146 reg = mmio_read_32(PFC_DRVCTRL16); 1147 reg = (reg & DRVCTRL16_MASK) | 1148 DRVCTRL16_SD3_DAT1(7) | 1149 DRVCTRL16_SD3_DAT2(7) | 1150 DRVCTRL16_SD3_DAT3(7) | 1151 DRVCTRL16_SD3_DAT4(7) | 1152 DRVCTRL16_SD3_DAT5(7) | 1153 DRVCTRL16_SD3_DAT6(7) | 1154 DRVCTRL16_SD3_DAT7(7) | 1155 DRVCTRL16_SD3_DS(7); 1156 pfc_reg_write(PFC_DRVCTRL16, reg); 1157 1158 reg = mmio_read_32(PFC_DRVCTRL17); 1159 reg = (reg & DRVCTRL17_MASK) | 1160 DRVCTRL17_SD0_CD(7) | 1161 DRVCTRL17_SD0_WP(7) | 1162 DRVCTRL17_SD1_CD(7) | 1163 DRVCTRL17_SD1_WP(7) | 1164 DRVCTRL17_SCK0(7) | 1165 DRVCTRL17_RX0(7) | 1166 DRVCTRL17_TX0(7) | 1167 DRVCTRL17_CTS0(7); 1168 pfc_reg_write(PFC_DRVCTRL17, reg); 1169 1170 reg = mmio_read_32(PFC_DRVCTRL18); 1171 reg = (reg & DRVCTRL18_MASK) | 1172 DRVCTRL18_RTS0_TANS(7) | 1173 DRVCTRL18_RX1(7) | 1174 DRVCTRL18_TX1(7) | 1175 DRVCTRL18_CTS1(7) | 1176 DRVCTRL18_RTS1_TANS(7) | 1177 DRVCTRL18_SCK2(7) | 1178 DRVCTRL18_TX2(7) | 1179 DRVCTRL18_RX2(7); 1180 pfc_reg_write(PFC_DRVCTRL18, reg); 1181 1182 reg = mmio_read_32(PFC_DRVCTRL19); 1183 reg = (reg & DRVCTRL19_MASK) | 1184 DRVCTRL19_HSCK0(7) | 1185 DRVCTRL19_HRX0(7) | 1186 DRVCTRL19_HTX0(7) | 1187 DRVCTRL19_HCTS0(7) | 1188 DRVCTRL19_HRTS0(7) | 1189 DRVCTRL19_MSIOF0_SCK(7) | 1190 DRVCTRL19_MSIOF0_SYNC(7) | 1191 DRVCTRL19_MSIOF0_SS1(7); 1192 pfc_reg_write(PFC_DRVCTRL19, reg); 1193 1194 reg = mmio_read_32(PFC_DRVCTRL20); 1195 reg = (reg & DRVCTRL20_MASK) | 1196 DRVCTRL20_MSIOF0_TXD(7) | 1197 DRVCTRL20_MSIOF0_SS2(7) | 1198 DRVCTRL20_MSIOF0_RXD(7) | 1199 DRVCTRL20_MLB_CLK(7) | 1200 DRVCTRL20_MLB_SIG(7) | 1201 DRVCTRL20_MLB_DAT(7) | 1202 DRVCTRL20_MLB_REF(7) | 1203 DRVCTRL20_SSI_SCK0129(7); 1204 pfc_reg_write(PFC_DRVCTRL20, reg); 1205 1206 reg = mmio_read_32(PFC_DRVCTRL21); 1207 reg = (reg & DRVCTRL21_MASK) | 1208 DRVCTRL21_SSI_WS0129(7) | 1209 DRVCTRL21_SSI_SDATA0(7) | 1210 DRVCTRL21_SSI_SDATA1(7) | 1211 DRVCTRL21_SSI_SDATA2(7) | 1212 DRVCTRL21_SSI_SCK34(7) | 1213 DRVCTRL21_SSI_WS34(7) | 1214 DRVCTRL21_SSI_SDATA3(7) | 1215 DRVCTRL21_SSI_SCK4(7); 1216 pfc_reg_write(PFC_DRVCTRL21, reg); 1217 1218 reg = mmio_read_32(PFC_DRVCTRL22); 1219 reg = (reg & DRVCTRL22_MASK) | 1220 DRVCTRL22_SSI_WS4(7) | 1221 DRVCTRL22_SSI_SDATA4(7) | 1222 DRVCTRL22_SSI_SCK5(7) | 1223 DRVCTRL22_SSI_WS5(7) | 1224 DRVCTRL22_SSI_SDATA5(7) | 1225 DRVCTRL22_SSI_SCK6(7) | 1226 DRVCTRL22_SSI_WS6(7) | 1227 DRVCTRL22_SSI_SDATA6(7); 1228 pfc_reg_write(PFC_DRVCTRL22, reg); 1229 1230 reg = mmio_read_32(PFC_DRVCTRL23); 1231 reg = (reg & DRVCTRL23_MASK) | 1232 DRVCTRL23_SSI_SCK78(7) | 1233 DRVCTRL23_SSI_WS78(7) | 1234 DRVCTRL23_SSI_SDATA7(7) | 1235 DRVCTRL23_SSI_SDATA8(7) | 1236 DRVCTRL23_SSI_SDATA9(7) | 1237 DRVCTRL23_AUDIO_CLKA(7) | 1238 DRVCTRL23_AUDIO_CLKB(7) | 1239 DRVCTRL23_USB0_PWEN(7); 1240 pfc_reg_write(PFC_DRVCTRL23, reg); 1241 1242 reg = mmio_read_32(PFC_DRVCTRL24); 1243 reg = (reg & DRVCTRL24_MASK) | 1244 DRVCTRL24_USB0_OVC(7) | 1245 DRVCTRL24_USB1_PWEN(7) | 1246 DRVCTRL24_USB1_OVC(7) | 1247 DRVCTRL24_USB30_PWEN(7) | 1248 DRVCTRL24_USB30_OVC(7) | 1249 DRVCTRL24_USB31_PWEN(7) | 1250 DRVCTRL24_USB31_OVC(7); 1251 pfc_reg_write(PFC_DRVCTRL24, reg); 1252 1253 /* initialize LSI pin pull-up/down control */ 1254 pfc_reg_write(PFC_PUD0, 0x00005FBFU); 1255 pfc_reg_write(PFC_PUD1, 0x00300EFEU); 1256 pfc_reg_write(PFC_PUD2, 0x330001E6U); 1257 pfc_reg_write(PFC_PUD3, 0x000002E0U); 1258 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U); 1259 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U); 1260 pfc_reg_write(PFC_PUD6, 0x00000055U); 1261 1262 /* initialize LSI pin pull-enable register */ 1263 pfc_reg_write(PFC_PUEN0, 0x00000FFFU); 1264 pfc_reg_write(PFC_PUEN1, 0x00100234U); 1265 pfc_reg_write(PFC_PUEN2, 0x000004C4U); 1266 pfc_reg_write(PFC_PUEN3, 0x00000200U); 1267 pfc_reg_write(PFC_PUEN4, 0x3E000000U); 1268 pfc_reg_write(PFC_PUEN5, 0x1F000805U); 1269 pfc_reg_write(PFC_PUEN6, 0x00000006U); 1270 1271 /* initialize positive/negative logic select */ 1272 mmio_write_32(GPIO_POSNEG0, 0x00000000U); 1273 mmio_write_32(GPIO_POSNEG1, 0x00000000U); 1274 mmio_write_32(GPIO_POSNEG2, 0x00000000U); 1275 mmio_write_32(GPIO_POSNEG3, 0x00000000U); 1276 mmio_write_32(GPIO_POSNEG4, 0x00000000U); 1277 mmio_write_32(GPIO_POSNEG5, 0x00000000U); 1278 mmio_write_32(GPIO_POSNEG6, 0x00000000U); 1279 mmio_write_32(GPIO_POSNEG7, 0x00000000U); 1280 1281 /* initialize general IO/interrupt switching */ 1282 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); 1283 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); 1284 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); 1285 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); 1286 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); 1287 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); 1288 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); 1289 mmio_write_32(GPIO_IOINTSEL7, 0x00000000U); 1290 1291 /* initialize general output register */ 1292 mmio_write_32(GPIO_OUTDT0, 0x00000001U); 1293 mmio_write_32(GPIO_OUTDT1, 0x00000000U); 1294 mmio_write_32(GPIO_OUTDT2, 0x00000400U); 1295 mmio_write_32(GPIO_OUTDT3, 0x00000000U); 1296 mmio_write_32(GPIO_OUTDT4, 0x00000000U); 1297 mmio_write_32(GPIO_OUTDT5, 0x00000000U); 1298 mmio_write_32(GPIO_OUTDT6, 0x00003800U); 1299 mmio_write_32(GPIO_OUTDT7, 0x00000003U); 1300 1301 /* initialize general input/output switching */ 1302 mmio_write_32(GPIO_INOUTSEL0, 0x00000001U); 1303 mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U); 1304 mmio_write_32(GPIO_INOUTSEL2, 0x00000418U); 1305 mmio_write_32(GPIO_INOUTSEL3, 0x00002000U); 1306 mmio_write_32(GPIO_INOUTSEL4, 0x00000040U); 1307 mmio_write_32(GPIO_INOUTSEL5, 0x00000208U); 1308 mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U); 1309 mmio_write_32(GPIO_INOUTSEL7, 0x00000003U); 1310 } 1311