1 /* 2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <lib/mmio.h> 10 11 #include "pfc_init_g2e.h" 12 #include "rcar_def.h" 13 14 #include "../pfc_regs.h" 15 16 /* PFC */ 17 #define GPSR0_SDA4 BIT(17) 18 #define GPSR0_SCL4 BIT(16) 19 #define GPSR0_D15 BIT(15) 20 #define GPSR0_D14 BIT(14) 21 #define GPSR0_D13 BIT(13) 22 #define GPSR0_D12 BIT(12) 23 #define GPSR0_D11 BIT(11) 24 #define GPSR0_D10 BIT(10) 25 #define GPSR0_D9 BIT(9) 26 #define GPSR0_D8 BIT(8) 27 #define GPSR0_D7 BIT(7) 28 #define GPSR0_D6 BIT(6) 29 #define GPSR0_D5 BIT(5) 30 #define GPSR0_D4 BIT(4) 31 #define GPSR0_D3 BIT(3) 32 #define GPSR0_D2 BIT(2) 33 #define GPSR0_D1 BIT(1) 34 #define GPSR0_D0 BIT(0) 35 #define GPSR1_WE0 BIT(22) 36 #define GPSR1_CS0 BIT(21) 37 #define GPSR1_CLKOUT BIT(20) 38 #define GPSR1_A19 BIT(19) 39 #define GPSR1_A18 BIT(18) 40 #define GPSR1_A17 BIT(17) 41 #define GPSR1_A16 BIT(16) 42 #define GPSR1_A15 BIT(15) 43 #define GPSR1_A14 BIT(14) 44 #define GPSR1_A13 BIT(13) 45 #define GPSR1_A12 BIT(12) 46 #define GPSR1_A11 BIT(11) 47 #define GPSR1_A10 BIT(10) 48 #define GPSR1_A9 BIT(9) 49 #define GPSR1_A8 BIT(8) 50 #define GPSR1_A7 BIT(7) 51 #define GPSR1_A6 BIT(6) 52 #define GPSR1_A5 BIT(5) 53 #define GPSR1_A4 BIT(4) 54 #define GPSR1_A3 BIT(3) 55 #define GPSR1_A2 BIT(2) 56 #define GPSR1_A1 BIT(1) 57 #define GPSR1_A0 BIT(0) 58 #define GPSR2_BIT27_REVERSED BIT(27) 59 #define GPSR2_BIT26_REVERSED BIT(26) 60 #define GPSR2_EX_WAIT0 BIT(25) 61 #define GPSR2_RD_WR BIT(24) 62 #define GPSR2_RD BIT(23) 63 #define GPSR2_BS BIT(22) 64 #define GPSR2_AVB_PHY_INT BIT(21) 65 #define GPSR2_AVB_TXCREFCLK BIT(20) 66 #define GPSR2_AVB_RD3 BIT(19) 67 #define GPSR2_AVB_RD2 BIT(18) 68 #define GPSR2_AVB_RD1 BIT(17) 69 #define GPSR2_AVB_RD0 BIT(16) 70 #define GPSR2_AVB_RXC BIT(15) 71 #define GPSR2_AVB_RX_CTL BIT(14) 72 #define GPSR2_RPC_RESET BIT(13) 73 #define GPSR2_RPC_RPC_INT BIT(12) 74 #define GPSR2_QSPI1_SSL BIT(11) 75 #define GPSR2_QSPI1_IO3 BIT(10) 76 #define GPSR2_QSPI1_IO2 BIT(9) 77 #define GPSR2_QSPI1_MISO_IO1 BIT(8) 78 #define GPSR2_QSPI1_MOSI_IO0 BIT(7) 79 #define GPSR2_QSPI1_SPCLK BIT(6) 80 #define GPSR2_QSPI0_SSL BIT(5) 81 #define GPSR2_QSPI0_IO3 BIT(4) 82 #define GPSR2_QSPI0_IO2 BIT(3) 83 #define GPSR2_QSPI0_MISO_IO1 BIT(2) 84 #define GPSR2_QSPI0_MOSI_IO0 BIT(1) 85 #define GPSR2_QSPI0_SPCLK BIT(0) 86 #define GPSR3_SD1_WP BIT(15) 87 #define GPSR3_SD1_CD BIT(14) 88 #define GPSR3_SD0_WP BIT(13) 89 #define GPSR3_SD0_CD BIT(12) 90 #define GPSR3_SD1_DAT3 BIT(11) 91 #define GPSR3_SD1_DAT2 BIT(10) 92 #define GPSR3_SD1_DAT1 BIT(9) 93 #define GPSR3_SD1_DAT0 BIT(8) 94 #define GPSR3_SD1_CMD BIT(7) 95 #define GPSR3_SD1_CLK BIT(6) 96 #define GPSR3_SD0_DAT3 BIT(5) 97 #define GPSR3_SD0_DAT2 BIT(4) 98 #define GPSR3_SD0_DAT1 BIT(3) 99 #define GPSR3_SD0_DAT0 BIT(2) 100 #define GPSR3_SD0_CMD BIT(1) 101 #define GPSR3_SD0_CLK BIT(0) 102 #define GPSR4_SD3_DS BIT(10) 103 #define GPSR4_SD3_DAT7 BIT(9) 104 #define GPSR4_SD3_DAT6 BIT(8) 105 #define GPSR4_SD3_DAT5 BIT(7) 106 #define GPSR4_SD3_DAT4 BIT(6) 107 #define GPSR4_SD3_DAT3 BIT(5) 108 #define GPSR4_SD3_DAT2 BIT(4) 109 #define GPSR4_SD3_DAT1 BIT(3) 110 #define GPSR4_SD3_DAT0 BIT(2) 111 #define GPSR4_SD3_CMD BIT(1) 112 #define GPSR4_SD3_CLK BIT(0) 113 #define GPSR5_MLB_DAT BIT(19) 114 #define GPSR5_MLB_SIG BIT(18) 115 #define GPSR5_MLB_CLK BIT(17) 116 #define GPSR5_SSI_SDATA9 BIT(16) 117 #define GPSR5_MSIOF0_SS2 BIT(15) 118 #define GPSR5_MSIOF0_SS1 BIT(14) 119 #define GPSR5_MSIOF0_SYNC BIT(13) 120 #define GPSR5_MSIOF0_TXD BIT(12) 121 #define GPSR5_MSIOF0_RXD BIT(11) 122 #define GPSR5_MSIOF0_SCK BIT(10) 123 #define GPSR5_RX2_A BIT(9) 124 #define GPSR5_TX2_A BIT(8) 125 #define GPSR5_SCK2_A BIT(7) 126 #define GPSR5_TX1 BIT(6) 127 #define GPSR5_RX1 BIT(5) 128 #define GPSR5_RTS0_A BIT(4) 129 #define GPSR5_CTS0_A BIT(3) 130 #define GPSR5_TX0_A BIT(2) 131 #define GPSR5_RX0_A BIT(1) 132 #define GPSR5_SCK0_A BIT(0) 133 #define GPSR6_USB30_PWEN BIT(17) 134 #define GPSR6_SSI_SDATA6 BIT(16) 135 #define GPSR6_SSI_WS6 BIT(15) 136 #define GPSR6_SSI_SCK6 BIT(14) 137 #define GPSR6_SSI_SDATA5 BIT(13) 138 #define GPSR6_SSI_WS5 BIT(12) 139 #define GPSR6_SSI_SCK5 BIT(11) 140 #define GPSR6_SSI_SDATA4 BIT(10) 141 #define GPSR6_USB30_OVC BIT(9) 142 #define GPSR6_AUDIO_CLKA BIT(8) 143 #define GPSR6_SSI_SDATA3 BIT(7) 144 #define GPSR6_SSI_WS349 BIT(6) 145 #define GPSR6_SSI_SCK349 BIT(5) 146 #define GPSR6_SSI_SDATA2 BIT(4) 147 #define GPSR6_SSI_SDATA1 BIT(3) 148 #define GPSR6_SSI_SDATA0 BIT(2) 149 #define GPSR6_SSI_WS01239 BIT(1) 150 #define GPSR6_SSI_SCK01239 BIT(0) 151 152 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) 153 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) 154 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) 155 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) 156 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) 157 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) 158 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) 159 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) 160 161 #define POCCTRL0_MASK (0x0007F000U) 162 #define POC_SD3_DS_33V BIT(29) 163 #define POC_SD3_DAT7_33V BIT(28) 164 #define POC_SD3_DAT6_33V BIT(27) 165 #define POC_SD3_DAT5_33V BIT(26) 166 #define POC_SD3_DAT4_33V BIT(25) 167 #define POC_SD3_DAT3_33V BIT(24) 168 #define POC_SD3_DAT2_33V BIT(23) 169 #define POC_SD3_DAT1_33V BIT(22) 170 #define POC_SD3_DAT0_33V BIT(21) 171 #define POC_SD3_CMD_33V BIT(20) 172 #define POC_SD3_CLK_33V BIT(19) 173 #define POC_SD1_DAT3_33V BIT(11) 174 #define POC_SD1_DAT2_33V BIT(10) 175 #define POC_SD1_DAT1_33V BIT(9) 176 #define POC_SD1_DAT0_33V BIT(8) 177 #define POC_SD1_CMD_33V BIT(7) 178 #define POC_SD1_CLK_33V BIT(6) 179 #define POC_SD0_DAT3_33V BIT(5) 180 #define POC_SD0_DAT2_33V BIT(4) 181 #define POC_SD0_DAT1_33V BIT(3) 182 #define POC_SD0_DAT0_33V BIT(2) 183 #define POC_SD0_CMD_33V BIT(1) 184 #define POC_SD0_CLK_33V BIT(0) 185 186 #define POCCTRL2_MASK (0xFFFFFFFEU) 187 #define POC2_VREF_33V BIT(0) 188 189 #define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U) 190 #define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U) 191 #define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U) 192 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U) 193 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U) 194 #define MOD_SEL0_FM_A ((uint32_t)0U << 26U) 195 #define MOD_SEL0_FM_B ((uint32_t)1U << 26U) 196 #define MOD_SEL0_FM_C ((uint32_t)2U << 26U) 197 #define MOD_SEL0_FSO_A ((uint32_t)0U << 25U) 198 #define MOD_SEL0_FSO_B ((uint32_t)1U << 25U) 199 #define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U) 200 #define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U) 201 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U) 202 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U) 203 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U) 204 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U) 205 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) 206 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) 207 #define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U) 208 #define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U) 209 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U) 210 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U) 211 #define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U) 212 #define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U) 213 #define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U) 214 #define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U) 215 #define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U) 216 #define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U) 217 #define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U) 218 #define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U) 219 #define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U) 220 #define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U) 221 #define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U) 222 #define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U) 223 #define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U) 224 #define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U) 225 #define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U) 226 #define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U) 227 #define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U) 228 #define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U) 229 #define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U) 230 #define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U) 231 #define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U) 232 #define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U) 233 #define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U) 234 #define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U) 235 #define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U) 236 #define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U) 237 #define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U) 238 #define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U) 239 #define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U) 240 #define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U) 241 #define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U) 242 #define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U) 243 #define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U) 244 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U) 245 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U) 246 #define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U) 247 #define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U) 248 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U) 249 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U) 250 #define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U) 251 #define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U) 252 #define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U) 253 #define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U) 254 #define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U) 255 #define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U) 256 #define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U) 257 #define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U) 258 #define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U) 259 #define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U) 260 #define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U) 261 #define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U) 262 #define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U) 263 #define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U) 264 #define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U) 265 #define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U) 266 #define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U) 267 #define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U) 268 #define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U) 269 #define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U) 270 #define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U) 271 #define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U) 272 #define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U) 273 #define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U) 274 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) 275 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) 276 #define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U) 277 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U) 278 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U) 279 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U) 280 #define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U) 281 #define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U) 282 #define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U) 283 #define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U) 284 #define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U) 285 #define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U) 286 #define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U) 287 #define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U) 288 #define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U) 289 #define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U) 290 #define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U) 291 #define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U) 292 293 static void pfc_reg_write(uint32_t addr, uint32_t data) 294 { 295 mmio_write_32(PFC_PMMR, ~data); 296 mmio_write_32((uintptr_t)addr, data); 297 } 298 299 void pfc_init_g2e(void) 300 { 301 uint32_t reg; 302 303 /* initialize module select */ 304 pfc_reg_write(PFC_MOD_SEL0, 305 MOD_SEL0_ADGB_A | 306 MOD_SEL0_DRIF0_A | 307 MOD_SEL0_FM_A | 308 MOD_SEL0_FSO_A | 309 MOD_SEL0_HSCIF0_A | 310 MOD_SEL0_HSCIF1_A | 311 MOD_SEL0_HSCIF2_A | 312 MOD_SEL0_I2C1_A | 313 MOD_SEL0_I2C2_A | 314 MOD_SEL0_NDFC_A | 315 MOD_SEL0_PWM0_A | 316 MOD_SEL0_PWM1_A | 317 MOD_SEL0_PWM2_A | 318 MOD_SEL0_PWM3_A | 319 MOD_SEL0_PWM4_A | 320 MOD_SEL0_PWM5_A | 321 MOD_SEL0_PWM6_A | 322 MOD_SEL0_REMOCON_A | 323 MOD_SEL0_SCIF_A | 324 MOD_SEL0_SCIF0_A | 325 MOD_SEL0_SCIF2_A | 326 MOD_SEL0_SPEED_PULSE_IF_A); 327 328 pfc_reg_write(PFC_MOD_SEL1, 329 MOD_SEL1_SIMCARD_A | 330 MOD_SEL1_SSI2_A | 331 MOD_SEL1_TIMER_TMU_A | 332 MOD_SEL1_USB20_CH0_B | 333 MOD_SEL1_DRIF2_A | 334 MOD_SEL1_DRIF3_A | 335 MOD_SEL1_HSCIF3_C | 336 MOD_SEL1_HSCIF4_B | 337 MOD_SEL1_I2C6_A | 338 MOD_SEL1_I2C7_A | 339 MOD_SEL1_MSIOF2_A | 340 MOD_SEL1_MSIOF3_A | 341 MOD_SEL1_SCIF3_A | 342 MOD_SEL1_SCIF4_A | 343 MOD_SEL1_SCIF5_A | 344 MOD_SEL1_VIN4_A | 345 MOD_SEL1_VIN5_A | 346 MOD_SEL1_ADGC_A | 347 MOD_SEL1_SSI9_A); 348 349 /* initialize peripheral function select */ 350 pfc_reg_write(PFC_IPSR0, 351 IPSR_28_FUNC(2) | /* HRX4_B */ 352 IPSR_24_FUNC(2) | /* HTX4_B */ 353 IPSR_20_FUNC(0) | /* QSPI1_SPCLK */ 354 IPSR_16_FUNC(0) | /* QSPI0_IO3 */ 355 IPSR_12_FUNC(0) | /* QSPI0_IO2 */ 356 IPSR_8_FUNC(0) | /* QSPI0_MISO/IO1 */ 357 IPSR_4_FUNC(0) | /* QSPI0_MOSI/IO0 */ 358 IPSR_0_FUNC(0)); /* QSPI0_SPCLK */ 359 360 pfc_reg_write(PFC_IPSR1, 361 IPSR_28_FUNC(0) | /* AVB_RD2 */ 362 IPSR_24_FUNC(0) | /* AVB_RD1 */ 363 IPSR_20_FUNC(0) | /* AVB_RD0 */ 364 IPSR_16_FUNC(0) | /* RPC_RESET# */ 365 IPSR_12_FUNC(0) | /* RPC_INT# */ 366 IPSR_8_FUNC(0) | /* QSPI1_SSL */ 367 IPSR_4_FUNC(2) | /* HRX3_C */ 368 IPSR_0_FUNC(2)); /* HTX3_C */ 369 370 pfc_reg_write(PFC_IPSR2, 371 IPSR_28_FUNC(1) | /* IRQ0 */ 372 IPSR_24_FUNC(0) | 373 IPSR_20_FUNC(0) | 374 IPSR_16_FUNC(2) | /* AVB_LINK */ 375 IPSR_12_FUNC(0) | 376 IPSR_8_FUNC(0) | /* AVB_MDC */ 377 IPSR_4_FUNC(0) | /* AVB_MDIO */ 378 IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */ 379 380 pfc_reg_write(PFC_IPSR3, 381 IPSR_28_FUNC(5) | /* DU_HSYNC */ 382 IPSR_24_FUNC(0) | 383 IPSR_20_FUNC(0) | 384 IPSR_16_FUNC(0) | 385 IPSR_12_FUNC(5) | /* DU_DG4 */ 386 IPSR_8_FUNC(5) | /* DU_DOTCLKOUT0 */ 387 IPSR_4_FUNC(5) | /* DU_DISP */ 388 IPSR_0_FUNC(1)); /* IRQ1 */ 389 390 pfc_reg_write(PFC_IPSR4, 391 IPSR_28_FUNC(5) | /* DU_DB5 */ 392 IPSR_24_FUNC(5) | /* DU_DB4 */ 393 IPSR_20_FUNC(5) | /* DU_DB3 */ 394 IPSR_16_FUNC(5) | /* DU_DB2 */ 395 IPSR_12_FUNC(5) | /* DU_DG6 */ 396 IPSR_8_FUNC(5) | /* DU_VSYNC */ 397 IPSR_4_FUNC(5) | /* DU_DG5 */ 398 IPSR_0_FUNC(5)); /* DU_DG7 */ 399 400 pfc_reg_write(PFC_IPSR5, 401 IPSR_28_FUNC(5) | /* DU_DR3 */ 402 IPSR_24_FUNC(5) | /* DU_DB7 */ 403 IPSR_20_FUNC(5) | /* DU_DR2 */ 404 IPSR_16_FUNC(5) | /* DU_DR1 */ 405 IPSR_12_FUNC(5) | /* DU_DR0 */ 406 IPSR_8_FUNC(5) | /* DU_DB1 */ 407 IPSR_4_FUNC(5) | /* DU_DB0 */ 408 IPSR_0_FUNC(5)); /* DU_DB6 */ 409 410 pfc_reg_write(PFC_IPSR6, 411 IPSR_28_FUNC(5) | /* DU_DG1 */ 412 IPSR_24_FUNC(5) | /* DU_DG0 */ 413 IPSR_20_FUNC(5) | /* DU_DR7 */ 414 IPSR_16_FUNC(1) | /* CANFD1_RX */ 415 IPSR_12_FUNC(5) | /* DU_DR6 */ 416 IPSR_8_FUNC(5) | /* DU_DR5 */ 417 IPSR_4_FUNC(1) | /* CANFD1_TX */ 418 IPSR_0_FUNC(5)); /* DU_DR4 */ 419 420 pfc_reg_write(PFC_IPSR7, 421 IPSR_28_FUNC(0) | /* SD0_CLK */ 422 IPSR_24_FUNC(0) | 423 IPSR_20_FUNC(5) | /* DU_DOTCLKIN0 */ 424 IPSR_16_FUNC(5) | /* DU_DG3 */ 425 IPSR_12_FUNC(1) | /* CAN_CLK */ 426 IPSR_8_FUNC(1) | /* CANFD0_RX */ 427 IPSR_4_FUNC(1) | /* CANFD0_TX */ 428 IPSR_0_FUNC(5)); /* DU_DG2 */ 429 430 pfc_reg_write(PFC_IPSR8, 431 IPSR_28_FUNC(0) | /* SD1_DAT0 */ 432 IPSR_24_FUNC(0) | /* SD1_CMD */ 433 IPSR_20_FUNC(0) | /* SD1_CLK */ 434 IPSR_16_FUNC(0) | /* SD0_DAT3 */ 435 IPSR_12_FUNC(0) | /* SD0_DAT2 */ 436 IPSR_8_FUNC(0) | /* SD0_DAT1 */ 437 IPSR_4_FUNC(0) | /* SD0_DAT0 */ 438 IPSR_0_FUNC(0)); /* SD0_CMD */ 439 440 pfc_reg_write(PFC_IPSR9, 441 IPSR_28_FUNC(0) | /* SD3_DAT2 */ 442 IPSR_24_FUNC(0) | /* SD3_DAT1 */ 443 IPSR_20_FUNC(0) | /* SD3_DAT0 */ 444 IPSR_16_FUNC(0) | /* SD3_CMD */ 445 IPSR_12_FUNC(0) | /* SD3_CLK */ 446 IPSR_8_FUNC(0) | /* SD1_DAT3 */ 447 IPSR_4_FUNC(0) | /* SD1_DAT2 */ 448 IPSR_0_FUNC(0)); /* SD1_DAT1 */ 449 450 pfc_reg_write(PFC_IPSR10, 451 IPSR_24_FUNC(0) | /* SD0_CD */ 452 IPSR_20_FUNC(0) | /* SD3_DS */ 453 IPSR_16_FUNC(0) | /* SD3_DAT7 */ 454 IPSR_12_FUNC(0) | /* SD3_DAT6 */ 455 IPSR_8_FUNC(0) | /* SD3_DAT5 */ 456 IPSR_4_FUNC(0) | /* SD3_DAT4 */ 457 IPSR_0_FUNC(0)); /* SD3_DAT3 */ 458 459 pfc_reg_write(PFC_IPSR11, 460 IPSR_28_FUNC(0) | 461 IPSR_24_FUNC(8) | /* USB0_ID */ 462 IPSR_20_FUNC(2) | /* AUDIO_CLKOUT1_A */ 463 IPSR_16_FUNC(0) | /* CTS0#_A */ 464 IPSR_12_FUNC(0) | 465 IPSR_8_FUNC(0) | 466 IPSR_4_FUNC(0) | /* SD1_WP */ 467 IPSR_0_FUNC(0)); /* SD1_CD */ 468 469 pfc_reg_write(PFC_IPSR12, 470 IPSR_28_FUNC(0) | 471 IPSR_24_FUNC(0) | 472 IPSR_20_FUNC(0) | 473 IPSR_16_FUNC(0) | 474 IPSR_12_FUNC(0) | /* RX2_A */ 475 IPSR_8_FUNC(0) | /* TX2_A */ 476 IPSR_4_FUNC(0) | /* SCK2_A */ 477 IPSR_0_FUNC(0)); 478 479 pfc_reg_write(PFC_IPSR13, 480 IPSR_28_FUNC(0) | 481 IPSR_24_FUNC(0) | 482 IPSR_20_FUNC(0) | 483 IPSR_16_FUNC(4) | /* SDA1_B */ 484 IPSR_12_FUNC(4) | /* SCL1_B */ 485 IPSR_8_FUNC(0) | /* SSI_SDATA9 */ 486 IPSR_4_FUNC(1) | /* HTX2_A */ 487 IPSR_0_FUNC(1)); /* HRX2_A */ 488 489 pfc_reg_write(PFC_IPSR14, 490 IPSR_28_FUNC(0) | /* SSI_SCK5 */ 491 IPSR_24_FUNC(0) | /* SSI_SDATA4 */ 492 IPSR_20_FUNC(0) | /* SSI_SDATA3 */ 493 IPSR_16_FUNC(0) | /* SSI_WS349 */ 494 IPSR_12_FUNC(0) | /* SSI_SCK349 */ 495 IPSR_8_FUNC(0) | 496 IPSR_4_FUNC(0) | /* SSI_SDATA1 */ 497 IPSR_0_FUNC(0));/* SSI_SDATA0 */ 498 499 pfc_reg_write(PFC_IPSR15, 500 IPSR_28_FUNC(0) | /* USB30_OVC */ 501 IPSR_24_FUNC(0) | /* USB30_PWEN */ 502 IPSR_20_FUNC(0) | /* AUDIO_CLKA */ 503 IPSR_16_FUNC(1) | /* HRTS2#_A */ 504 IPSR_12_FUNC(1) | /* HCTS2#_A */ 505 IPSR_8_FUNC(3) | /* TPU0TO1 */ 506 IPSR_4_FUNC(3) | /* TPU0TO0 */ 507 IPSR_0_FUNC(0)); /* SSI_WS5 */ 508 509 /* initialize GPIO/peripheral function select */ 510 pfc_reg_write(PFC_GPSR0, 511 GPSR0_SCL4 | 512 GPSR0_D15 | 513 GPSR0_D14 | 514 GPSR0_D13 | 515 GPSR0_D12 | 516 GPSR0_D11 | 517 GPSR0_D10 | 518 GPSR0_D9 | 519 GPSR0_D8 | 520 GPSR0_D7 | 521 GPSR0_D6 | 522 GPSR0_D5 | 523 GPSR0_D4 | 524 GPSR0_D3 | 525 GPSR0_D2 | 526 GPSR0_D1 | 527 GPSR0_D0); 528 529 pfc_reg_write(PFC_GPSR1, 530 GPSR1_WE0 | 531 GPSR1_CS0 | 532 GPSR1_A19 | 533 GPSR1_A18 | 534 GPSR1_A17 | 535 GPSR1_A16 | 536 GPSR1_A15 | 537 GPSR1_A14 | 538 GPSR1_A13 | 539 GPSR1_A12 | 540 GPSR1_A11 | 541 GPSR1_A10 | 542 GPSR1_A9 | 543 GPSR1_A8 | 544 GPSR1_A4 | 545 GPSR1_A3 | 546 GPSR1_A2 | 547 GPSR1_A1 | 548 GPSR1_A0); 549 550 pfc_reg_write(PFC_GPSR2, 551 GPSR2_BIT27_REVERSED | 552 GPSR2_BIT26_REVERSED | 553 GPSR2_AVB_PHY_INT | 554 GPSR2_AVB_TXCREFCLK | 555 GPSR2_AVB_RD3 | 556 GPSR2_AVB_RD2 | 557 GPSR2_AVB_RD1 | 558 GPSR2_AVB_RD0 | 559 GPSR2_AVB_RXC | 560 GPSR2_AVB_RX_CTL | 561 GPSR2_RPC_RESET | 562 GPSR2_RPC_RPC_INT | 563 GPSR2_QSPI1_IO3 | 564 GPSR2_QSPI1_IO2 | 565 GPSR2_QSPI1_MISO_IO1 | 566 GPSR2_QSPI1_MOSI_IO0 | 567 GPSR2_QSPI0_SSL | 568 GPSR2_QSPI0_IO3 | 569 GPSR2_QSPI0_IO2 | 570 GPSR2_QSPI0_MISO_IO1 | 571 GPSR2_QSPI0_MOSI_IO0 | 572 GPSR2_QSPI0_SPCLK); 573 574 pfc_reg_write(PFC_GPSR3, 575 GPSR3_SD0_CD | 576 GPSR3_SD1_DAT3 | 577 GPSR3_SD1_DAT2 | 578 GPSR3_SD1_DAT1 | 579 GPSR3_SD1_DAT0 | 580 GPSR3_SD1_CMD | 581 GPSR3_SD1_CLK | 582 GPSR3_SD0_DAT3 | 583 GPSR3_SD0_DAT2 | 584 GPSR3_SD0_DAT1 | 585 GPSR3_SD0_DAT0 | 586 GPSR3_SD0_CMD | 587 GPSR3_SD0_CLK); 588 589 pfc_reg_write(PFC_GPSR4, 590 GPSR4_SD3_DAT3 | 591 GPSR4_SD3_DAT2 | 592 GPSR4_SD3_DAT1 | 593 GPSR4_SD3_DAT0 | 594 GPSR4_SD3_CMD | 595 GPSR4_SD3_CLK); 596 597 pfc_reg_write(PFC_GPSR5, 598 GPSR5_MLB_SIG | 599 GPSR5_MLB_CLK | 600 GPSR5_SSI_SDATA9 | 601 GPSR5_MSIOF0_SS2 | 602 GPSR5_MSIOF0_SS1 | 603 GPSR5_MSIOF0_SYNC | 604 GPSR5_MSIOF0_TXD | 605 GPSR5_MSIOF0_RXD | 606 GPSR5_MSIOF0_SCK | 607 GPSR5_RX2_A | 608 GPSR5_TX2_A | 609 GPSR5_RTS0_A | 610 GPSR5_SCK0_A); 611 612 pfc_reg_write(PFC_GPSR6, 613 GPSR6_USB30_PWEN | 614 GPSR6_SSI_SDATA6 | 615 GPSR6_SSI_WS6 | 616 GPSR6_SSI_SCK6 | 617 GPSR6_SSI_SDATA5 | 618 GPSR6_SSI_SCK5 | 619 GPSR6_SSI_SDATA4 | 620 GPSR6_USB30_OVC | 621 GPSR6_AUDIO_CLKA | 622 GPSR6_SSI_SDATA3 | 623 GPSR6_SSI_WS349 | 624 GPSR6_SSI_SCK349 | 625 GPSR6_SSI_SDATA0 | 626 GPSR6_SSI_WS01239 | 627 GPSR6_SSI_SCK01239); 628 629 /* initialize POC control */ 630 reg = mmio_read_32(PFC_POCCTRL0); 631 reg = (reg & POCCTRL0_MASK) | 632 POC_SD1_DAT3_33V | 633 POC_SD1_DAT2_33V | 634 POC_SD1_DAT1_33V | 635 POC_SD1_DAT0_33V | 636 POC_SD1_CMD_33V | 637 POC_SD1_CLK_33V | 638 POC_SD0_DAT3_33V | 639 POC_SD0_DAT2_33V | 640 POC_SD0_DAT1_33V | 641 POC_SD0_DAT0_33V | 642 POC_SD0_CMD_33V | 643 POC_SD0_CLK_33V; 644 pfc_reg_write(PFC_POCCTRL0, reg); 645 646 reg = mmio_read_32(PFC_POCCTRL2); 647 reg = ((reg & POCCTRL2_MASK) & ~POC2_VREF_33V); 648 pfc_reg_write(PFC_POCCTRL2, reg); 649 650 /* initialize LSI pin pull-up/down control */ 651 pfc_reg_write(PFC_PUD0, 0x00080000U); 652 pfc_reg_write(PFC_PUD1, 0xCE398464U); 653 pfc_reg_write(PFC_PUD2, 0xA4C380F4U); 654 pfc_reg_write(PFC_PUD3, 0x0000079FU); 655 pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU); 656 pfc_reg_write(PFC_PUD5, 0x40000000U); 657 658 /* initialize LSI pin pull-enable register */ 659 pfc_reg_write(PFC_PUEN0, 0x00000000U); 660 pfc_reg_write(PFC_PUEN1, 0x00300000U); 661 pfc_reg_write(PFC_PUEN2, 0x00400074U); 662 pfc_reg_write(PFC_PUEN3, 0x00000000U); 663 pfc_reg_write(PFC_PUEN4, 0x07900600U); 664 pfc_reg_write(PFC_PUEN5, 0x00000000U); 665 666 /* initialize positive/negative logic select */ 667 mmio_write_32(GPIO_POSNEG0, 0x00000000U); 668 mmio_write_32(GPIO_POSNEG1, 0x00000000U); 669 mmio_write_32(GPIO_POSNEG2, 0x00000000U); 670 mmio_write_32(GPIO_POSNEG3, 0x00000000U); 671 mmio_write_32(GPIO_POSNEG4, 0x00000000U); 672 mmio_write_32(GPIO_POSNEG5, 0x00000000U); 673 mmio_write_32(GPIO_POSNEG6, 0x00000000U); 674 675 /* initialize general IO/interrupt switching */ 676 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); 677 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); 678 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); 679 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); 680 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); 681 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); 682 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); 683 684 /* initialize general output register */ 685 mmio_write_32(GPIO_OUTDT0, 0x00000000U); 686 mmio_write_32(GPIO_OUTDT1, 0x00000000U); 687 mmio_write_32(GPIO_OUTDT2, 0x00000000U); 688 mmio_write_32(GPIO_OUTDT3, 0x00006000U); 689 mmio_write_32(GPIO_OUTDT5, 0x00000000U); 690 mmio_write_32(GPIO_OUTDT6, 0x00000000U); 691 692 /* initialize general input/output switching */ 693 mmio_write_32(GPIO_INOUTSEL0, 0x00020000U); 694 mmio_write_32(GPIO_INOUTSEL1, 0x00100000U); 695 mmio_write_32(GPIO_INOUTSEL2, 0x03000000U); 696 mmio_write_32(GPIO_INOUTSEL3, 0x0000E000U); 697 mmio_write_32(GPIO_INOUTSEL4, 0x00000440U); 698 mmio_write_32(GPIO_INOUTSEL5, 0x00080000U); 699 mmio_write_32(GPIO_INOUTSEL6, 0x00000010U); 700 } 701