1 /* 2 * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 11 #include "../qos_common.h" 12 #include "../qos_reg.h" 13 #include "qos_init_m3_v30.h" 14 15 #define RCAR_QOS_VERSION "rev.0.04" 16 17 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */ 18 19 #define QOSWT_WTEN_ENABLE 0x1U 20 21 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U) 22 23 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U 24 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U 25 #define QOSWT_WTREF_SLOT0_EN \ 26 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 27 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 28 #define QOSWT_WTREF_SLOT1_EN \ 29 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 30 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 31 32 #define QOSWT_WTSET0_REQ_SSLOT0 5U 33 #define WT_BASE_SUB_SLOT_NUM0 12U 34 #define QOSWT_WTSET0_PERIOD0_M3_30 \ 35 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U) 36 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 37 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U) 38 39 #define QOSWT_WTSET1_PERIOD1_M3_30 \ 40 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U) 41 #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 42 #define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U) 43 44 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 45 46 #if RCAR_REF_INT == RCAR_REF_DEFAULT 47 #include "qos_init_m3_v30_mstat195.h" 48 #else 49 #include "qos_init_m3_v30_mstat390.h" 50 #endif 51 52 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 53 54 #if RCAR_REF_INT == RCAR_REF_DEFAULT 55 #include "qos_init_m3_v30_qoswt195.h" 56 #else 57 #include "qos_init_m3_v30_qoswt390.h" 58 #endif 59 60 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 61 #endif 62 63 struct rcar_gen3_dbsc_qos_settings m3_v30_qos[] = { 64 /* BUFCAM settings */ 65 { DBSC_DBCAM0CNF1, 0x00043218 }, 66 { DBSC_DBCAM0CNF2, 0x000000F4 }, 67 { DBSC_DBCAM0CNF3, 0x00000000 }, 68 { DBSC_DBSCHCNT0, 0x000F0037 }, 69 { DBSC_DBSCHSZ0, 0x00000001 }, 70 { DBSC_DBSCHRW0, 0x22421111 }, 71 72 /* DDR3 */ 73 { DBSC_SCFCTST2, 0x012F1123 }, 74 75 /* QoS Settings */ 76 { DBSC_DBSCHQOS00, 0x00000F00 }, 77 { DBSC_DBSCHQOS01, 0x00000B00 }, 78 { DBSC_DBSCHQOS02, 0x00000000 }, 79 { DBSC_DBSCHQOS03, 0x00000000 }, 80 { DBSC_DBSCHQOS40, 0x00000300 }, 81 { DBSC_DBSCHQOS41, 0x000002F0 }, 82 { DBSC_DBSCHQOS42, 0x00000200 }, 83 { DBSC_DBSCHQOS43, 0x00000100 }, 84 { DBSC_DBSCHQOS90, 0x00000100 }, 85 { DBSC_DBSCHQOS91, 0x000000F0 }, 86 { DBSC_DBSCHQOS92, 0x000000A0 }, 87 { DBSC_DBSCHQOS93, 0x00000040 }, 88 { DBSC_DBSCHQOS120, 0x00000040 }, 89 { DBSC_DBSCHQOS121, 0x00000030 }, 90 { DBSC_DBSCHQOS122, 0x00000020 }, 91 { DBSC_DBSCHQOS123, 0x00000010 }, 92 { DBSC_DBSCHQOS130, 0x00000100 }, 93 { DBSC_DBSCHQOS131, 0x000000F0 }, 94 { DBSC_DBSCHQOS132, 0x000000A0 }, 95 { DBSC_DBSCHQOS133, 0x00000040 }, 96 { DBSC_DBSCHQOS140, 0x000000C0 }, 97 { DBSC_DBSCHQOS141, 0x000000B0 }, 98 { DBSC_DBSCHQOS142, 0x00000080 }, 99 { DBSC_DBSCHQOS143, 0x00000040 }, 100 { DBSC_DBSCHQOS150, 0x00000040 }, 101 { DBSC_DBSCHQOS151, 0x00000030 }, 102 { DBSC_DBSCHQOS152, 0x00000020 }, 103 { DBSC_DBSCHQOS153, 0x00000010 }, 104 }; 105 106 void qos_init_m3_v30(void) 107 { 108 rcar_qos_dbsc_setting(m3_v30_qos, ARRAY_SIZE(m3_v30_qos), true); 109 110 /* DRAM Split Address mapping */ 111 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH 112 #if RCAR_LSI == RCAR_M3 113 #error "Don't set DRAM Split 4ch(M3)" 114 #else 115 ERROR("DRAM Split 4ch not supported.(M3)"); 116 panic(); 117 #endif 118 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ 119 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) 120 NOTICE("BL2: DRAM Split is 2ch\n"); 121 io_write_32(AXI_ADSPLCR0, 0x00000000U); 122 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT 123 | ADSPLCR0_SPLITSEL(0xFFU) 124 | ADSPLCR0_AREA(0x1DU) 125 | ADSPLCR0_SWP); 126 io_write_32(AXI_ADSPLCR2, 0x00001004U); 127 io_write_32(AXI_ADSPLCR3, 0x00000000U); 128 #else 129 NOTICE("BL2: DRAM Split is OFF\n"); 130 #endif 131 132 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) 133 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 134 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); 135 #endif 136 137 #if RCAR_REF_INT == RCAR_REF_DEFAULT 138 NOTICE("BL2: DRAM refresh interval 1.95 usec\n"); 139 #else 140 NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); 141 #endif 142 143 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 144 NOTICE("BL2: Periodic Write DQ Training\n"); 145 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 146 147 io_write_32(QOSCTRL_RAS, 0x00000044U); 148 io_write_64(QOSCTRL_DANN, 0x0404020002020201UL); 149 io_write_32(QOSCTRL_DANT, 0x0020100AU); 150 io_write_32(QOSCTRL_FSS, 0x0000000AU); 151 io_write_32(QOSCTRL_INSFC, 0x06330001U); 152 io_write_32(QOSCTRL_EARLYR, 0x00000001U); 153 io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ 154 155 /* GPU Boost Mode */ 156 io_write_32(QOSCTRL_STATGEN0, 0x00000001U); 157 158 io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30); 159 io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16))); 160 161 uint32_t i; 162 163 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { 164 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); 165 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); 166 } 167 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { 168 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); 169 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); 170 } 171 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 172 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { 173 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]); 174 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]); 175 } 176 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { 177 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]); 178 io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]); 179 } 180 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 181 182 /* RT bus Leaf setting */ 183 io_write_32(RT_ACT0, 0x00000000U); 184 io_write_32(RT_ACT1, 0x00000000U); 185 186 /* CCI bus Leaf setting */ 187 io_write_32(CPU_ACT0, 0x00000003U); 188 io_write_32(CPU_ACT1, 0x00000003U); 189 io_write_32(CPU_ACT2, 0x00000003U); 190 io_write_32(CPU_ACT3, 0x00000003U); 191 192 io_write_32(QOSCTRL_RAEN, 0x00000001U); 193 194 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 195 /* re-write training setting */ 196 io_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN)); 197 io_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_M3_30 << 16) | (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0)); 198 io_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_M3_30 << 16) | (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1)); 199 200 io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE); 201 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 202 203 io_write_32(QOSCTRL_STATQC, 0x00000001U); 204 #else 205 NOTICE("BL2: QoS is None\n"); 206 207 io_write_32(QOSCTRL_RAEN, 0x00000001U); 208 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 209 } 210