1 /* 2 * Copyright (c) 2015-2024, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 11 #include "../qos_common.h" 12 #include "../qos_reg.h" 13 #include "qos_init_m3_v10.h" 14 15 #define RCAR_QOS_VERSION "rev.0.19" 16 17 #include "qos_init_m3_v10_mstat.h" 18 19 struct rcar_gen3_dbsc_qos_settings m3_v10_qos[] = { 20 /* BUFCAM settings */ 21 /* DBSC_DBCAM0CNF0 not set */ 22 { DBSC_DBCAM0CNF1, 0x00048218U }, 23 { DBSC_DBCAM0CNF2, 0x000000F4 }, 24 { DBSC_DBCAM0CNF3, 0x00000000 }, 25 { DBSC_DBSCHCNT0, 0x080F0037 }, 26 /* DBSC_DBSCHCNT1 not set */ 27 { DBSC_DBSCHSZ0, 0x00000001 }, 28 { DBSC_DBSCHRW0, 0x22421111 }, 29 30 /* DDR3 */ 31 { DBSC_SCFCTST2, 0x012F1123 }, 32 33 /* QoS Settings */ 34 { DBSC_DBSCHQOS00, 0x00000F00 }, 35 { DBSC_DBSCHQOS01, 0x00000B00 }, 36 { DBSC_DBSCHQOS02, 0x00000000 }, 37 { DBSC_DBSCHQOS03, 0x00000000 }, 38 { DBSC_DBSCHQOS40, 0x00000300 }, 39 { DBSC_DBSCHQOS41, 0x000002F0 }, 40 { DBSC_DBSCHQOS42, 0x00000200 }, 41 { DBSC_DBSCHQOS43, 0x00000100 }, 42 { DBSC_DBSCHQOS90, 0x00000300 }, 43 { DBSC_DBSCHQOS91, 0x000002F0 }, 44 { DBSC_DBSCHQOS92, 0x00000200 }, 45 { DBSC_DBSCHQOS93, 0x00000100 }, 46 { DBSC_DBSCHQOS130, 0x00000100 }, 47 { DBSC_DBSCHQOS131, 0x000000F0 }, 48 { DBSC_DBSCHQOS132, 0x000000A0 }, 49 { DBSC_DBSCHQOS133, 0x00000040 }, 50 { DBSC_DBSCHQOS140, 0x000000C0 }, 51 { DBSC_DBSCHQOS141, 0x000000B0 }, 52 { DBSC_DBSCHQOS142, 0x00000080 }, 53 { DBSC_DBSCHQOS143, 0x00000040 }, 54 { DBSC_DBSCHQOS150, 0x00000040 }, 55 { DBSC_DBSCHQOS151, 0x00000030 }, 56 { DBSC_DBSCHQOS152, 0x00000020 }, 57 { DBSC_DBSCHQOS153, 0x00000010 }, 58 }; 59 60 void qos_init_m3_v10(void) 61 { 62 rcar_qos_dbsc_setting(m3_v10_qos, ARRAY_SIZE(m3_v10_qos), false); 63 64 /* DRAM Split Address mapping */ 65 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH 66 #if RCAR_LSI == RCAR_M3 67 #error "Don't set DRAM Split 4ch(M3)" 68 #else 69 ERROR("DRAM Split 4ch not supported.(M3)"); 70 panic(); 71 #endif 72 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ 73 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) 74 NOTICE("BL2: DRAM Split is 2ch\n"); 75 io_write_32(AXI_ADSPLCR0, 0x00000000U); 76 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT 77 | ADSPLCR0_SPLITSEL(0xFFU) 78 | ADSPLCR0_AREA(0x1CU) 79 | ADSPLCR0_SWP); 80 io_write_32(AXI_ADSPLCR2, 0x089A0000U); 81 io_write_32(AXI_ADSPLCR3, 0x00000000U); 82 #else 83 NOTICE("BL2: DRAM Split is OFF\n"); 84 #endif 85 86 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) 87 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 88 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); 89 #endif 90 91 /* Resource Alloc setting */ 92 io_write_32(QOSCTRL_RAS, 0x00000028U); 93 io_write_32(QOSCTRL_FIXTH, 0x000F0005U); 94 io_write_32(QOSCTRL_REGGD, 0x00000000U); 95 io_write_64(QOSCTRL_DANN, 0x0101010102020201UL); 96 io_write_32(QOSCTRL_DANT, 0x00100804U); 97 io_write_32(QOSCTRL_EC, 0x00000000U); 98 io_write_64(QOSCTRL_EMS, 0x0000000000000000UL); 99 io_write_32(QOSCTRL_FSS, 0x000003e8U); 100 io_write_32(QOSCTRL_INSFC, 0xC7840001U); 101 io_write_32(QOSCTRL_BERR, 0x00000000U); 102 io_write_32(QOSCTRL_RACNT0, 0x00000000U); 103 104 /* QOSBW setting */ 105 io_write_32(QOSCTRL_SL_INIT, 106 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK); 107 io_write_32(QOSCTRL_REF_ARS, 0x00330000U); 108 109 /* QOSBW SRAM setting */ 110 uint32_t i; 111 112 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { 113 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); 114 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); 115 } 116 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { 117 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); 118 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); 119 } 120 121 /* 3DG bus Leaf setting */ 122 io_write_32(0xFD820808U, 0x00001234U); 123 io_write_32(0xFD820800U, 0x00000006U); 124 io_write_32(0xFD821800U, 0x00000006U); 125 io_write_32(0xFD822800U, 0x00000006U); 126 io_write_32(0xFD823800U, 0x00000006U); 127 io_write_32(0xFD824800U, 0x00000006U); 128 io_write_32(0xFD825800U, 0x00000006U); 129 io_write_32(0xFD826800U, 0x00000006U); 130 io_write_32(0xFD827800U, 0x00000006U); 131 132 /* RT bus Leaf setting */ 133 io_write_32(0xFFC50800U, 0x00000000U); 134 io_write_32(0xFFC51800U, 0x00000000U); 135 136 /* Resource Alloc start */ 137 io_write_32(QOSCTRL_RAEN, 0x00000001U); 138 139 /* QOSBW start */ 140 io_write_32(QOSCTRL_STATQC, 0x00000001U); 141 #else 142 NOTICE("BL2: QoS is None\n"); 143 144 /* Resource Alloc setting */ 145 io_write_32(QOSCTRL_EC, 0x00000000U); 146 /* Resource Alloc start */ 147 io_write_32(QOSCTRL_RAEN, 0x00000001U); 148 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 149 } 150