1 /* 2 * Copyright (c) 2015-2024, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 11 #include "../qos_common.h" 12 #include "../qos_reg.h" 13 #include "qos_init_h3_v20.h" 14 15 #define RCAR_QOS_VERSION "rev.0.21" 16 17 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */ 18 19 #define QOSWT_WTEN_ENABLE 0x1U 20 21 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 (SL_INIT_SSLOTCLK_H3_20 - 0x5U) 22 23 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U 24 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U 25 #define QOSWT_WTREF_SLOT0_EN \ 26 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 27 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 28 #define QOSWT_WTREF_SLOT1_EN \ 29 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \ 30 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) 31 32 #define QOSWT_WTSET0_REQ_SSLOT0 5U 33 #define WT_BASE_SUB_SLOT_NUM0 12U 34 #define QOSWT_WTSET0_PERIOD0_H3_20 \ 35 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U) 36 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 37 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U) 38 39 #define QOSWT_WTSET1_PERIOD1_H3_20 \ 40 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_20) - 1U) 41 #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U) 42 #define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U) 43 44 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 45 46 #if RCAR_REF_INT == RCAR_REF_DEFAULT 47 #include "qos_init_h3_v20_mstat195.h" 48 #else 49 #include "qos_init_h3_v20_mstat390.h" 50 #endif 51 52 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 53 54 #if RCAR_REF_INT == RCAR_REF_DEFAULT 55 #include "qos_init_h3_v20_qoswt195.h" 56 #else 57 #include "qos_init_h3_v20_qoswt390.h" 58 #endif 59 60 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 61 62 #endif 63 64 struct rcar_gen3_dbsc_qos_settings h3_v20_qos[] = { 65 /* BUFCAM settings */ 66 { DBSC_DBCAM0CNF1, 0x00048218U }, 67 { DBSC_DBCAM0CNF2, 0x000000F4U }, 68 { DBSC_DBCAM0CNF3, 0x00000000U }, 69 { DBSC_DBSCHCNT0, 0x000F0037U }, 70 { DBSC_DBSCHSZ0, 0x00000001U }, 71 { DBSC_DBSCHRW0, 0x22421111U }, 72 73 /* DDR3 */ 74 { DBSC_SCFCTST2, 0x012F1123U }, 75 76 /* QoS Settings */ 77 { DBSC_DBSCHQOS00, 0x00000F00U }, 78 { DBSC_DBSCHQOS01, 0x00000B00U }, 79 { DBSC_DBSCHQOS02, 0x00000000U }, 80 { DBSC_DBSCHQOS03, 0x00000000U }, 81 { DBSC_DBSCHQOS40, 0x00000300U }, 82 { DBSC_DBSCHQOS41, 0x000002F0U }, 83 { DBSC_DBSCHQOS42, 0x00000200U }, 84 { DBSC_DBSCHQOS43, 0x00000100U }, 85 { DBSC_DBSCHQOS90, 0x00000100U }, 86 { DBSC_DBSCHQOS91, 0x000000F0U }, 87 { DBSC_DBSCHQOS92, 0x000000A0U }, 88 { DBSC_DBSCHQOS93, 0x00000040U }, 89 { DBSC_DBSCHQOS120, 0x00000040U }, 90 { DBSC_DBSCHQOS121, 0x00000030U }, 91 { DBSC_DBSCHQOS122, 0x00000020U }, 92 { DBSC_DBSCHQOS123, 0x00000010U }, 93 { DBSC_DBSCHQOS130, 0x00000100U }, 94 { DBSC_DBSCHQOS131, 0x000000F0U }, 95 { DBSC_DBSCHQOS132, 0x000000A0U }, 96 { DBSC_DBSCHQOS133, 0x00000040U }, 97 { DBSC_DBSCHQOS140, 0x000000C0U }, 98 { DBSC_DBSCHQOS141, 0x000000B0U }, 99 { DBSC_DBSCHQOS142, 0x00000080U }, 100 { DBSC_DBSCHQOS143, 0x00000040U }, 101 { DBSC_DBSCHQOS150, 0x00000040U }, 102 { DBSC_DBSCHQOS151, 0x00000030U }, 103 { DBSC_DBSCHQOS152, 0x00000020U }, 104 { DBSC_DBSCHQOS153, 0x00000010U }, 105 }; 106 107 void qos_init_h3_v20(void) 108 { 109 rcar_qos_dbsc_setting(h3_v20_qos, ARRAY_SIZE(h3_v20_qos), true); 110 111 /* DRAM Split Address mapping */ 112 #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \ 113 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) 114 NOTICE("BL2: DRAM Split is 4ch\n"); 115 io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT 116 | ADSPLCR0_SPLITSEL(0xFFU) 117 | ADSPLCR0_AREA(0x1BU) 118 | ADSPLCR0_SWP); 119 io_write_32(AXI_ADSPLCR1, 0x00000000U); 120 io_write_32(AXI_ADSPLCR2, 0x00001054U); 121 io_write_32(AXI_ADSPLCR3, 0x00000000U); 122 #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH 123 NOTICE("BL2: DRAM Split is 2ch\n"); 124 io_write_32(AXI_ADSPLCR0, 0x00000000U); 125 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT 126 | ADSPLCR0_SPLITSEL(0xFFU) 127 | ADSPLCR0_AREA(0x1BU) 128 | ADSPLCR0_SWP); 129 io_write_32(AXI_ADSPLCR2, 0x00001004U); 130 io_write_32(AXI_ADSPLCR3, 0x00000000U); 131 #else 132 NOTICE("BL2: DRAM Split is OFF\n"); 133 #endif 134 135 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) 136 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT 137 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); 138 #endif 139 140 #if RCAR_REF_INT == RCAR_REF_DEFAULT 141 NOTICE("BL2: DRAM refresh interval 1.95 usec\n"); 142 #else 143 NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); 144 #endif 145 146 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 147 NOTICE("BL2: Periodic Write DQ Training\n"); 148 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 149 150 io_write_32(QOSCTRL_RAS, 0x00000044U); 151 io_write_64(QOSCTRL_DANN, 0x0404010002020201UL); 152 io_write_32(QOSCTRL_DANT, 0x0020100AU); 153 io_write_32(QOSCTRL_INSFC, 0x06330001U); 154 io_write_32(QOSCTRL_RACNT0, 0x00010003U); 155 156 /* GPU Boost Mode */ 157 io_write_32(QOSCTRL_STATGEN0, 0x00000001U); 158 159 io_write_32(QOSCTRL_SL_INIT, 160 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | 161 SL_INIT_SSLOTCLK_H3_20); 162 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 163 io_write_32(QOSCTRL_REF_ARS, 164 ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 << 16))); 165 #else 166 io_write_32(QOSCTRL_REF_ARS, 0x00330000U); 167 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 168 169 uint32_t i; 170 171 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { 172 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); 173 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); 174 } 175 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { 176 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); 177 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); 178 } 179 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 180 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { 181 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, 182 qoswt_fix[i]); 183 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, 184 qoswt_fix[i]); 185 } 186 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { 187 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]); 188 io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]); 189 } 190 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 191 192 /* 3DG bus Leaf setting */ 193 io_write_32(GPU_ACT0, 0x00000000U); 194 io_write_32(GPU_ACT1, 0x00000000U); 195 io_write_32(GPU_ACT2, 0x00000000U); 196 io_write_32(GPU_ACT3, 0x00000000U); 197 io_write_32(GPU_ACT4, 0x00000000U); 198 io_write_32(GPU_ACT5, 0x00000000U); 199 io_write_32(GPU_ACT6, 0x00000000U); 200 io_write_32(GPU_ACT7, 0x00000000U); 201 202 /* RT bus Leaf setting */ 203 io_write_32(RT_ACT0, 0x00000000U); 204 io_write_32(RT_ACT1, 0x00000000U); 205 206 /* CCI bus Leaf setting */ 207 io_write_32(CPU_ACT0, 0x00000003U); 208 io_write_32(CPU_ACT1, 0x00000003U); 209 io_write_32(CPU_ACT2, 0x00000003U); 210 io_write_32(CPU_ACT3, 0x00000003U); 211 212 io_write_32(QOSCTRL_RAEN, 0x00000001U); 213 214 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE 215 /* re-write training setting */ 216 io_write_32(QOSWT_WTREF, 217 ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN)); 218 io_write_32(QOSWT_WTSET0, 219 ((QOSWT_WTSET0_PERIOD0_H3_20 << 16) | 220 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0)); 221 io_write_32(QOSWT_WTSET1, 222 ((QOSWT_WTSET1_PERIOD1_H3_20 << 16) | 223 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1)); 224 225 io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE); 226 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ 227 228 io_write_32(QOSCTRL_STATQC, 0x00000001U); 229 #else 230 NOTICE("BL2: QoS is None\n"); 231 232 io_write_32(QOSCTRL_RAEN, 0x00000001U); 233 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ 234 } 235