1 /* 2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> /* for uint32_t */ 8 9 #include <lib/mmio.h> 10 11 #include "pfc_init_m3n.h" 12 #include "rcar_def.h" 13 #include "../pfc_regs.h" 14 15 #define GPSR0_D15 BIT(15) 16 #define GPSR0_D14 BIT(14) 17 #define GPSR0_D13 BIT(13) 18 #define GPSR0_D12 BIT(12) 19 #define GPSR0_D11 BIT(11) 20 #define GPSR0_D10 BIT(10) 21 #define GPSR0_D9 BIT(9) 22 #define GPSR0_D8 BIT(8) 23 #define GPSR0_D7 BIT(7) 24 #define GPSR0_D6 BIT(6) 25 #define GPSR0_D5 BIT(5) 26 #define GPSR0_D4 BIT(4) 27 #define GPSR0_D3 BIT(3) 28 #define GPSR0_D2 BIT(2) 29 #define GPSR0_D1 BIT(1) 30 #define GPSR0_D0 BIT(0) 31 #define GPSR1_CLKOUT BIT(28) 32 #define GPSR1_EX_WAIT0_A BIT(27) 33 #define GPSR1_WE1 BIT(26) 34 #define GPSR1_WE0 BIT(25) 35 #define GPSR1_RD_WR BIT(24) 36 #define GPSR1_RD BIT(23) 37 #define GPSR1_BS BIT(22) 38 #define GPSR1_CS1_A26 BIT(21) 39 #define GPSR1_CS0 BIT(20) 40 #define GPSR1_A19 BIT(19) 41 #define GPSR1_A18 BIT(18) 42 #define GPSR1_A17 BIT(17) 43 #define GPSR1_A16 BIT(16) 44 #define GPSR1_A15 BIT(15) 45 #define GPSR1_A14 BIT(14) 46 #define GPSR1_A13 BIT(13) 47 #define GPSR1_A12 BIT(12) 48 #define GPSR1_A11 BIT(11) 49 #define GPSR1_A10 BIT(10) 50 #define GPSR1_A9 BIT(9) 51 #define GPSR1_A8 BIT(8) 52 #define GPSR1_A7 BIT(7) 53 #define GPSR1_A6 BIT(6) 54 #define GPSR1_A5 BIT(5) 55 #define GPSR1_A4 BIT(4) 56 #define GPSR1_A3 BIT(3) 57 #define GPSR1_A2 BIT(2) 58 #define GPSR1_A1 BIT(1) 59 #define GPSR1_A0 BIT(0) 60 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14) 61 #define GPSR2_AVB_AVTP_MATCH_A BIT(13) 62 #define GPSR2_AVB_LINK BIT(12) 63 #define GPSR2_AVB_PHY_INT BIT(11) 64 #define GPSR2_AVB_MAGIC BIT(10) 65 #define GPSR2_AVB_MDC BIT(9) 66 #define GPSR2_PWM2_A BIT(8) 67 #define GPSR2_PWM1_A BIT(7) 68 #define GPSR2_PWM0 BIT(6) 69 #define GPSR2_IRQ5 BIT(5) 70 #define GPSR2_IRQ4 BIT(4) 71 #define GPSR2_IRQ3 BIT(3) 72 #define GPSR2_IRQ2 BIT(2) 73 #define GPSR2_IRQ1 BIT(1) 74 #define GPSR2_IRQ0 BIT(0) 75 #define GPSR3_SD1_WP BIT(15) 76 #define GPSR3_SD1_CD BIT(14) 77 #define GPSR3_SD0_WP BIT(13) 78 #define GPSR3_SD0_CD BIT(12) 79 #define GPSR3_SD1_DAT3 BIT(11) 80 #define GPSR3_SD1_DAT2 BIT(10) 81 #define GPSR3_SD1_DAT1 BIT(9) 82 #define GPSR3_SD1_DAT0 BIT(8) 83 #define GPSR3_SD1_CMD BIT(7) 84 #define GPSR3_SD1_CLK BIT(6) 85 #define GPSR3_SD0_DAT3 BIT(5) 86 #define GPSR3_SD0_DAT2 BIT(4) 87 #define GPSR3_SD0_DAT1 BIT(3) 88 #define GPSR3_SD0_DAT0 BIT(2) 89 #define GPSR3_SD0_CMD BIT(1) 90 #define GPSR3_SD0_CLK BIT(0) 91 #define GPSR4_SD3_DS BIT(17) 92 #define GPSR4_SD3_DAT7 BIT(16) 93 #define GPSR4_SD3_DAT6 BIT(15) 94 #define GPSR4_SD3_DAT5 BIT(14) 95 #define GPSR4_SD3_DAT4 BIT(13) 96 #define GPSR4_SD3_DAT3 BIT(12) 97 #define GPSR4_SD3_DAT2 BIT(11) 98 #define GPSR4_SD3_DAT1 BIT(10) 99 #define GPSR4_SD3_DAT0 BIT(9) 100 #define GPSR4_SD3_CMD BIT(8) 101 #define GPSR4_SD3_CLK BIT(7) 102 #define GPSR4_SD2_DS BIT(6) 103 #define GPSR4_SD2_DAT3 BIT(5) 104 #define GPSR4_SD2_DAT2 BIT(4) 105 #define GPSR4_SD2_DAT1 BIT(3) 106 #define GPSR4_SD2_DAT0 BIT(2) 107 #define GPSR4_SD2_CMD BIT(1) 108 #define GPSR4_SD2_CLK BIT(0) 109 #define GPSR5_MLB_DAT BIT(25) 110 #define GPSR5_MLB_SIG BIT(24) 111 #define GPSR5_MLB_CLK BIT(23) 112 #define GPSR5_MSIOF0_RXD BIT(22) 113 #define GPSR5_MSIOF0_SS2 BIT(21) 114 #define GPSR5_MSIOF0_TXD BIT(20) 115 #define GPSR5_MSIOF0_SS1 BIT(19) 116 #define GPSR5_MSIOF0_SYNC BIT(18) 117 #define GPSR5_MSIOF0_SCK BIT(17) 118 #define GPSR5_HRTS0 BIT(16) 119 #define GPSR5_HCTS0 BIT(15) 120 #define GPSR5_HTX0 BIT(14) 121 #define GPSR5_HRX0 BIT(13) 122 #define GPSR5_HSCK0 BIT(12) 123 #define GPSR5_RX2_A BIT(11) 124 #define GPSR5_TX2_A BIT(10) 125 #define GPSR5_SCK2 BIT(9) 126 #define GPSR5_RTS1_TANS BIT(8) 127 #define GPSR5_CTS1 BIT(7) 128 #define GPSR5_TX1_A BIT(6) 129 #define GPSR5_RX1_A BIT(5) 130 #define GPSR5_RTS0_TANS BIT(4) 131 #define GPSR5_CTS0 BIT(3) 132 #define GPSR5_TX0 BIT(2) 133 #define GPSR5_RX0 BIT(1) 134 #define GPSR5_SCK0 BIT(0) 135 #define GPSR6_USB31_OVC BIT(31) 136 #define GPSR6_USB31_PWEN BIT(30) 137 #define GPSR6_USB30_OVC BIT(29) 138 #define GPSR6_USB30_PWEN BIT(28) 139 #define GPSR6_USB1_OVC BIT(27) 140 #define GPSR6_USB1_PWEN BIT(26) 141 #define GPSR6_USB0_OVC BIT(25) 142 #define GPSR6_USB0_PWEN BIT(24) 143 #define GPSR6_AUDIO_CLKB_B BIT(23) 144 #define GPSR6_AUDIO_CLKA_A BIT(22) 145 #define GPSR6_SSI_SDATA9_A BIT(21) 146 #define GPSR6_SSI_SDATA8 BIT(20) 147 #define GPSR6_SSI_SDATA7 BIT(19) 148 #define GPSR6_SSI_WS78 BIT(18) 149 #define GPSR6_SSI_SCK78 BIT(17) 150 #define GPSR6_SSI_SDATA6 BIT(16) 151 #define GPSR6_SSI_WS6 BIT(15) 152 #define GPSR6_SSI_SCK6 BIT(14) 153 #define GPSR6_SSI_SDATA5 BIT(13) 154 #define GPSR6_SSI_WS5 BIT(12) 155 #define GPSR6_SSI_SCK5 BIT(11) 156 #define GPSR6_SSI_SDATA4 BIT(10) 157 #define GPSR6_SSI_WS4 BIT(9) 158 #define GPSR6_SSI_SCK4 BIT(8) 159 #define GPSR6_SSI_SDATA3 BIT(7) 160 #define GPSR6_SSI_WS34 BIT(6) 161 #define GPSR6_SSI_SCK34 BIT(5) 162 #define GPSR6_SSI_SDATA2_A BIT(4) 163 #define GPSR6_SSI_SDATA1_A BIT(3) 164 #define GPSR6_SSI_SDATA0 BIT(2) 165 #define GPSR6_SSI_WS0129 BIT(1) 166 #define GPSR6_SSI_SCK0129 BIT(0) 167 #define GPSR7_HDMI1_CEC BIT(3) 168 #define GPSR7_HDMI0_CEC BIT(2) 169 #define GPSR7_AVS2 BIT(1) 170 #define GPSR7_AVS1 BIT(0) 171 172 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) 173 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) 174 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) 175 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) 176 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) 177 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) 178 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) 179 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) 180 181 #define POC_SD3_DS_33V BIT(29) 182 #define POC_SD3_DAT7_33V BIT(28) 183 #define POC_SD3_DAT6_33V BIT(27) 184 #define POC_SD3_DAT5_33V BIT(26) 185 #define POC_SD3_DAT4_33V BIT(25) 186 #define POC_SD3_DAT3_33V BIT(24) 187 #define POC_SD3_DAT2_33V BIT(23) 188 #define POC_SD3_DAT1_33V BIT(22) 189 #define POC_SD3_DAT0_33V BIT(21) 190 #define POC_SD3_CMD_33V BIT(20) 191 #define POC_SD3_CLK_33V BIT(19) 192 #define POC_SD2_DS_33V BIT(18) 193 #define POC_SD2_DAT3_33V BIT(17) 194 #define POC_SD2_DAT2_33V BIT(16) 195 #define POC_SD2_DAT1_33V BIT(15) 196 #define POC_SD2_DAT0_33V BIT(14) 197 #define POC_SD2_CMD_33V BIT(13) 198 #define POC_SD2_CLK_33V BIT(12) 199 #define POC_SD1_DAT3_33V BIT(11) 200 #define POC_SD1_DAT2_33V BIT(10) 201 #define POC_SD1_DAT1_33V BIT(9) 202 #define POC_SD1_DAT0_33V BIT(8) 203 #define POC_SD1_CMD_33V BIT(7) 204 #define POC_SD1_CLK_33V BIT(6) 205 #define POC_SD0_DAT3_33V BIT(5) 206 #define POC_SD0_DAT2_33V BIT(4) 207 #define POC_SD0_DAT1_33V BIT(3) 208 #define POC_SD0_DAT0_33V BIT(2) 209 #define POC_SD0_CMD_33V BIT(1) 210 #define POC_SD0_CLK_33V BIT(0) 211 212 #define DRVCTRL0_MASK (0xCCCCCCCCU) 213 #define DRVCTRL1_MASK (0xCCCCCCC8U) 214 #define DRVCTRL2_MASK (0x88888888U) 215 #define DRVCTRL3_MASK (0x88888888U) 216 #define DRVCTRL4_MASK (0x88888888U) 217 #define DRVCTRL5_MASK (0x88888888U) 218 #define DRVCTRL6_MASK (0x88888888U) 219 #define DRVCTRL7_MASK (0x88888888U) 220 #define DRVCTRL8_MASK (0x88888888U) 221 #define DRVCTRL9_MASK (0x88888888U) 222 #define DRVCTRL10_MASK (0x88888888U) 223 #define DRVCTRL11_MASK (0x888888CCU) 224 #define DRVCTRL12_MASK (0xCCCFFFCFU) 225 #define DRVCTRL13_MASK (0xCC888888U) 226 #define DRVCTRL14_MASK (0x88888888U) 227 #define DRVCTRL15_MASK (0x88888888U) 228 #define DRVCTRL16_MASK (0x88888888U) 229 #define DRVCTRL17_MASK (0x88888888U) 230 #define DRVCTRL18_MASK (0x88888888U) 231 #define DRVCTRL19_MASK (0x88888888U) 232 #define DRVCTRL20_MASK (0x88888888U) 233 #define DRVCTRL21_MASK (0x88888888U) 234 #define DRVCTRL22_MASK (0x88888888U) 235 #define DRVCTRL23_MASK (0x88888888U) 236 #define DRVCTRL24_MASK (0x8888888FU) 237 238 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) 239 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) 240 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) 241 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) 242 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) 243 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) 244 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) 245 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) 246 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) 247 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) 248 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) 249 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) 250 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) 251 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) 252 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) 253 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) 254 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) 255 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) 256 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) 257 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) 258 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) 259 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) 260 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) 261 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) 262 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) 263 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) 264 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) 265 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) 266 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) 267 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) 268 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) 269 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) 270 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) 271 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) 272 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) 273 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) 274 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) 275 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) 276 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) 277 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) 278 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) 279 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) 280 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) 281 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) 282 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) 283 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) 284 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) 285 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) 286 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) 287 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) 288 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) 289 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) 290 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) 291 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) 292 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) 293 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) 294 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) 295 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) 296 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) 297 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) 298 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) 299 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) 300 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) 301 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) 302 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) 303 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) 304 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) 305 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) 306 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) 307 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) 308 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) 309 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) 310 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) 311 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) 312 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) 313 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) 314 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) 315 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) 316 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) 317 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) 318 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) 319 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) 320 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) 321 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) 322 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) 323 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) 324 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) 325 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) 326 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) 327 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) 328 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) 329 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) 330 #define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U) 331 #define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U) 332 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) 333 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) 334 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) 335 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) 336 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) 337 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) 338 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) 339 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) 340 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) 341 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) 342 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) 343 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) 344 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) 345 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) 346 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) 347 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) 348 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) 349 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) 350 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) 351 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) 352 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) 353 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) 354 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) 355 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) 356 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) 357 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) 358 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) 359 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) 360 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) 361 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) 362 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) 363 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) 364 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) 365 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) 366 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) 367 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) 368 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) 369 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) 370 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) 371 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) 372 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) 373 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) 374 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) 375 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) 376 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) 377 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) 378 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) 379 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) 380 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) 381 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) 382 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) 383 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) 384 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) 385 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) 386 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) 387 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) 388 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) 389 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) 390 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) 391 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) 392 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) 393 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) 394 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) 395 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) 396 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) 397 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) 398 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) 399 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) 400 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) 401 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) 402 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) 403 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) 404 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) 405 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) 406 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) 407 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) 408 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) 409 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) 410 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) 411 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) 412 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) 413 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) 414 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) 415 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) 416 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) 417 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) 418 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) 419 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) 420 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) 421 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) 422 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) 423 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) 424 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) 425 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) 426 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) 427 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) 428 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) 429 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) 430 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) 431 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) 432 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) 433 434 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) 435 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) 436 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) 437 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) 438 #define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U) 439 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) 440 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) 441 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) 442 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) 443 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) 444 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) 445 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) 446 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) 447 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) 448 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) 449 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) 450 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) 451 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) 452 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) 453 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) 454 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U) 455 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U) 456 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) 457 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) 458 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U) 459 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U) 460 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U) 461 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U) 462 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U) 463 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U) 464 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U) 465 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U) 466 #define MOD_SEL0_FSO_A ((uint32_t)0U << 15U) 467 #define MOD_SEL0_FSO_B ((uint32_t)1U << 15U) 468 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U) 469 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U) 470 #define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U) 471 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U) 472 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U) 473 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U) 474 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U) 475 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U) 476 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U) 477 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U) 478 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U) 479 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U) 480 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U) 481 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U) 482 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U) 483 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U) 484 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U) 485 #define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U) 486 #define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U) 487 #define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U) 488 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) 489 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) 490 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) 491 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) 492 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) 493 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) 494 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) 495 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) 496 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) 497 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) 498 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) 499 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) 500 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) 501 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) 502 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) 503 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) 504 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) 505 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) 506 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) 507 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) 508 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) 509 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) 510 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) 511 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) 512 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) 513 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) 514 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) 515 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) 516 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) 517 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) 518 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) 519 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) 520 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) 521 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) 522 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) 523 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) 524 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) 525 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) 526 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) 527 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) 528 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) 529 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) 530 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) 531 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) 532 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) 533 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) 534 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) 535 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) 536 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) 537 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) 538 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) 539 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) 540 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) 541 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) 542 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) 543 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) 544 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) 545 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) 546 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) 547 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) 548 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) 549 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) 550 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) 551 #define MOD_SEL2_FM_A ((uint32_t)0U << 27U) 552 #define MOD_SEL2_FM_B ((uint32_t)1U << 27U) 553 #define MOD_SEL2_FM_C ((uint32_t)2U << 27U) 554 #define MOD_SEL2_FM_D ((uint32_t)3U << 27U) 555 #define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U) 556 #define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U) 557 #define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U) 558 #define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U) 559 #define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U) 560 #define MOD_SEL2_NDF_A ((uint32_t)0U << 22U) 561 #define MOD_SEL2_NDF_B ((uint32_t)1U << 22U) 562 #define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U) 563 #define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U) 564 #define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U) 565 #define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U) 566 #define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U) 567 #define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U) 568 #define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U) 569 #define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U) 570 #define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U) 571 #define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U) 572 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) 573 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) 574 575 static void pfc_reg_write(uint32_t addr, uint32_t data) 576 { 577 mmio_write_32(PFC_PMMR, ~data); 578 mmio_write_32((uintptr_t)addr, data); 579 } 580 581 void pfc_init_m3n(void) 582 { 583 uint32_t reg; 584 585 /* initialize module select */ 586 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A 587 | MOD_SEL0_MSIOF2_A 588 | MOD_SEL0_MSIOF1_A 589 | MOD_SEL0_LBSC_A 590 | MOD_SEL0_IEBUS_A 591 | MOD_SEL0_I2C2_A 592 | MOD_SEL0_I2C1_A 593 | MOD_SEL0_HSCIF4_A 594 | MOD_SEL0_HSCIF3_A 595 | MOD_SEL0_HSCIF1_A 596 | MOD_SEL0_FSO_A 597 | MOD_SEL0_HSCIF2_A 598 | MOD_SEL0_ETHERAVB_A 599 | MOD_SEL0_DRIF3_A 600 | MOD_SEL0_DRIF2_A 601 | MOD_SEL0_DRIF1_A 602 | MOD_SEL0_DRIF0_A 603 | MOD_SEL0_CANFD0_A 604 | MOD_SEL0_ADG_A_A); 605 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A 606 | MOD_SEL1_TSIF0_A 607 | MOD_SEL1_TIMER_TMU_A 608 | MOD_SEL1_SSP1_1_A 609 | MOD_SEL1_SSP1_0_A 610 | MOD_SEL1_SSI_A 611 | MOD_SEL1_SPEED_PULSE_IF_A 612 | MOD_SEL1_SIMCARD_A 613 | MOD_SEL1_SDHI2_A 614 | MOD_SEL1_SCIF4_A 615 | MOD_SEL1_SCIF3_A 616 | MOD_SEL1_SCIF2_A 617 | MOD_SEL1_SCIF1_A 618 | MOD_SEL1_SCIF_A 619 | MOD_SEL1_REMOCON_A 620 | MOD_SEL1_RCAN0_A 621 | MOD_SEL1_PWM6_A 622 | MOD_SEL1_PWM5_A 623 | MOD_SEL1_PWM4_A 624 | MOD_SEL1_PWM3_A 625 | MOD_SEL1_PWM2_A 626 | MOD_SEL1_PWM1_A); 627 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A 628 | MOD_SEL2_I2C_3_A 629 | MOD_SEL2_I2C_0_A 630 | MOD_SEL2_FM_A 631 | MOD_SEL2_SCIF5_A 632 | MOD_SEL2_I2C6_A 633 | MOD_SEL2_NDF_A 634 | MOD_SEL2_SSI2_A 635 | MOD_SEL2_SSI9_A 636 | MOD_SEL2_TIMER_TMU2_A 637 | MOD_SEL2_ADG_B_A 638 | MOD_SEL2_ADG_C_A 639 | MOD_SEL2_VIN4_A); 640 641 /* initialize peripheral function select */ 642 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) 643 | IPSR_24_FUNC(0) 644 | IPSR_20_FUNC(0) 645 | IPSR_16_FUNC(0) 646 | IPSR_12_FUNC(0) 647 | IPSR_8_FUNC(0) 648 | IPSR_4_FUNC(0) 649 | IPSR_0_FUNC(0)); 650 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6) 651 | IPSR_24_FUNC(0) 652 | IPSR_20_FUNC(0) 653 | IPSR_16_FUNC(0) 654 | IPSR_12_FUNC(3) 655 | IPSR_8_FUNC(3) 656 | IPSR_4_FUNC(3) 657 | IPSR_0_FUNC(3)); 658 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) 659 | IPSR_24_FUNC(6) 660 | IPSR_20_FUNC(6) 661 | IPSR_16_FUNC(6) 662 | IPSR_12_FUNC(6) 663 | IPSR_8_FUNC(6) 664 | IPSR_4_FUNC(6) 665 | IPSR_0_FUNC(6)); 666 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6) 667 | IPSR_24_FUNC(6) 668 | IPSR_20_FUNC(6) 669 | IPSR_16_FUNC(6) 670 | IPSR_12_FUNC(6) 671 | IPSR_8_FUNC(0) 672 | IPSR_4_FUNC(0) 673 | IPSR_0_FUNC(0)); 674 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) 675 | IPSR_24_FUNC(0) 676 | IPSR_20_FUNC(0) 677 | IPSR_16_FUNC(0) 678 | IPSR_12_FUNC(0) 679 | IPSR_8_FUNC(6) 680 | IPSR_4_FUNC(6) 681 | IPSR_0_FUNC(6)); 682 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) 683 | IPSR_24_FUNC(0) 684 | IPSR_20_FUNC(0) 685 | IPSR_16_FUNC(0) 686 | IPSR_12_FUNC(0) 687 | IPSR_8_FUNC(6) 688 | IPSR_4_FUNC(0) 689 | IPSR_0_FUNC(0)); 690 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6) 691 | IPSR_24_FUNC(6) 692 | IPSR_20_FUNC(6) 693 | IPSR_16_FUNC(6) 694 | IPSR_12_FUNC(6) 695 | IPSR_8_FUNC(0) 696 | IPSR_4_FUNC(0) 697 | IPSR_0_FUNC(0)); 698 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) 699 | IPSR_24_FUNC(0) 700 | IPSR_20_FUNC(0) 701 | IPSR_16_FUNC(0) 702 | IPSR_12_FUNC(0) 703 | IPSR_8_FUNC(6) 704 | IPSR_4_FUNC(6) 705 | IPSR_0_FUNC(6)); 706 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1) 707 | IPSR_24_FUNC(1) 708 | IPSR_20_FUNC(1) 709 | IPSR_16_FUNC(1) 710 | IPSR_12_FUNC(0) 711 | IPSR_8_FUNC(0) 712 | IPSR_4_FUNC(0) 713 | IPSR_0_FUNC(0)); 714 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) 715 | IPSR_24_FUNC(0) 716 | IPSR_20_FUNC(0) 717 | IPSR_16_FUNC(0) 718 | IPSR_12_FUNC(0) 719 | IPSR_8_FUNC(0) 720 | IPSR_4_FUNC(0) 721 | IPSR_0_FUNC(0)); 722 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1) 723 | IPSR_24_FUNC(0) 724 | IPSR_20_FUNC(0) 725 | IPSR_16_FUNC(0) 726 | IPSR_12_FUNC(0) 727 | IPSR_8_FUNC(0) 728 | IPSR_4_FUNC(0) 729 | IPSR_0_FUNC(0)); 730 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0) 731 | IPSR_24_FUNC(4) 732 | IPSR_20_FUNC(0) 733 | IPSR_16_FUNC(0) 734 | IPSR_12_FUNC(0) 735 | IPSR_8_FUNC(0) 736 | IPSR_4_FUNC(0) 737 | IPSR_0_FUNC(1)); 738 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0) 739 | IPSR_24_FUNC(0) 740 | IPSR_20_FUNC(0) 741 | IPSR_16_FUNC(0) 742 | IPSR_12_FUNC(0) 743 | IPSR_8_FUNC(4) 744 | IPSR_4_FUNC(0) 745 | IPSR_0_FUNC(0)); 746 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8) 747 | IPSR_24_FUNC(0) 748 | IPSR_20_FUNC(0) 749 | IPSR_16_FUNC(0) 750 | IPSR_12_FUNC(0) 751 | IPSR_8_FUNC(3) 752 | IPSR_4_FUNC(0) 753 | IPSR_0_FUNC(0)); 754 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0) 755 | IPSR_24_FUNC(0) 756 | IPSR_20_FUNC(0) 757 | IPSR_16_FUNC(0) 758 | IPSR_12_FUNC(0) 759 | IPSR_8_FUNC(0) 760 | IPSR_4_FUNC(3) 761 | IPSR_0_FUNC(8)); 762 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) 763 | IPSR_24_FUNC(0) 764 | IPSR_20_FUNC(0) 765 | IPSR_16_FUNC(0) 766 | IPSR_12_FUNC(0) 767 | IPSR_8_FUNC(0) 768 | IPSR_4_FUNC(0) 769 | IPSR_0_FUNC(0)); 770 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0) 771 | IPSR_24_FUNC(0) 772 | IPSR_20_FUNC(0) 773 | IPSR_16_FUNC(0) 774 | IPSR_12_FUNC(0) 775 | IPSR_8_FUNC(0) 776 | IPSR_4_FUNC(0) 777 | IPSR_0_FUNC(0)); 778 pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0) 779 | IPSR_24_FUNC(0) 780 | IPSR_20_FUNC(0) 781 | IPSR_16_FUNC(0) 782 | IPSR_12_FUNC(0) 783 | IPSR_8_FUNC(0) 784 | IPSR_4_FUNC(1) 785 | IPSR_0_FUNC(0)); 786 pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0) 787 | IPSR_0_FUNC(0)); 788 789 /* initialize GPIO/perihperal function select */ 790 pfc_reg_write(PFC_GPSR0, GPSR0_D15 791 | GPSR0_D14 792 | GPSR0_D13 793 | GPSR0_D12 794 | GPSR0_D11 795 | GPSR0_D10 796 | GPSR0_D9 797 | GPSR0_D8); 798 pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT 799 | GPSR1_EX_WAIT0_A 800 | GPSR1_A19 801 | GPSR1_A18 802 | GPSR1_A17 803 | GPSR1_A16 804 | GPSR1_A15 805 | GPSR1_A14 806 | GPSR1_A13 807 | GPSR1_A12 808 | GPSR1_A7 809 | GPSR1_A6 810 | GPSR1_A5 811 | GPSR1_A4 812 | GPSR1_A3 813 | GPSR1_A2 814 | GPSR1_A1 815 | GPSR1_A0); 816 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A 817 | GPSR2_AVB_AVTP_MATCH_A 818 | GPSR2_AVB_LINK 819 | GPSR2_AVB_PHY_INT 820 | GPSR2_AVB_MDC 821 | GPSR2_PWM2_A 822 | GPSR2_PWM1_A 823 | GPSR2_IRQ5 824 | GPSR2_IRQ4 825 | GPSR2_IRQ3 826 | GPSR2_IRQ2 827 | GPSR2_IRQ1 828 | GPSR2_IRQ0); 829 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP 830 | GPSR3_SD0_CD 831 | GPSR3_SD1_DAT3 832 | GPSR3_SD1_DAT2 833 | GPSR3_SD1_DAT1 834 | GPSR3_SD1_DAT0 835 | GPSR3_SD0_DAT3 836 | GPSR3_SD0_DAT2 837 | GPSR3_SD0_DAT1 838 | GPSR3_SD0_DAT0 839 | GPSR3_SD0_CMD 840 | GPSR3_SD0_CLK); 841 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7 842 | GPSR4_SD3_DAT6 843 | GPSR4_SD3_DAT3 844 | GPSR4_SD3_DAT2 845 | GPSR4_SD3_DAT1 846 | GPSR4_SD3_DAT0 847 | GPSR4_SD3_CMD 848 | GPSR4_SD3_CLK 849 | GPSR4_SD2_DS 850 | GPSR4_SD2_DAT3 851 | GPSR4_SD2_DAT2 852 | GPSR4_SD2_DAT1 853 | GPSR4_SD2_DAT0 854 | GPSR4_SD2_CMD 855 | GPSR4_SD2_CLK); 856 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2 857 | GPSR5_MSIOF0_SS1 858 | GPSR5_MSIOF0_SYNC 859 | GPSR5_HRTS0 860 | GPSR5_HCTS0 861 | GPSR5_HTX0 862 | GPSR5_HRX0 863 | GPSR5_HSCK0 864 | GPSR5_RX2_A 865 | GPSR5_TX2_A 866 | GPSR5_SCK2 867 | GPSR5_RTS1_TANS 868 | GPSR5_CTS1 869 | GPSR5_TX1_A 870 | GPSR5_RX1_A 871 | GPSR5_RTS0_TANS 872 | GPSR5_SCK0); 873 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC 874 | GPSR6_USB30_PWEN 875 | GPSR6_USB1_OVC 876 | GPSR6_USB1_PWEN 877 | GPSR6_USB0_OVC 878 | GPSR6_USB0_PWEN 879 | GPSR6_AUDIO_CLKB_B 880 | GPSR6_AUDIO_CLKA_A 881 | GPSR6_SSI_SDATA8 882 | GPSR6_SSI_SDATA7 883 | GPSR6_SSI_WS78 884 | GPSR6_SSI_SCK78 885 | GPSR6_SSI_WS6 886 | GPSR6_SSI_SCK6 887 | GPSR6_SSI_SDATA4 888 | GPSR6_SSI_WS4 889 | GPSR6_SSI_SCK4 890 | GPSR6_SSI_SDATA1_A 891 | GPSR6_SSI_SDATA0 892 | GPSR6_SSI_WS0129 893 | GPSR6_SSI_SCK0129); 894 pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC 895 | GPSR7_HDMI0_CEC 896 | GPSR7_AVS2 897 | GPSR7_AVS1); 898 899 /* initialize POC control register */ 900 pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V 901 | POC_SD3_DAT7_33V 902 | POC_SD3_DAT6_33V 903 | POC_SD3_DAT5_33V 904 | POC_SD3_DAT4_33V 905 | POC_SD3_DAT3_33V 906 | POC_SD3_DAT2_33V 907 | POC_SD3_DAT1_33V 908 | POC_SD3_DAT0_33V 909 | POC_SD3_CMD_33V 910 | POC_SD3_CLK_33V 911 | POC_SD0_DAT3_33V 912 | POC_SD0_DAT2_33V 913 | POC_SD0_DAT1_33V 914 | POC_SD0_DAT0_33V 915 | POC_SD0_CMD_33V 916 | POC_SD0_CLK_33V); 917 918 /* initialize DRV control register */ 919 reg = mmio_read_32(PFC_DRVCTRL0); 920 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) 921 | DRVCTRL0_QSPI0_MOSI_IO0(3) 922 | DRVCTRL0_QSPI0_MISO_IO1(3) 923 | DRVCTRL0_QSPI0_IO2(3) 924 | DRVCTRL0_QSPI0_IO3(3) 925 | DRVCTRL0_QSPI0_SSL(3) 926 | DRVCTRL0_QSPI1_SPCLK(3) 927 | DRVCTRL0_QSPI1_MOSI_IO0(3)); 928 pfc_reg_write(PFC_DRVCTRL0, reg); 929 reg = mmio_read_32(PFC_DRVCTRL1); 930 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) 931 | DRVCTRL1_QSPI1_IO2(3) 932 | DRVCTRL1_QSPI1_IO3(3) 933 | DRVCTRL1_QSPI1_SS(3) 934 | DRVCTRL1_RPC_INT(3) 935 | DRVCTRL1_RPC_WP(3) 936 | DRVCTRL1_RPC_RESET(3) 937 | DRVCTRL1_AVB_RX_CTL(7)); 938 pfc_reg_write(PFC_DRVCTRL1, reg); 939 reg = mmio_read_32(PFC_DRVCTRL2); 940 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) 941 | DRVCTRL2_AVB_RD0(7) 942 | DRVCTRL2_AVB_RD1(7) 943 | DRVCTRL2_AVB_RD2(7) 944 | DRVCTRL2_AVB_RD3(7) 945 | DRVCTRL2_AVB_TX_CTL(3) 946 | DRVCTRL2_AVB_TXC(3) 947 | DRVCTRL2_AVB_TD0(3)); 948 pfc_reg_write(PFC_DRVCTRL2, reg); 949 reg = mmio_read_32(PFC_DRVCTRL3); 950 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3) 951 | DRVCTRL3_AVB_TD2(3) 952 | DRVCTRL3_AVB_TD3(3) 953 | DRVCTRL3_AVB_TXCREFCLK(7) 954 | DRVCTRL3_AVB_MDIO(7) 955 | DRVCTRL3_AVB_MDC(7) 956 | DRVCTRL3_AVB_MAGIC(7) 957 | DRVCTRL3_AVB_PHY_INT(7)); 958 pfc_reg_write(PFC_DRVCTRL3, reg); 959 reg = mmio_read_32(PFC_DRVCTRL4); 960 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) 961 | DRVCTRL4_AVB_AVTP_MATCH(7) 962 | DRVCTRL4_AVB_AVTP_CAPTURE(7) 963 | DRVCTRL4_IRQ0(7) 964 | DRVCTRL4_IRQ1(7) 965 | DRVCTRL4_IRQ2(7) 966 | DRVCTRL4_IRQ3(7) 967 | DRVCTRL4_IRQ4(7)); 968 pfc_reg_write(PFC_DRVCTRL4, reg); 969 reg = mmio_read_32(PFC_DRVCTRL5); 970 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) 971 | DRVCTRL5_PWM0(7) 972 | DRVCTRL5_PWM1(7) 973 | DRVCTRL5_PWM2(7) 974 | DRVCTRL5_A0(3) 975 | DRVCTRL5_A1(3) 976 | DRVCTRL5_A2(3) 977 | DRVCTRL5_A3(3)); 978 pfc_reg_write(PFC_DRVCTRL5, reg); 979 reg = mmio_read_32(PFC_DRVCTRL6); 980 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3) 981 | DRVCTRL6_A5(3) 982 | DRVCTRL6_A6(3) 983 | DRVCTRL6_A7(3) 984 | DRVCTRL6_A8(7) 985 | DRVCTRL6_A9(7) 986 | DRVCTRL6_A10(7) 987 | DRVCTRL6_A11(7)); 988 pfc_reg_write(PFC_DRVCTRL6, reg); 989 reg = mmio_read_32(PFC_DRVCTRL7); 990 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3) 991 | DRVCTRL7_A13(3) 992 | DRVCTRL7_A14(3) 993 | DRVCTRL7_A15(3) 994 | DRVCTRL7_A16(3) 995 | DRVCTRL7_A17(3) 996 | DRVCTRL7_A18(3) 997 | DRVCTRL7_A19(3)); 998 pfc_reg_write(PFC_DRVCTRL7, reg); 999 reg = mmio_read_32(PFC_DRVCTRL8); 1000 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) 1001 | DRVCTRL8_CS0(7) 1002 | DRVCTRL8_CS1_A2(7) 1003 | DRVCTRL8_BS(7) 1004 | DRVCTRL8_RD(7) 1005 | DRVCTRL8_RD_W(7) 1006 | DRVCTRL8_WE0(7) 1007 | DRVCTRL8_WE1(7)); 1008 pfc_reg_write(PFC_DRVCTRL8, reg); 1009 reg = mmio_read_32(PFC_DRVCTRL9); 1010 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7) 1011 | DRVCTRL9_PRESETOU(7) 1012 | DRVCTRL9_D0(7) 1013 | DRVCTRL9_D1(7) 1014 | DRVCTRL9_D2(7) 1015 | DRVCTRL9_D3(7) 1016 | DRVCTRL9_D4(7) 1017 | DRVCTRL9_D5(7)); 1018 pfc_reg_write(PFC_DRVCTRL9, reg); 1019 reg = mmio_read_32(PFC_DRVCTRL10); 1020 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) 1021 | DRVCTRL10_D7(7) 1022 | DRVCTRL10_D8(3) 1023 | DRVCTRL10_D9(3) 1024 | DRVCTRL10_D10(3) 1025 | DRVCTRL10_D11(3) 1026 | DRVCTRL10_D12(3) 1027 | DRVCTRL10_D13(3)); 1028 pfc_reg_write(PFC_DRVCTRL10, reg); 1029 reg = mmio_read_32(PFC_DRVCTRL11); 1030 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3) 1031 | DRVCTRL11_D15(3) 1032 | DRVCTRL11_AVS1(7) 1033 | DRVCTRL11_AVS2(7) 1034 | DRVCTRL11_HDMI0_CEC(7) 1035 | DRVCTRL11_HDMI1_CEC(7) 1036 | DRVCTRL11_DU_DOTCLKIN0(3) 1037 | DRVCTRL11_DU_DOTCLKIN1(3)); 1038 pfc_reg_write(PFC_DRVCTRL11, reg); 1039 reg = mmio_read_32(PFC_DRVCTRL12); 1040 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3) 1041 | DRVCTRL12_DU_DOTCLKIN3(3) 1042 | DRVCTRL12_DU_FSCLKST(3) 1043 | DRVCTRL12_DU_TMS(3)); 1044 pfc_reg_write(PFC_DRVCTRL12, reg); 1045 reg = mmio_read_32(PFC_DRVCTRL13); 1046 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) 1047 | DRVCTRL13_ASEBRK(3) 1048 | DRVCTRL13_SD0_CLK(7) 1049 | DRVCTRL13_SD0_CMD(7) 1050 | DRVCTRL13_SD0_DAT0(7) 1051 | DRVCTRL13_SD0_DAT1(7) 1052 | DRVCTRL13_SD0_DAT2(7) 1053 | DRVCTRL13_SD0_DAT3(7)); 1054 pfc_reg_write(PFC_DRVCTRL13, reg); 1055 reg = mmio_read_32(PFC_DRVCTRL14); 1056 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7) 1057 | DRVCTRL14_SD1_CMD(7) 1058 | DRVCTRL14_SD1_DAT0(5) 1059 | DRVCTRL14_SD1_DAT1(5) 1060 | DRVCTRL14_SD1_DAT2(5) 1061 | DRVCTRL14_SD1_DAT3(5) 1062 | DRVCTRL14_SD2_CLK(5) 1063 | DRVCTRL14_SD2_CMD(5)); 1064 pfc_reg_write(PFC_DRVCTRL14, reg); 1065 reg = mmio_read_32(PFC_DRVCTRL15); 1066 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5) 1067 | DRVCTRL15_SD2_DAT1(5) 1068 | DRVCTRL15_SD2_DAT2(5) 1069 | DRVCTRL15_SD2_DAT3(5) 1070 | DRVCTRL15_SD2_DS(5) 1071 | DRVCTRL15_SD3_CLK(7) 1072 | DRVCTRL15_SD3_CMD(7) 1073 | DRVCTRL15_SD3_DAT0(7)); 1074 pfc_reg_write(PFC_DRVCTRL15, reg); 1075 reg = mmio_read_32(PFC_DRVCTRL16); 1076 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7) 1077 | DRVCTRL16_SD3_DAT2(7) 1078 | DRVCTRL16_SD3_DAT3(7) 1079 | DRVCTRL16_SD3_DAT4(7) 1080 | DRVCTRL16_SD3_DAT5(7) 1081 | DRVCTRL16_SD3_DAT6(7) 1082 | DRVCTRL16_SD3_DAT7(7) 1083 | DRVCTRL16_SD3_DS(7)); 1084 pfc_reg_write(PFC_DRVCTRL16, reg); 1085 reg = mmio_read_32(PFC_DRVCTRL17); 1086 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7) 1087 | DRVCTRL17_SD0_WP(7) 1088 | DRVCTRL17_SD1_CD(7) 1089 | DRVCTRL17_SD1_WP(7) 1090 | DRVCTRL17_SCK0(7) 1091 | DRVCTRL17_RX0(7) 1092 | DRVCTRL17_TX0(7) 1093 | DRVCTRL17_CTS0(7)); 1094 pfc_reg_write(PFC_DRVCTRL17, reg); 1095 reg = mmio_read_32(PFC_DRVCTRL18); 1096 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7) 1097 | DRVCTRL18_RX1(7) 1098 | DRVCTRL18_TX1(7) 1099 | DRVCTRL18_CTS1(7) 1100 | DRVCTRL18_RTS1_TANS(7) 1101 | DRVCTRL18_SCK2(7) 1102 | DRVCTRL18_TX2(7) 1103 | DRVCTRL18_RX2(7)); 1104 pfc_reg_write(PFC_DRVCTRL18, reg); 1105 reg = mmio_read_32(PFC_DRVCTRL19); 1106 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7) 1107 | DRVCTRL19_HRX0(7) 1108 | DRVCTRL19_HTX0(7) 1109 | DRVCTRL19_HCTS0(7) 1110 | DRVCTRL19_HRTS0(7) 1111 | DRVCTRL19_MSIOF0_SCK(7) 1112 | DRVCTRL19_MSIOF0_SYNC(7) 1113 | DRVCTRL19_MSIOF0_SS1(7)); 1114 pfc_reg_write(PFC_DRVCTRL19, reg); 1115 reg = mmio_read_32(PFC_DRVCTRL20); 1116 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7) 1117 | DRVCTRL20_MSIOF0_SS2(7) 1118 | DRVCTRL20_MSIOF0_RXD(7) 1119 | DRVCTRL20_MLB_CLK(7) 1120 | DRVCTRL20_MLB_SIG(7) 1121 | DRVCTRL20_MLB_DAT(7) 1122 | DRVCTRL20_MLB_REF(7) 1123 | DRVCTRL20_SSI_SCK0129(7)); 1124 pfc_reg_write(PFC_DRVCTRL20, reg); 1125 reg = mmio_read_32(PFC_DRVCTRL21); 1126 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7) 1127 | DRVCTRL21_SSI_SDATA0(7) 1128 | DRVCTRL21_SSI_SDATA1(7) 1129 | DRVCTRL21_SSI_SDATA2(7) 1130 | DRVCTRL21_SSI_SCK34(7) 1131 | DRVCTRL21_SSI_WS34(7) 1132 | DRVCTRL21_SSI_SDATA3(7) 1133 | DRVCTRL21_SSI_SCK4(7)); 1134 pfc_reg_write(PFC_DRVCTRL21, reg); 1135 reg = mmio_read_32(PFC_DRVCTRL22); 1136 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7) 1137 | DRVCTRL22_SSI_SDATA4(7) 1138 | DRVCTRL22_SSI_SCK5(7) 1139 | DRVCTRL22_SSI_WS5(7) 1140 | DRVCTRL22_SSI_SDATA5(7) 1141 | DRVCTRL22_SSI_SCK6(7) 1142 | DRVCTRL22_SSI_WS6(7) 1143 | DRVCTRL22_SSI_SDATA6(7)); 1144 pfc_reg_write(PFC_DRVCTRL22, reg); 1145 reg = mmio_read_32(PFC_DRVCTRL23); 1146 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7) 1147 | DRVCTRL23_SSI_WS78(7) 1148 | DRVCTRL23_SSI_SDATA7(7) 1149 | DRVCTRL23_SSI_SDATA8(7) 1150 | DRVCTRL23_SSI_SDATA9(7) 1151 | DRVCTRL23_AUDIO_CLKA(7) 1152 | DRVCTRL23_AUDIO_CLKB(7) 1153 | DRVCTRL23_USB0_PWEN(7)); 1154 pfc_reg_write(PFC_DRVCTRL23, reg); 1155 reg = mmio_read_32(PFC_DRVCTRL24); 1156 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7) 1157 | DRVCTRL24_USB1_PWEN(7) 1158 | DRVCTRL24_USB1_OVC(7) 1159 | DRVCTRL24_USB30_PWEN(7) 1160 | DRVCTRL24_USB30_OVC(7) 1161 | DRVCTRL24_USB31_PWEN(7) 1162 | DRVCTRL24_USB31_OVC(7)); 1163 pfc_reg_write(PFC_DRVCTRL24, reg); 1164 1165 /* initialize LSI pin pull-up/down control */ 1166 pfc_reg_write(PFC_PUD0, 0x00005FBFU); 1167 pfc_reg_write(PFC_PUD1, 0x00300FFEU); 1168 pfc_reg_write(PFC_PUD2, 0x330001E6U); 1169 pfc_reg_write(PFC_PUD3, 0x000002E0U); 1170 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U); 1171 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U); 1172 pfc_reg_write(PFC_PUD6, 0x00000055U); 1173 1174 /* initialize LSI pin pull-enable register */ 1175 pfc_reg_write(PFC_PUEN0, 0x00000FFFU); 1176 pfc_reg_write(PFC_PUEN1, 0x00100234U); 1177 pfc_reg_write(PFC_PUEN2, 0x000004C4U); 1178 pfc_reg_write(PFC_PUEN3, 0x00000200U); 1179 pfc_reg_write(PFC_PUEN4, 0x3E000000U); 1180 pfc_reg_write(PFC_PUEN5, 0x1F000805U); 1181 pfc_reg_write(PFC_PUEN6, 0x00000006U); 1182 1183 /* initialize positive/negative logic select */ 1184 mmio_write_32(GPIO_POSNEG0, 0x00000000U); 1185 mmio_write_32(GPIO_POSNEG1, 0x00000000U); 1186 mmio_write_32(GPIO_POSNEG2, 0x00000000U); 1187 mmio_write_32(GPIO_POSNEG3, 0x00000000U); 1188 mmio_write_32(GPIO_POSNEG4, 0x00000000U); 1189 mmio_write_32(GPIO_POSNEG5, 0x00000000U); 1190 mmio_write_32(GPIO_POSNEG6, 0x00000000U); 1191 1192 /* initialize general IO/interrupt switching */ 1193 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); 1194 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); 1195 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); 1196 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); 1197 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); 1198 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); 1199 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); 1200 1201 /* initialize general output register */ 1202 mmio_write_32(GPIO_OUTDT1, 0x00000000U); 1203 mmio_write_32(GPIO_OUTDT2, 0x00000400U); 1204 mmio_write_32(GPIO_OUTDT3, 0x0000C000U); 1205 mmio_write_32(GPIO_OUTDT5, 0x00000006U); 1206 mmio_write_32(GPIO_OUTDT6, 0x00003880U); 1207 1208 /* initialize general input/output switching */ 1209 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); 1210 mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U); 1211 mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); 1212 mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); 1213 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); 1214 #if (RCAR_GEN3_ULCB == 1) 1215 mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); 1216 #else 1217 mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); 1218 #endif 1219 mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); 1220 } 1221