1 /* 2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> /* for uint32_t */ 8 9 #include <lib/mmio.h> 10 11 #include "pfc_init_m3.h" 12 #include "rcar_def.h" 13 #include "rcar_private.h" 14 #include "../pfc_regs.h" 15 16 #define GPSR0_D15 BIT(15) 17 #define GPSR0_D14 BIT(14) 18 #define GPSR0_D13 BIT(13) 19 #define GPSR0_D12 BIT(12) 20 #define GPSR0_D11 BIT(11) 21 #define GPSR0_D10 BIT(10) 22 #define GPSR0_D9 BIT(9) 23 #define GPSR0_D8 BIT(8) 24 #define GPSR0_D7 BIT(7) 25 #define GPSR0_D6 BIT(6) 26 #define GPSR0_D5 BIT(5) 27 #define GPSR0_D4 BIT(4) 28 #define GPSR0_D3 BIT(3) 29 #define GPSR0_D2 BIT(2) 30 #define GPSR0_D1 BIT(1) 31 #define GPSR0_D0 BIT(0) 32 #define GPSR1_CLKOUT BIT(28) 33 #define GPSR1_EX_WAIT0_A BIT(27) 34 #define GPSR1_WE1 BIT(26) 35 #define GPSR1_WE0 BIT(25) 36 #define GPSR1_RD_WR BIT(24) 37 #define GPSR1_RD BIT(23) 38 #define GPSR1_BS BIT(22) 39 #define GPSR1_CS1_A26 BIT(21) 40 #define GPSR1_CS0 BIT(20) 41 #define GPSR1_A19 BIT(19) 42 #define GPSR1_A18 BIT(18) 43 #define GPSR1_A17 BIT(17) 44 #define GPSR1_A16 BIT(16) 45 #define GPSR1_A15 BIT(15) 46 #define GPSR1_A14 BIT(14) 47 #define GPSR1_A13 BIT(13) 48 #define GPSR1_A12 BIT(12) 49 #define GPSR1_A11 BIT(11) 50 #define GPSR1_A10 BIT(10) 51 #define GPSR1_A9 BIT(9) 52 #define GPSR1_A8 BIT(8) 53 #define GPSR1_A7 BIT(7) 54 #define GPSR1_A6 BIT(6) 55 #define GPSR1_A5 BIT(5) 56 #define GPSR1_A4 BIT(4) 57 #define GPSR1_A3 BIT(3) 58 #define GPSR1_A2 BIT(2) 59 #define GPSR1_A1 BIT(1) 60 #define GPSR1_A0 BIT(0) 61 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14) 62 #define GPSR2_AVB_AVTP_MATCH_A BIT(13) 63 #define GPSR2_AVB_LINK BIT(12) 64 #define GPSR2_AVB_PHY_INT BIT(11) 65 #define GPSR2_AVB_MAGIC BIT(10) 66 #define GPSR2_AVB_MDC BIT(9) 67 #define GPSR2_PWM2_A BIT(8) 68 #define GPSR2_PWM1_A BIT(7) 69 #define GPSR2_PWM0 BIT(6) 70 #define GPSR2_IRQ5 BIT(5) 71 #define GPSR2_IRQ4 BIT(4) 72 #define GPSR2_IRQ3 BIT(3) 73 #define GPSR2_IRQ2 BIT(2) 74 #define GPSR2_IRQ1 BIT(1) 75 #define GPSR2_IRQ0 BIT(0) 76 #define GPSR3_SD1_WP BIT(15) 77 #define GPSR3_SD1_CD BIT(14) 78 #define GPSR3_SD0_WP BIT(13) 79 #define GPSR3_SD0_CD BIT(12) 80 #define GPSR3_SD1_DAT3 BIT(11) 81 #define GPSR3_SD1_DAT2 BIT(10) 82 #define GPSR3_SD1_DAT1 BIT(9) 83 #define GPSR3_SD1_DAT0 BIT(8) 84 #define GPSR3_SD1_CMD BIT(7) 85 #define GPSR3_SD1_CLK BIT(6) 86 #define GPSR3_SD0_DAT3 BIT(5) 87 #define GPSR3_SD0_DAT2 BIT(4) 88 #define GPSR3_SD0_DAT1 BIT(3) 89 #define GPSR3_SD0_DAT0 BIT(2) 90 #define GPSR3_SD0_CMD BIT(1) 91 #define GPSR3_SD0_CLK BIT(0) 92 #define GPSR4_SD3_DS BIT(17) 93 #define GPSR4_SD3_DAT7 BIT(16) 94 #define GPSR4_SD3_DAT6 BIT(15) 95 #define GPSR4_SD3_DAT5 BIT(14) 96 #define GPSR4_SD3_DAT4 BIT(13) 97 #define GPSR4_SD3_DAT3 BIT(12) 98 #define GPSR4_SD3_DAT2 BIT(11) 99 #define GPSR4_SD3_DAT1 BIT(10) 100 #define GPSR4_SD3_DAT0 BIT(9) 101 #define GPSR4_SD3_CMD BIT(8) 102 #define GPSR4_SD3_CLK BIT(7) 103 #define GPSR4_SD2_DS BIT(6) 104 #define GPSR4_SD2_DAT3 BIT(5) 105 #define GPSR4_SD2_DAT2 BIT(4) 106 #define GPSR4_SD2_DAT1 BIT(3) 107 #define GPSR4_SD2_DAT0 BIT(2) 108 #define GPSR4_SD2_CMD BIT(1) 109 #define GPSR4_SD2_CLK BIT(0) 110 #define GPSR5_MLB_DAT BIT(25) 111 #define GPSR5_MLB_SIG BIT(24) 112 #define GPSR5_MLB_CLK BIT(23) 113 #define GPSR5_MSIOF0_RXD BIT(22) 114 #define GPSR5_MSIOF0_SS2 BIT(21) 115 #define GPSR5_MSIOF0_TXD BIT(20) 116 #define GPSR5_MSIOF0_SS1 BIT(19) 117 #define GPSR5_MSIOF0_SYNC BIT(18) 118 #define GPSR5_MSIOF0_SCK BIT(17) 119 #define GPSR5_HRTS0 BIT(16) 120 #define GPSR5_HCTS0 BIT(15) 121 #define GPSR5_HTX0 BIT(14) 122 #define GPSR5_HRX0 BIT(13) 123 #define GPSR5_HSCK0 BIT(12) 124 #define GPSR5_RX2_A BIT(11) 125 #define GPSR5_TX2_A BIT(10) 126 #define GPSR5_SCK2 BIT(9) 127 #define GPSR5_RTS1_TANS BIT(8) 128 #define GPSR5_CTS1 BIT(7) 129 #define GPSR5_TX1_A BIT(6) 130 #define GPSR5_RX1_A BIT(5) 131 #define GPSR5_RTS0_TANS BIT(4) 132 #define GPSR5_CTS0 BIT(3) 133 #define GPSR5_TX0 BIT(2) 134 #define GPSR5_RX0 BIT(1) 135 #define GPSR5_SCK0 BIT(0) 136 #define GPSR6_USB31_OVC BIT(31) 137 #define GPSR6_USB31_PWEN BIT(30) 138 #define GPSR6_USB30_OVC BIT(29) 139 #define GPSR6_USB30_PWEN BIT(28) 140 #define GPSR6_USB1_OVC BIT(27) 141 #define GPSR6_USB1_PWEN BIT(26) 142 #define GPSR6_USB0_OVC BIT(25) 143 #define GPSR6_USB0_PWEN BIT(24) 144 #define GPSR6_AUDIO_CLKB_B BIT(23) 145 #define GPSR6_AUDIO_CLKA_A BIT(22) 146 #define GPSR6_SSI_SDATA9_A BIT(21) 147 #define GPSR6_SSI_SDATA8 BIT(20) 148 #define GPSR6_SSI_SDATA7 BIT(19) 149 #define GPSR6_SSI_WS78 BIT(18) 150 #define GPSR6_SSI_SCK78 BIT(17) 151 #define GPSR6_SSI_SDATA6 BIT(16) 152 #define GPSR6_SSI_WS6 BIT(15) 153 #define GPSR6_SSI_SCK6 BIT(14) 154 #define GPSR6_SSI_SDATA5 BIT(13) 155 #define GPSR6_SSI_WS5 BIT(12) 156 #define GPSR6_SSI_SCK5 BIT(11) 157 #define GPSR6_SSI_SDATA4 BIT(10) 158 #define GPSR6_SSI_WS4 BIT(9) 159 #define GPSR6_SSI_SCK4 BIT(8) 160 #define GPSR6_SSI_SDATA3 BIT(7) 161 #define GPSR6_SSI_WS34 BIT(6) 162 #define GPSR6_SSI_SCK34 BIT(5) 163 #define GPSR6_SSI_SDATA2_A BIT(4) 164 #define GPSR6_SSI_SDATA1_A BIT(3) 165 #define GPSR6_SSI_SDATA0 BIT(2) 166 #define GPSR6_SSI_WS0129 BIT(1) 167 #define GPSR6_SSI_SCK0129 BIT(0) 168 #define GPSR7_HDMI1_CEC BIT(3) 169 #define GPSR7_HDMI0_CEC BIT(2) 170 #define GPSR7_AVS2 BIT(1) 171 #define GPSR7_AVS1 BIT(0) 172 173 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) 174 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) 175 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) 176 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) 177 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) 178 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) 179 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) 180 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) 181 182 #define POC_SD3_DS_33V BIT(29) 183 #define POC_SD3_DAT7_33V BIT(28) 184 #define POC_SD3_DAT6_33V BIT(27) 185 #define POC_SD3_DAT5_33V BIT(26) 186 #define POC_SD3_DAT4_33V BIT(25) 187 #define POC_SD3_DAT3_33V BIT(24) 188 #define POC_SD3_DAT2_33V BIT(23) 189 #define POC_SD3_DAT1_33V BIT(22) 190 #define POC_SD3_DAT0_33V BIT(21) 191 #define POC_SD3_CMD_33V BIT(20) 192 #define POC_SD3_CLK_33V BIT(19) 193 #define POC_SD2_DS_33V BIT(18) 194 #define POC_SD2_DAT3_33V BIT(17) 195 #define POC_SD2_DAT2_33V BIT(16) 196 #define POC_SD2_DAT1_33V BIT(15) 197 #define POC_SD2_DAT0_33V BIT(14) 198 #define POC_SD2_CMD_33V BIT(13) 199 #define POC_SD2_CLK_33V BIT(12) 200 #define POC_SD1_DAT3_33V BIT(11) 201 #define POC_SD1_DAT2_33V BIT(10) 202 #define POC_SD1_DAT1_33V BIT(9) 203 #define POC_SD1_DAT0_33V BIT(8) 204 #define POC_SD1_CMD_33V BIT(7) 205 #define POC_SD1_CLK_33V BIT(6) 206 #define POC_SD0_DAT3_33V BIT(5) 207 #define POC_SD0_DAT2_33V BIT(4) 208 #define POC_SD0_DAT1_33V BIT(3) 209 #define POC_SD0_DAT0_33V BIT(2) 210 #define POC_SD0_CMD_33V BIT(1) 211 #define POC_SD0_CLK_33V BIT(0) 212 213 #define DRVCTRL0_MASK (0xCCCCCCCCU) 214 #define DRVCTRL1_MASK (0xCCCCCCC8U) 215 #define DRVCTRL2_MASK (0x88888888U) 216 #define DRVCTRL3_MASK (0x88888888U) 217 #define DRVCTRL4_MASK (0x88888888U) 218 #define DRVCTRL5_MASK (0x88888888U) 219 #define DRVCTRL6_MASK (0x88888888U) 220 #define DRVCTRL7_MASK (0x88888888U) 221 #define DRVCTRL8_MASK (0x88888888U) 222 #define DRVCTRL9_MASK (0x88888888U) 223 #define DRVCTRL10_MASK (0x88888888U) 224 #define DRVCTRL11_MASK (0x888888CCU) 225 #define DRVCTRL12_MASK (0xCCCFFFCFU) 226 #define DRVCTRL13_MASK (0xCC888888U) 227 #define DRVCTRL14_MASK (0x88888888U) 228 #define DRVCTRL15_MASK (0x88888888U) 229 #define DRVCTRL16_MASK (0x88888888U) 230 #define DRVCTRL17_MASK (0x88888888U) 231 #define DRVCTRL18_MASK (0x88888888U) 232 #define DRVCTRL19_MASK (0x88888888U) 233 #define DRVCTRL20_MASK (0x88888888U) 234 #define DRVCTRL21_MASK (0x88888888U) 235 #define DRVCTRL22_MASK (0x88888888U) 236 #define DRVCTRL23_MASK (0x88888888U) 237 #define DRVCTRL24_MASK (0x8888888FU) 238 239 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) 240 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) 241 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) 242 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) 243 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) 244 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) 245 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) 246 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) 247 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) 248 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) 249 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) 250 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) 251 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) 252 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) 253 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) 254 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) 255 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) 256 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) 257 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) 258 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) 259 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) 260 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) 261 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) 262 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) 263 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) 264 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) 265 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) 266 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) 267 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) 268 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) 269 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) 270 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) 271 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) 272 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) 273 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) 274 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) 275 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) 276 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) 277 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) 278 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) 279 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) 280 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) 281 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) 282 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) 283 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) 284 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) 285 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) 286 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) 287 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) 288 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) 289 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) 290 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) 291 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) 292 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) 293 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) 294 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) 295 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) 296 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) 297 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) 298 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) 299 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) 300 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) 301 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) 302 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) 303 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) 304 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) 305 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) 306 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) 307 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) 308 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) 309 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) 310 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) 311 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) 312 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) 313 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) 314 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) 315 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) 316 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) 317 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) 318 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) 319 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) 320 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) 321 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) 322 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) 323 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) 324 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) 325 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) 326 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) 327 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) 328 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) 329 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) 330 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) 331 #define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U) 332 #define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U) 333 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) 334 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) 335 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) 336 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) 337 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) 338 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) 339 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) 340 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) 341 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) 342 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) 343 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) 344 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) 345 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) 346 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) 347 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) 348 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) 349 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) 350 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) 351 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) 352 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) 353 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) 354 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) 355 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) 356 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) 357 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) 358 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) 359 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) 360 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) 361 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) 362 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) 363 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) 364 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) 365 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) 366 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) 367 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) 368 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) 369 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) 370 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) 371 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) 372 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) 373 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) 374 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) 375 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) 376 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) 377 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) 378 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) 379 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) 380 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) 381 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) 382 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) 383 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) 384 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) 385 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) 386 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) 387 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) 388 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) 389 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) 390 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) 391 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) 392 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) 393 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) 394 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) 395 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) 396 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) 397 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) 398 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) 399 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) 400 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) 401 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) 402 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) 403 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) 404 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) 405 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) 406 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) 407 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) 408 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) 409 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) 410 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) 411 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) 412 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) 413 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) 414 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) 415 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) 416 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) 417 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) 418 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) 419 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) 420 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) 421 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) 422 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) 423 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) 424 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) 425 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) 426 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) 427 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) 428 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) 429 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) 430 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) 431 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) 432 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) 433 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) 434 435 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) 436 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) 437 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) 438 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) 439 #define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U) 440 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) 441 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) 442 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) 443 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) 444 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) 445 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) 446 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) 447 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) 448 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) 449 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) 450 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) 451 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) 452 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) 453 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) 454 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) 455 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U) 456 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U) 457 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) 458 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) 459 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U) 460 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U) 461 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U) 462 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U) 463 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U) 464 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U) 465 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U) 466 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U) 467 #define MOD_SEL0_FSO_A ((uint32_t)0U << 15U) 468 #define MOD_SEL0_FSO_B ((uint32_t)1U << 15U) 469 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U) 470 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U) 471 #define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U) 472 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U) 473 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U) 474 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U) 475 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U) 476 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U) 477 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U) 478 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U) 479 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U) 480 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U) 481 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U) 482 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U) 483 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U) 484 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U) 485 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U) 486 #define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U) 487 #define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U) 488 #define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U) 489 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) 490 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) 491 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) 492 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) 493 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) 494 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) 495 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) 496 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) 497 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) 498 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) 499 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) 500 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) 501 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) 502 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) 503 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) 504 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) 505 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) 506 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) 507 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) 508 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) 509 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) 510 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) 511 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) 512 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) 513 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) 514 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) 515 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) 516 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) 517 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) 518 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) 519 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) 520 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) 521 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) 522 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) 523 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) 524 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) 525 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) 526 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) 527 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) 528 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) 529 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) 530 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) 531 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) 532 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) 533 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) 534 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) 535 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) 536 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) 537 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) 538 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) 539 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) 540 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) 541 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) 542 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) 543 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) 544 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) 545 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) 546 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) 547 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) 548 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) 549 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) 550 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) 551 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) 552 #define MOD_SEL2_FM_A ((uint32_t)0U << 27U) 553 #define MOD_SEL2_FM_B ((uint32_t)1U << 27U) 554 #define MOD_SEL2_FM_C ((uint32_t)2U << 27U) 555 #define MOD_SEL2_FM_D ((uint32_t)3U << 27U) 556 #define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U) 557 #define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U) 558 #define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U) 559 #define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U) 560 #define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U) 561 #define MOD_SEL2_NDF_A ((uint32_t)0U << 22U) 562 #define MOD_SEL2_NDF_B ((uint32_t)1U << 22U) 563 #define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U) 564 #define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U) 565 #define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U) 566 #define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U) 567 #define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U) 568 #define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U) 569 #define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U) 570 #define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U) 571 #define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U) 572 #define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U) 573 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) 574 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) 575 576 /* SCIF3 Registers for Dummy write */ 577 #define SCIF3_BASE (0xE6C50000U) 578 #define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) 579 #define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) 580 #define SCFCR_DATA (0x0000U) 581 582 /* Realtime module stop control */ 583 #define CPG_BASE (0xE6150000U) 584 #define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U) 585 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U) 586 #define SCMSTPCR0_RTDMAC (0x00200000U) 587 588 /* RT-DMAC Registers */ 589 #define RTDMAC_CH (0U) /* choose 0 to 15 */ 590 591 #define RTDMAC_BASE (0xFFC10000U) 592 #define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) 593 #define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) 594 #define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) 595 #define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) 596 #define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) 597 #define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) 598 #define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) 599 #define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) 600 #define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) 601 #define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) 602 #define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) 603 #define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) 604 605 #define RDMOR_DME (0x0001U) /* DMA Master Enable */ 606 #define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ 607 #define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ 608 #define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ 609 #define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ 610 #define RDMCHCR_DE (0x00000001U) /* DMA Enable */ 611 #define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ 612 #define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ 613 #define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ 614 615 static void start_rtdma0_descriptor(void) 616 { 617 uint32_t reg; 618 619 reg = mmio_read_32(RCAR_PRR); 620 reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 621 if (reg == (RCAR_PRODUCT_M3_CUT10)) { 622 /* Enable clock supply to RTDMAC. */ 623 mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC); 624 625 /* Initialize ch0, Reset Descriptor */ 626 mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH)); 627 mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST); 628 629 /* Enable DMA */ 630 mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); 631 632 /* Set first transfer */ 633 mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR); 634 mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR); 635 mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U); 636 637 /* Set descriptor */ 638 mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U); 639 mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U); 640 mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U); 641 mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256); 642 mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE 643 | RDMDPBASE_SEL_EXT); 644 645 /* Set transfer parameter, Start transfer */ 646 mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE 647 | RDMCHCR_RPT_TCR 648 | RDMCHCR_TS_2 649 | RDMCHCR_RS_AUTO 650 | RDMCHCR_DE); 651 } 652 } 653 654 static void pfc_reg_write(uint32_t addr, uint32_t data) 655 { 656 uint32_t prr; 657 658 prr = mmio_read_32(RCAR_PRR); 659 prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 660 661 mmio_write_32(PFC_PMMR, ~data); 662 if (prr == (RCAR_PRODUCT_M3_CUT10)) { 663 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ 664 } 665 mmio_write_32((uintptr_t)addr, data); 666 if (prr == (RCAR_PRODUCT_M3_CUT10)) { 667 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ 668 } 669 } 670 671 void pfc_init_m3(void) 672 { 673 uint32_t reg; 674 675 /* Work around for PFC eratta */ 676 start_rtdma0_descriptor(); 677 678 /* initialize module select */ 679 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A 680 | MOD_SEL0_MSIOF2_A 681 | MOD_SEL0_MSIOF1_A 682 | MOD_SEL0_LBSC_A 683 | MOD_SEL0_IEBUS_A 684 | MOD_SEL0_I2C2_A 685 | MOD_SEL0_I2C1_A 686 | MOD_SEL0_HSCIF4_A 687 | MOD_SEL0_HSCIF3_A 688 | MOD_SEL0_HSCIF1_A 689 | MOD_SEL0_FSO_A 690 | MOD_SEL0_HSCIF2_A 691 | MOD_SEL0_ETHERAVB_A 692 | MOD_SEL0_DRIF3_A 693 | MOD_SEL0_DRIF2_A 694 | MOD_SEL0_DRIF1_A 695 | MOD_SEL0_DRIF0_A 696 | MOD_SEL0_CANFD0_A 697 | MOD_SEL0_ADG_A_A); 698 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A 699 | MOD_SEL1_TSIF0_A 700 | MOD_SEL1_TIMER_TMU_A 701 | MOD_SEL1_SSP1_1_A 702 | MOD_SEL1_SSP1_0_A 703 | MOD_SEL1_SSI_A 704 | MOD_SEL1_SPEED_PULSE_IF_A 705 | MOD_SEL1_SIMCARD_A 706 | MOD_SEL1_SDHI2_A 707 | MOD_SEL1_SCIF4_A 708 | MOD_SEL1_SCIF3_A 709 | MOD_SEL1_SCIF2_A 710 | MOD_SEL1_SCIF1_A 711 | MOD_SEL1_SCIF_A 712 | MOD_SEL1_REMOCON_A 713 | MOD_SEL1_RCAN0_A 714 | MOD_SEL1_PWM6_A 715 | MOD_SEL1_PWM5_A 716 | MOD_SEL1_PWM4_A 717 | MOD_SEL1_PWM3_A 718 | MOD_SEL1_PWM2_A 719 | MOD_SEL1_PWM1_A); 720 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A 721 | MOD_SEL2_I2C_3_A 722 | MOD_SEL2_I2C_0_A 723 | MOD_SEL2_FM_A 724 | MOD_SEL2_SCIF5_A 725 | MOD_SEL2_I2C6_A 726 | MOD_SEL2_NDF_A 727 | MOD_SEL2_SSI2_A 728 | MOD_SEL2_SSI9_A 729 | MOD_SEL2_TIMER_TMU2_A 730 | MOD_SEL2_ADG_B_A 731 | MOD_SEL2_ADG_C_A 732 | MOD_SEL2_VIN4_A); 733 734 /* initialize peripheral function select */ 735 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) 736 | IPSR_24_FUNC(0) 737 | IPSR_20_FUNC(0) 738 | IPSR_16_FUNC(0) 739 | IPSR_12_FUNC(0) 740 | IPSR_8_FUNC(0) 741 | IPSR_4_FUNC(0) 742 | IPSR_0_FUNC(0)); 743 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6) 744 | IPSR_24_FUNC(0) 745 | IPSR_20_FUNC(0) 746 | IPSR_16_FUNC(0) 747 | IPSR_12_FUNC(3) 748 | IPSR_8_FUNC(3) 749 | IPSR_4_FUNC(3) 750 | IPSR_0_FUNC(3)); 751 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) 752 | IPSR_24_FUNC(6) 753 | IPSR_20_FUNC(6) 754 | IPSR_16_FUNC(6) 755 | IPSR_12_FUNC(6) 756 | IPSR_8_FUNC(6) 757 | IPSR_4_FUNC(6) 758 | IPSR_0_FUNC(6)); 759 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6) 760 | IPSR_24_FUNC(6) 761 | IPSR_20_FUNC(6) 762 | IPSR_16_FUNC(6) 763 | IPSR_12_FUNC(6) 764 | IPSR_8_FUNC(0) 765 | IPSR_4_FUNC(0) 766 | IPSR_0_FUNC(0)); 767 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) 768 | IPSR_24_FUNC(0) 769 | IPSR_20_FUNC(0) 770 | IPSR_16_FUNC(0) 771 | IPSR_12_FUNC(0) 772 | IPSR_8_FUNC(6) 773 | IPSR_4_FUNC(6) 774 | IPSR_0_FUNC(6)); 775 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) 776 | IPSR_24_FUNC(0) 777 | IPSR_20_FUNC(0) 778 | IPSR_16_FUNC(0) 779 | IPSR_12_FUNC(0) 780 | IPSR_8_FUNC(6) 781 | IPSR_4_FUNC(0) 782 | IPSR_0_FUNC(0)); 783 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6) 784 | IPSR_24_FUNC(6) 785 | IPSR_20_FUNC(6) 786 | IPSR_16_FUNC(6) 787 | IPSR_12_FUNC(6) 788 | IPSR_8_FUNC(0) 789 | IPSR_4_FUNC(0) 790 | IPSR_0_FUNC(0)); 791 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) 792 | IPSR_24_FUNC(0) 793 | IPSR_20_FUNC(0) 794 | IPSR_16_FUNC(0) 795 | IPSR_12_FUNC(0) 796 | IPSR_8_FUNC(6) 797 | IPSR_4_FUNC(6) 798 | IPSR_0_FUNC(6)); 799 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1) 800 | IPSR_24_FUNC(1) 801 | IPSR_20_FUNC(1) 802 | IPSR_16_FUNC(1) 803 | IPSR_12_FUNC(0) 804 | IPSR_8_FUNC(0) 805 | IPSR_4_FUNC(0) 806 | IPSR_0_FUNC(0)); 807 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) 808 | IPSR_24_FUNC(0) 809 | IPSR_20_FUNC(0) 810 | IPSR_16_FUNC(0) 811 | IPSR_12_FUNC(0) 812 | IPSR_8_FUNC(0) 813 | IPSR_4_FUNC(0) 814 | IPSR_0_FUNC(0)); 815 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1) 816 | IPSR_24_FUNC(0) 817 | IPSR_20_FUNC(0) 818 | IPSR_16_FUNC(0) 819 | IPSR_12_FUNC(0) 820 | IPSR_8_FUNC(0) 821 | IPSR_4_FUNC(0) 822 | IPSR_0_FUNC(0)); 823 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0) 824 | IPSR_24_FUNC(4) 825 | IPSR_20_FUNC(0) 826 | IPSR_16_FUNC(0) 827 | IPSR_12_FUNC(0) 828 | IPSR_8_FUNC(0) 829 | IPSR_4_FUNC(0) 830 | IPSR_0_FUNC(1)); 831 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0) 832 | IPSR_24_FUNC(0) 833 | IPSR_20_FUNC(0) 834 | IPSR_16_FUNC(0) 835 | IPSR_12_FUNC(0) 836 | IPSR_8_FUNC(4) 837 | IPSR_4_FUNC(0) 838 | IPSR_0_FUNC(0)); 839 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8) 840 | IPSR_24_FUNC(0) 841 | IPSR_20_FUNC(0) 842 | IPSR_16_FUNC(0) 843 | IPSR_12_FUNC(0) 844 | IPSR_8_FUNC(3) 845 | IPSR_4_FUNC(0) 846 | IPSR_0_FUNC(0)); 847 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0) 848 | IPSR_24_FUNC(0) 849 | IPSR_20_FUNC(0) 850 | IPSR_16_FUNC(0) 851 | IPSR_12_FUNC(0) 852 | IPSR_8_FUNC(0) 853 | IPSR_4_FUNC(3) 854 | IPSR_0_FUNC(8)); 855 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) 856 | IPSR_24_FUNC(0) 857 | IPSR_20_FUNC(0) 858 | IPSR_16_FUNC(0) 859 | IPSR_12_FUNC(0) 860 | IPSR_8_FUNC(0) 861 | IPSR_4_FUNC(0) 862 | IPSR_0_FUNC(0)); 863 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0) 864 | IPSR_24_FUNC(0) 865 | IPSR_20_FUNC(0) 866 | IPSR_16_FUNC(0) 867 | IPSR_12_FUNC(0) 868 | IPSR_8_FUNC(0) 869 | IPSR_4_FUNC(0) 870 | IPSR_0_FUNC(0)); 871 pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0) 872 | IPSR_24_FUNC(0) 873 | IPSR_20_FUNC(0) 874 | IPSR_16_FUNC(0) 875 | IPSR_12_FUNC(0) 876 | IPSR_8_FUNC(0) 877 | IPSR_4_FUNC(1) 878 | IPSR_0_FUNC(0)); 879 pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0) 880 | IPSR_0_FUNC(0)); 881 882 /* initialize GPIO/perihperal function select */ 883 pfc_reg_write(PFC_GPSR0, GPSR0_D15 884 | GPSR0_D14 885 | GPSR0_D13 886 | GPSR0_D12 887 | GPSR0_D11 888 | GPSR0_D10 889 | GPSR0_D9 890 | GPSR0_D8); 891 pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT 892 | GPSR1_EX_WAIT0_A 893 | GPSR1_A19 894 | GPSR1_A18 895 | GPSR1_A17 896 | GPSR1_A16 897 | GPSR1_A15 898 | GPSR1_A14 899 | GPSR1_A13 900 | GPSR1_A12 901 | GPSR1_A7 902 | GPSR1_A6 903 | GPSR1_A5 904 | GPSR1_A4 905 | GPSR1_A3 906 | GPSR1_A2 907 | GPSR1_A1 908 | GPSR1_A0); 909 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A 910 | GPSR2_AVB_AVTP_MATCH_A 911 | GPSR2_AVB_LINK 912 | GPSR2_AVB_PHY_INT 913 | GPSR2_AVB_MDC 914 | GPSR2_PWM2_A 915 | GPSR2_PWM1_A 916 | GPSR2_IRQ5 917 | GPSR2_IRQ4 918 | GPSR2_IRQ3 919 | GPSR2_IRQ2 920 | GPSR2_IRQ1 921 | GPSR2_IRQ0); 922 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP 923 | GPSR3_SD0_CD 924 | GPSR3_SD1_DAT3 925 | GPSR3_SD1_DAT2 926 | GPSR3_SD1_DAT1 927 | GPSR3_SD1_DAT0 928 | GPSR3_SD0_DAT3 929 | GPSR3_SD0_DAT2 930 | GPSR3_SD0_DAT1 931 | GPSR3_SD0_DAT0 932 | GPSR3_SD0_CMD 933 | GPSR3_SD0_CLK); 934 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7 935 | GPSR4_SD3_DAT6 936 | GPSR4_SD3_DAT3 937 | GPSR4_SD3_DAT2 938 | GPSR4_SD3_DAT1 939 | GPSR4_SD3_DAT0 940 | GPSR4_SD3_CMD 941 | GPSR4_SD3_CLK 942 | GPSR4_SD2_DS 943 | GPSR4_SD2_DAT3 944 | GPSR4_SD2_DAT2 945 | GPSR4_SD2_DAT1 946 | GPSR4_SD2_DAT0 947 | GPSR4_SD2_CMD 948 | GPSR4_SD2_CLK); 949 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2 950 | GPSR5_MSIOF0_SS1 951 | GPSR5_MSIOF0_SYNC 952 | GPSR5_HRTS0 953 | GPSR5_HCTS0 954 | GPSR5_HTX0 955 | GPSR5_HRX0 956 | GPSR5_HSCK0 957 | GPSR5_RX2_A 958 | GPSR5_TX2_A 959 | GPSR5_SCK2 960 | GPSR5_RTS1_TANS 961 | GPSR5_CTS1 962 | GPSR5_TX1_A 963 | GPSR5_RX1_A 964 | GPSR5_RTS0_TANS 965 | GPSR5_SCK0); 966 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC 967 | GPSR6_USB30_PWEN 968 | GPSR6_USB1_OVC 969 | GPSR6_USB1_PWEN 970 | GPSR6_USB0_OVC 971 | GPSR6_USB0_PWEN 972 | GPSR6_AUDIO_CLKB_B 973 | GPSR6_AUDIO_CLKA_A 974 | GPSR6_SSI_SDATA8 975 | GPSR6_SSI_SDATA7 976 | GPSR6_SSI_WS78 977 | GPSR6_SSI_SCK78 978 | GPSR6_SSI_WS6 979 | GPSR6_SSI_SCK6 980 | GPSR6_SSI_SDATA4 981 | GPSR6_SSI_WS4 982 | GPSR6_SSI_SCK4 983 | GPSR6_SSI_SDATA1_A 984 | GPSR6_SSI_SDATA0 985 | GPSR6_SSI_WS0129 986 | GPSR6_SSI_SCK0129); 987 pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC 988 | GPSR7_HDMI0_CEC 989 | GPSR7_AVS2 990 | GPSR7_AVS1); 991 992 /* initialize POC control register */ 993 pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V 994 | POC_SD3_DAT7_33V 995 | POC_SD3_DAT6_33V 996 | POC_SD3_DAT5_33V 997 | POC_SD3_DAT4_33V 998 | POC_SD3_DAT3_33V 999 | POC_SD3_DAT2_33V 1000 | POC_SD3_DAT1_33V 1001 | POC_SD3_DAT0_33V 1002 | POC_SD3_CMD_33V 1003 | POC_SD3_CLK_33V 1004 | POC_SD0_DAT3_33V 1005 | POC_SD0_DAT2_33V 1006 | POC_SD0_DAT1_33V 1007 | POC_SD0_DAT0_33V 1008 | POC_SD0_CMD_33V 1009 | POC_SD0_CLK_33V); 1010 1011 /* initialize DRV control register */ 1012 reg = mmio_read_32(PFC_DRVCTRL0); 1013 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) 1014 | DRVCTRL0_QSPI0_MOSI_IO0(3) 1015 | DRVCTRL0_QSPI0_MISO_IO1(3) 1016 | DRVCTRL0_QSPI0_IO2(3) 1017 | DRVCTRL0_QSPI0_IO3(3) 1018 | DRVCTRL0_QSPI0_SSL(3) 1019 | DRVCTRL0_QSPI1_SPCLK(3) 1020 | DRVCTRL0_QSPI1_MOSI_IO0(3)); 1021 pfc_reg_write(PFC_DRVCTRL0, reg); 1022 reg = mmio_read_32(PFC_DRVCTRL1); 1023 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) 1024 | DRVCTRL1_QSPI1_IO2(3) 1025 | DRVCTRL1_QSPI1_IO3(3) 1026 | DRVCTRL1_QSPI1_SS(3) 1027 | DRVCTRL1_RPC_INT(3) 1028 | DRVCTRL1_RPC_WP(3) 1029 | DRVCTRL1_RPC_RESET(3) 1030 | DRVCTRL1_AVB_RX_CTL(7)); 1031 pfc_reg_write(PFC_DRVCTRL1, reg); 1032 reg = mmio_read_32(PFC_DRVCTRL2); 1033 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) 1034 | DRVCTRL2_AVB_RD0(7) 1035 | DRVCTRL2_AVB_RD1(7) 1036 | DRVCTRL2_AVB_RD2(7) 1037 | DRVCTRL2_AVB_RD3(7) 1038 | DRVCTRL2_AVB_TX_CTL(3) 1039 | DRVCTRL2_AVB_TXC(3) 1040 | DRVCTRL2_AVB_TD0(3)); 1041 pfc_reg_write(PFC_DRVCTRL2, reg); 1042 reg = mmio_read_32(PFC_DRVCTRL3); 1043 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3) 1044 | DRVCTRL3_AVB_TD2(3) 1045 | DRVCTRL3_AVB_TD3(3) 1046 | DRVCTRL3_AVB_TXCREFCLK(7) 1047 | DRVCTRL3_AVB_MDIO(7) 1048 | DRVCTRL3_AVB_MDC(7) 1049 | DRVCTRL3_AVB_MAGIC(7) 1050 | DRVCTRL3_AVB_PHY_INT(7)); 1051 pfc_reg_write(PFC_DRVCTRL3, reg); 1052 reg = mmio_read_32(PFC_DRVCTRL4); 1053 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) 1054 | DRVCTRL4_AVB_AVTP_MATCH(7) 1055 | DRVCTRL4_AVB_AVTP_CAPTURE(7) 1056 | DRVCTRL4_IRQ0(7) 1057 | DRVCTRL4_IRQ1(7) 1058 | DRVCTRL4_IRQ2(7) 1059 | DRVCTRL4_IRQ3(7) 1060 | DRVCTRL4_IRQ4(7)); 1061 pfc_reg_write(PFC_DRVCTRL4, reg); 1062 reg = mmio_read_32(PFC_DRVCTRL5); 1063 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) 1064 | DRVCTRL5_PWM0(7) 1065 | DRVCTRL5_PWM1(7) 1066 | DRVCTRL5_PWM2(7) 1067 | DRVCTRL5_A0(3) 1068 | DRVCTRL5_A1(3) 1069 | DRVCTRL5_A2(3) 1070 | DRVCTRL5_A3(3)); 1071 pfc_reg_write(PFC_DRVCTRL5, reg); 1072 reg = mmio_read_32(PFC_DRVCTRL6); 1073 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3) 1074 | DRVCTRL6_A5(3) 1075 | DRVCTRL6_A6(3) 1076 | DRVCTRL6_A7(3) 1077 | DRVCTRL6_A8(7) 1078 | DRVCTRL6_A9(7) 1079 | DRVCTRL6_A10(7) 1080 | DRVCTRL6_A11(7)); 1081 pfc_reg_write(PFC_DRVCTRL6, reg); 1082 reg = mmio_read_32(PFC_DRVCTRL7); 1083 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3) 1084 | DRVCTRL7_A13(3) 1085 | DRVCTRL7_A14(3) 1086 | DRVCTRL7_A15(3) 1087 | DRVCTRL7_A16(3) 1088 | DRVCTRL7_A17(3) 1089 | DRVCTRL7_A18(3) 1090 | DRVCTRL7_A19(3)); 1091 pfc_reg_write(PFC_DRVCTRL7, reg); 1092 reg = mmio_read_32(PFC_DRVCTRL8); 1093 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) 1094 | DRVCTRL8_CS0(7) 1095 | DRVCTRL8_CS1_A2(7) 1096 | DRVCTRL8_BS(7) 1097 | DRVCTRL8_RD(7) 1098 | DRVCTRL8_RD_W(7) 1099 | DRVCTRL8_WE0(7) 1100 | DRVCTRL8_WE1(7)); 1101 pfc_reg_write(PFC_DRVCTRL8, reg); 1102 reg = mmio_read_32(PFC_DRVCTRL9); 1103 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7) 1104 | DRVCTRL9_PRESETOU(7) 1105 | DRVCTRL9_D0(7) 1106 | DRVCTRL9_D1(7) 1107 | DRVCTRL9_D2(7) 1108 | DRVCTRL9_D3(7) 1109 | DRVCTRL9_D4(7) 1110 | DRVCTRL9_D5(7)); 1111 pfc_reg_write(PFC_DRVCTRL9, reg); 1112 reg = mmio_read_32(PFC_DRVCTRL10); 1113 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) 1114 | DRVCTRL10_D7(7) 1115 | DRVCTRL10_D8(3) 1116 | DRVCTRL10_D9(3) 1117 | DRVCTRL10_D10(3) 1118 | DRVCTRL10_D11(3) 1119 | DRVCTRL10_D12(3) 1120 | DRVCTRL10_D13(3)); 1121 pfc_reg_write(PFC_DRVCTRL10, reg); 1122 reg = mmio_read_32(PFC_DRVCTRL11); 1123 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3) 1124 | DRVCTRL11_D15(3) 1125 | DRVCTRL11_AVS1(7) 1126 | DRVCTRL11_AVS2(7) 1127 | DRVCTRL11_HDMI0_CEC(7) 1128 | DRVCTRL11_HDMI1_CEC(7) 1129 | DRVCTRL11_DU_DOTCLKIN0(3) 1130 | DRVCTRL11_DU_DOTCLKIN1(3)); 1131 pfc_reg_write(PFC_DRVCTRL11, reg); 1132 reg = mmio_read_32(PFC_DRVCTRL12); 1133 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3) 1134 | DRVCTRL12_DU_DOTCLKIN3(3) 1135 | DRVCTRL12_DU_FSCLKST(3) 1136 | DRVCTRL12_DU_TMS(3)); 1137 pfc_reg_write(PFC_DRVCTRL12, reg); 1138 reg = mmio_read_32(PFC_DRVCTRL13); 1139 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) 1140 | DRVCTRL13_ASEBRK(3) 1141 | DRVCTRL13_SD0_CLK(7) 1142 | DRVCTRL13_SD0_CMD(7) 1143 | DRVCTRL13_SD0_DAT0(7) 1144 | DRVCTRL13_SD0_DAT1(7) 1145 | DRVCTRL13_SD0_DAT2(7) 1146 | DRVCTRL13_SD0_DAT3(7)); 1147 pfc_reg_write(PFC_DRVCTRL13, reg); 1148 reg = mmio_read_32(PFC_DRVCTRL14); 1149 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7) 1150 | DRVCTRL14_SD1_CMD(7) 1151 | DRVCTRL14_SD1_DAT0(5) 1152 | DRVCTRL14_SD1_DAT1(5) 1153 | DRVCTRL14_SD1_DAT2(5) 1154 | DRVCTRL14_SD1_DAT3(5) 1155 | DRVCTRL14_SD2_CLK(5) 1156 | DRVCTRL14_SD2_CMD(5)); 1157 pfc_reg_write(PFC_DRVCTRL14, reg); 1158 reg = mmio_read_32(PFC_DRVCTRL15); 1159 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5) 1160 | DRVCTRL15_SD2_DAT1(5) 1161 | DRVCTRL15_SD2_DAT2(5) 1162 | DRVCTRL15_SD2_DAT3(5) 1163 | DRVCTRL15_SD2_DS(5) 1164 | DRVCTRL15_SD3_CLK(7) 1165 | DRVCTRL15_SD3_CMD(7) 1166 | DRVCTRL15_SD3_DAT0(7)); 1167 pfc_reg_write(PFC_DRVCTRL15, reg); 1168 reg = mmio_read_32(PFC_DRVCTRL16); 1169 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7) 1170 | DRVCTRL16_SD3_DAT2(7) 1171 | DRVCTRL16_SD3_DAT3(7) 1172 | DRVCTRL16_SD3_DAT4(7) 1173 | DRVCTRL16_SD3_DAT5(7) 1174 | DRVCTRL16_SD3_DAT6(7) 1175 | DRVCTRL16_SD3_DAT7(7) 1176 | DRVCTRL16_SD3_DS(7)); 1177 pfc_reg_write(PFC_DRVCTRL16, reg); 1178 reg = mmio_read_32(PFC_DRVCTRL17); 1179 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7) 1180 | DRVCTRL17_SD0_WP(7) 1181 | DRVCTRL17_SD1_CD(7) 1182 | DRVCTRL17_SD1_WP(7) 1183 | DRVCTRL17_SCK0(7) 1184 | DRVCTRL17_RX0(7) 1185 | DRVCTRL17_TX0(7) 1186 | DRVCTRL17_CTS0(7)); 1187 pfc_reg_write(PFC_DRVCTRL17, reg); 1188 reg = mmio_read_32(PFC_DRVCTRL18); 1189 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7) 1190 | DRVCTRL18_RX1(7) 1191 | DRVCTRL18_TX1(7) 1192 | DRVCTRL18_CTS1(7) 1193 | DRVCTRL18_RTS1_TANS(7) 1194 | DRVCTRL18_SCK2(7) 1195 | DRVCTRL18_TX2(7) 1196 | DRVCTRL18_RX2(7)); 1197 pfc_reg_write(PFC_DRVCTRL18, reg); 1198 reg = mmio_read_32(PFC_DRVCTRL19); 1199 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7) 1200 | DRVCTRL19_HRX0(7) 1201 | DRVCTRL19_HTX0(7) 1202 | DRVCTRL19_HCTS0(7) 1203 | DRVCTRL19_HRTS0(7) 1204 | DRVCTRL19_MSIOF0_SCK(7) 1205 | DRVCTRL19_MSIOF0_SYNC(7) 1206 | DRVCTRL19_MSIOF0_SS1(7)); 1207 pfc_reg_write(PFC_DRVCTRL19, reg); 1208 reg = mmio_read_32(PFC_DRVCTRL20); 1209 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7) 1210 | DRVCTRL20_MSIOF0_SS2(7) 1211 | DRVCTRL20_MSIOF0_RXD(7) 1212 | DRVCTRL20_MLB_CLK(7) 1213 | DRVCTRL20_MLB_SIG(7) 1214 | DRVCTRL20_MLB_DAT(7) 1215 | DRVCTRL20_MLB_REF(7) 1216 | DRVCTRL20_SSI_SCK0129(7)); 1217 pfc_reg_write(PFC_DRVCTRL20, reg); 1218 reg = mmio_read_32(PFC_DRVCTRL21); 1219 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7) 1220 | DRVCTRL21_SSI_SDATA0(7) 1221 | DRVCTRL21_SSI_SDATA1(7) 1222 | DRVCTRL21_SSI_SDATA2(7) 1223 | DRVCTRL21_SSI_SCK34(7) 1224 | DRVCTRL21_SSI_WS34(7) 1225 | DRVCTRL21_SSI_SDATA3(7) 1226 | DRVCTRL21_SSI_SCK4(7)); 1227 pfc_reg_write(PFC_DRVCTRL21, reg); 1228 reg = mmio_read_32(PFC_DRVCTRL22); 1229 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7) 1230 | DRVCTRL22_SSI_SDATA4(7) 1231 | DRVCTRL22_SSI_SCK5(7) 1232 | DRVCTRL22_SSI_WS5(7) 1233 | DRVCTRL22_SSI_SDATA5(7) 1234 | DRVCTRL22_SSI_SCK6(7) 1235 | DRVCTRL22_SSI_WS6(7) 1236 | DRVCTRL22_SSI_SDATA6(7)); 1237 pfc_reg_write(PFC_DRVCTRL22, reg); 1238 reg = mmio_read_32(PFC_DRVCTRL23); 1239 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7) 1240 | DRVCTRL23_SSI_WS78(7) 1241 | DRVCTRL23_SSI_SDATA7(7) 1242 | DRVCTRL23_SSI_SDATA8(7) 1243 | DRVCTRL23_SSI_SDATA9(7) 1244 | DRVCTRL23_AUDIO_CLKA(7) 1245 | DRVCTRL23_AUDIO_CLKB(7) 1246 | DRVCTRL23_USB0_PWEN(7)); 1247 pfc_reg_write(PFC_DRVCTRL23, reg); 1248 reg = mmio_read_32(PFC_DRVCTRL24); 1249 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7) 1250 | DRVCTRL24_USB1_PWEN(7) 1251 | DRVCTRL24_USB1_OVC(7) 1252 | DRVCTRL24_USB30_PWEN(7) 1253 | DRVCTRL24_USB30_OVC(7) 1254 | DRVCTRL24_USB31_PWEN(7) 1255 | DRVCTRL24_USB31_OVC(7)); 1256 pfc_reg_write(PFC_DRVCTRL24, reg); 1257 1258 /* initialize LSI pin pull-up/down control */ 1259 pfc_reg_write(PFC_PUD0, 0x00005FBFU); 1260 pfc_reg_write(PFC_PUD1, 0x00300FFEU); 1261 pfc_reg_write(PFC_PUD2, 0x330001E6U); 1262 pfc_reg_write(PFC_PUD3, 0x000002E0U); 1263 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U); 1264 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U); 1265 pfc_reg_write(PFC_PUD6, 0x00000055U); 1266 1267 /* initialize LSI pin pull-enable register */ 1268 pfc_reg_write(PFC_PUEN0, 0x00000FFFU); 1269 pfc_reg_write(PFC_PUEN1, 0x00100234U); 1270 pfc_reg_write(PFC_PUEN2, 0x000004C4U); 1271 pfc_reg_write(PFC_PUEN3, 0x00000200U); 1272 pfc_reg_write(PFC_PUEN4, 0x3E000000U); 1273 pfc_reg_write(PFC_PUEN5, 0x1F000805U); 1274 pfc_reg_write(PFC_PUEN6, 0x00000006U); 1275 1276 /* initialize positive/negative logic select */ 1277 mmio_write_32(GPIO_POSNEG0, 0x00000000U); 1278 mmio_write_32(GPIO_POSNEG1, 0x00000000U); 1279 mmio_write_32(GPIO_POSNEG2, 0x00000000U); 1280 mmio_write_32(GPIO_POSNEG3, 0x00000000U); 1281 mmio_write_32(GPIO_POSNEG4, 0x00000000U); 1282 mmio_write_32(GPIO_POSNEG5, 0x00000000U); 1283 mmio_write_32(GPIO_POSNEG6, 0x00000000U); 1284 1285 /* initialize general IO/interrupt switching */ 1286 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); 1287 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); 1288 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); 1289 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); 1290 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); 1291 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); 1292 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); 1293 1294 /* initialize general output register */ 1295 mmio_write_32(GPIO_OUTDT1, 0x00000000U); 1296 mmio_write_32(GPIO_OUTDT2, 0x00000400U); 1297 mmio_write_32(GPIO_OUTDT3, 0x0000C000U); 1298 mmio_write_32(GPIO_OUTDT5, 0x00000006U); 1299 mmio_write_32(GPIO_OUTDT6, 0x00003880U); 1300 1301 /* initialize general input/output switching */ 1302 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); 1303 mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U); 1304 mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); 1305 mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); 1306 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); 1307 #if (RCAR_GEN3_ULCB == 1) 1308 mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); 1309 #else 1310 mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); 1311 #endif 1312 mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); 1313 } 1314