1 /* 2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 #include <lib/mmio.h> 9 #include "rcar_def.h" 10 #include "../pfc_regs.h" 11 12 #define GPSR0_D15 BIT(15) 13 #define GPSR0_D14 BIT(14) 14 #define GPSR0_D13 BIT(13) 15 #define GPSR0_D12 BIT(12) 16 #define GPSR0_D11 BIT(11) 17 #define GPSR0_D10 BIT(10) 18 #define GPSR0_D9 BIT(9) 19 #define GPSR0_D8 BIT(8) 20 #define GPSR0_D7 BIT(7) 21 #define GPSR0_D6 BIT(6) 22 #define GPSR0_D5 BIT(5) 23 #define GPSR0_D4 BIT(4) 24 #define GPSR0_D3 BIT(3) 25 #define GPSR0_D2 BIT(2) 26 #define GPSR0_D1 BIT(1) 27 #define GPSR0_D0 BIT(0) 28 #define GPSR1_EX_WAIT0_A BIT(27) 29 #define GPSR1_WE1 BIT(26) 30 #define GPSR1_WE0 BIT(25) 31 #define GPSR1_RD_WR BIT(24) 32 #define GPSR1_RD BIT(23) 33 #define GPSR1_BS BIT(22) 34 #define GPSR1_CS1_A26 BIT(21) 35 #define GPSR1_CS0 BIT(20) 36 #define GPSR1_A19 BIT(19) 37 #define GPSR1_A18 BIT(18) 38 #define GPSR1_A17 BIT(17) 39 #define GPSR1_A16 BIT(16) 40 #define GPSR1_A15 BIT(15) 41 #define GPSR1_A14 BIT(14) 42 #define GPSR1_A13 BIT(13) 43 #define GPSR1_A12 BIT(12) 44 #define GPSR1_A11 BIT(11) 45 #define GPSR1_A10 BIT(10) 46 #define GPSR1_A9 BIT(9) 47 #define GPSR1_A8 BIT(8) 48 #define GPSR1_A7 BIT(7) 49 #define GPSR1_A6 BIT(6) 50 #define GPSR1_A5 BIT(5) 51 #define GPSR1_A4 BIT(4) 52 #define GPSR1_A3 BIT(3) 53 #define GPSR1_A2 BIT(2) 54 #define GPSR1_A1 BIT(1) 55 #define GPSR1_A0 BIT(0) 56 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14) 57 #define GPSR2_AVB_AVTP_MATCH_A BIT(13) 58 #define GPSR2_AVB_LINK BIT(12) 59 #define GPSR2_AVB_PHY_INT BIT(11) 60 #define GPSR2_AVB_MAGIC BIT(10) 61 #define GPSR2_AVB_MDC BIT(9) 62 #define GPSR2_PWM2_A BIT(8) 63 #define GPSR2_PWM1_A BIT(7) 64 #define GPSR2_PWM0 BIT(6) 65 #define GPSR2_IRQ5 BIT(5) 66 #define GPSR2_IRQ4 BIT(4) 67 #define GPSR2_IRQ3 BIT(3) 68 #define GPSR2_IRQ2 BIT(2) 69 #define GPSR2_IRQ1 BIT(1) 70 #define GPSR2_IRQ0 BIT(0) 71 #define GPSR3_SD1_WP BIT(15) 72 #define GPSR3_SD1_CD BIT(14) 73 #define GPSR3_SD0_WP BIT(13) 74 #define GPSR3_SD0_CD BIT(12) 75 #define GPSR3_SD1_DAT3 BIT(11) 76 #define GPSR3_SD1_DAT2 BIT(10) 77 #define GPSR3_SD1_DAT1 BIT(9) 78 #define GPSR3_SD1_DAT0 BIT(8) 79 #define GPSR3_SD1_CMD BIT(7) 80 #define GPSR3_SD1_CLK BIT(6) 81 #define GPSR3_SD0_DAT3 BIT(5) 82 #define GPSR3_SD0_DAT2 BIT(4) 83 #define GPSR3_SD0_DAT1 BIT(3) 84 #define GPSR3_SD0_DAT0 BIT(2) 85 #define GPSR3_SD0_CMD BIT(1) 86 #define GPSR3_SD0_CLK BIT(0) 87 #define GPSR4_SD3_DS BIT(17) 88 #define GPSR4_SD3_DAT7 BIT(16) 89 #define GPSR4_SD3_DAT6 BIT(15) 90 #define GPSR4_SD3_DAT5 BIT(14) 91 #define GPSR4_SD3_DAT4 BIT(13) 92 #define GPSR4_SD3_DAT3 BIT(12) 93 #define GPSR4_SD3_DAT2 BIT(11) 94 #define GPSR4_SD3_DAT1 BIT(10) 95 #define GPSR4_SD3_DAT0 BIT(9) 96 #define GPSR4_SD3_CMD BIT(8) 97 #define GPSR4_SD3_CLK BIT(7) 98 #define GPSR4_SD2_DS BIT(6) 99 #define GPSR4_SD2_DAT3 BIT(5) 100 #define GPSR4_SD2_DAT2 BIT(4) 101 #define GPSR4_SD2_DAT1 BIT(3) 102 #define GPSR4_SD2_DAT0 BIT(2) 103 #define GPSR4_SD2_CMD BIT(1) 104 #define GPSR4_SD2_CLK BIT(0) 105 #define GPSR5_MLB_DAT BIT(25) 106 #define GPSR5_MLB_SIG BIT(24) 107 #define GPSR5_MLB_CLK BIT(23) 108 #define GPSR5_MSIOF0_RXD BIT(22) 109 #define GPSR5_MSIOF0_SS2 BIT(21) 110 #define GPSR5_MSIOF0_TXD BIT(20) 111 #define GPSR5_MSIOF0_SS1 BIT(19) 112 #define GPSR5_MSIOF0_SYNC BIT(18) 113 #define GPSR5_MSIOF0_SCK BIT(17) 114 #define GPSR5_HRTS0 BIT(16) 115 #define GPSR5_HCTS0 BIT(15) 116 #define GPSR5_HTX0 BIT(14) 117 #define GPSR5_HRX0 BIT(13) 118 #define GPSR5_HSCK0 BIT(12) 119 #define GPSR5_RX2_A BIT(11) 120 #define GPSR5_TX2_A BIT(10) 121 #define GPSR5_SCK2 BIT(9) 122 #define GPSR5_RTS1 BIT(8) 123 #define GPSR5_CTS1 BIT(7) 124 #define GPSR5_TX1_A BIT(6) 125 #define GPSR5_RX1_A BIT(5) 126 #define GPSR5_RTS0 BIT(4) 127 #define GPSR5_CTS0 BIT(3) 128 #define GPSR5_TX0 BIT(2) 129 #define GPSR5_RX0 BIT(1) 130 #define GPSR5_SCK0 BIT(0) 131 #define GPSR6_USB31_OVC BIT(31) 132 #define GPSR6_USB31_PWEN BIT(30) 133 #define GPSR6_USB30_OVC BIT(29) 134 #define GPSR6_USB30_PWEN BIT(28) 135 #define GPSR6_USB1_OVC BIT(27) 136 #define GPSR6_USB1_PWEN BIT(26) 137 #define GPSR6_USB0_OVC BIT(25) 138 #define GPSR6_USB0_PWEN BIT(24) 139 #define GPSR6_AUDIO_CLKB_B BIT(23) 140 #define GPSR6_AUDIO_CLKA_A BIT(22) 141 #define GPSR6_SSI_SDATA9_A BIT(21) 142 #define GPSR6_SSI_SDATA8 BIT(20) 143 #define GPSR6_SSI_SDATA7 BIT(19) 144 #define GPSR6_SSI_WS78 BIT(18) 145 #define GPSR6_SSI_SCK78 BIT(17) 146 #define GPSR6_SSI_SDATA6 BIT(16) 147 #define GPSR6_SSI_WS6 BIT(15) 148 #define GPSR6_SSI_SCK6 BIT(14) 149 #define GPSR6_SSI_SDATA5 BIT(13) 150 #define GPSR6_SSI_WS5 BIT(12) 151 #define GPSR6_SSI_SCK5 BIT(11) 152 #define GPSR6_SSI_SDATA4 BIT(10) 153 #define GPSR6_SSI_WS4 BIT(9) 154 #define GPSR6_SSI_SCK4 BIT(8) 155 #define GPSR6_SSI_SDATA3 BIT(7) 156 #define GPSR6_SSI_WS34 BIT(6) 157 #define GPSR6_SSI_SCK34 BIT(5) 158 #define GPSR6_SSI_SDATA2_A BIT(4) 159 #define GPSR6_SSI_SDATA1_A BIT(3) 160 #define GPSR6_SSI_SDATA0 BIT(2) 161 #define GPSR6_SSI_WS0129 BIT(1) 162 #define GPSR6_SSI_SCK0129 BIT(0) 163 #define GPSR7_AVS2 BIT(1) 164 #define GPSR7_AVS1 BIT(0) 165 166 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) 167 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) 168 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) 169 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) 170 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) 171 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) 172 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) 173 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) 174 175 #define POC_SD3_DS_33V BIT(29) 176 #define POC_SD3_DAT7_33V BIT(28) 177 #define POC_SD3_DAT6_33V BIT(27) 178 #define POC_SD3_DAT5_33V BIT(26) 179 #define POC_SD3_DAT4_33V BIT(25) 180 #define POC_SD3_DAT3_33V BIT(24) 181 #define POC_SD3_DAT2_33V BIT(23) 182 #define POC_SD3_DAT1_33V BIT(22) 183 #define POC_SD3_DAT0_33V BIT(21) 184 #define POC_SD3_CMD_33V BIT(20) 185 #define POC_SD3_CLK_33V BIT(19) 186 #define POC_SD2_DS_33V BIT(18) 187 #define POC_SD2_DAT3_33V BIT(17) 188 #define POC_SD2_DAT2_33V BIT(16) 189 #define POC_SD2_DAT1_33V BIT(15) 190 #define POC_SD2_DAT0_33V BIT(14) 191 #define POC_SD2_CMD_33V BIT(13) 192 #define POC_SD2_CLK_33V BIT(12) 193 #define POC_SD1_DAT3_33V BIT(11) 194 #define POC_SD1_DAT2_33V BIT(10) 195 #define POC_SD1_DAT1_33V BIT(9) 196 #define POC_SD1_DAT0_33V BIT(8) 197 #define POC_SD1_CMD_33V BIT(7) 198 #define POC_SD1_CLK_33V BIT(6) 199 #define POC_SD0_DAT3_33V BIT(5) 200 #define POC_SD0_DAT2_33V BIT(4) 201 #define POC_SD0_DAT1_33V BIT(3) 202 #define POC_SD0_DAT0_33V BIT(2) 203 #define POC_SD0_CMD_33V BIT(1) 204 #define POC_SD0_CLK_33V BIT(0) 205 206 #define DRVCTRL0_MASK (0xCCCCCCCCU) 207 #define DRVCTRL1_MASK (0xCCCCCCC8U) 208 #define DRVCTRL2_MASK (0x88888888U) 209 #define DRVCTRL3_MASK (0x88888888U) 210 #define DRVCTRL4_MASK (0x88888888U) 211 #define DRVCTRL5_MASK (0x88888888U) 212 #define DRVCTRL6_MASK (0x88888888U) 213 #define DRVCTRL7_MASK (0x88888888U) 214 #define DRVCTRL8_MASK (0x88888888U) 215 #define DRVCTRL9_MASK (0x88888888U) 216 #define DRVCTRL10_MASK (0x88888888U) 217 #define DRVCTRL11_MASK (0x888888CCU) 218 #define DRVCTRL12_MASK (0xCCCFFFCFU) 219 #define DRVCTRL13_MASK (0xCC888888U) 220 #define DRVCTRL14_MASK (0x88888888U) 221 #define DRVCTRL15_MASK (0x88888888U) 222 #define DRVCTRL16_MASK (0x88888888U) 223 #define DRVCTRL17_MASK (0x88888888U) 224 #define DRVCTRL18_MASK (0x88888888U) 225 #define DRVCTRL19_MASK (0x88888888U) 226 #define DRVCTRL20_MASK (0x88888888U) 227 #define DRVCTRL21_MASK (0x88888888U) 228 #define DRVCTRL22_MASK (0x88888888U) 229 #define DRVCTRL23_MASK (0x88888888U) 230 #define DRVCTRL24_MASK (0x8888888FU) 231 232 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) 233 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) 234 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) 235 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) 236 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) 237 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) 238 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) 239 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) 240 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) 241 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) 242 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) 243 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) 244 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) 245 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) 246 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) 247 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) 248 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) 249 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) 250 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) 251 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) 252 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) 253 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) 254 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) 255 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) 256 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) 257 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) 258 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) 259 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) 260 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) 261 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) 262 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) 263 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) 264 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) 265 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) 266 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) 267 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) 268 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) 269 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) 270 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) 271 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) 272 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) 273 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) 274 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) 275 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) 276 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) 277 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) 278 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) 279 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) 280 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) 281 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) 282 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) 283 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) 284 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) 285 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) 286 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) 287 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) 288 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) 289 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) 290 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) 291 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) 292 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) 293 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) 294 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) 295 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) 296 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) 297 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) 298 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) 299 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) 300 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) 301 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) 302 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) 303 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) 304 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) 305 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) 306 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) 307 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) 308 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) 309 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) 310 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) 311 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) 312 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) 313 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) 314 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) 315 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) 316 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) 317 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) 318 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) 319 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) 320 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) 321 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) 322 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) 323 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) 324 #define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U) 325 #define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U) 326 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) 327 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) 328 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) 329 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) 330 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) 331 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) 332 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) 333 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) 334 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) 335 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) 336 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) 337 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) 338 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) 339 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) 340 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) 341 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) 342 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) 343 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) 344 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) 345 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) 346 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) 347 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) 348 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) 349 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) 350 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) 351 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) 352 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) 353 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) 354 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) 355 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) 356 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) 357 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) 358 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) 359 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) 360 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) 361 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) 362 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) 363 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) 364 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) 365 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) 366 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) 367 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) 368 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) 369 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) 370 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) 371 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) 372 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) 373 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) 374 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) 375 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) 376 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) 377 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) 378 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) 379 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) 380 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) 381 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) 382 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) 383 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) 384 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) 385 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) 386 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) 387 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) 388 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) 389 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) 390 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) 391 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) 392 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) 393 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) 394 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) 395 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) 396 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) 397 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) 398 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) 399 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) 400 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) 401 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) 402 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) 403 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) 404 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) 405 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) 406 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) 407 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) 408 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) 409 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) 410 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) 411 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) 412 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) 413 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) 414 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) 415 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) 416 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) 417 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) 418 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) 419 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) 420 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) 421 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) 422 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) 423 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) 424 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) 425 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) 426 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) 427 428 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) 429 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) 430 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) 431 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) 432 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) 433 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) 434 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) 435 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) 436 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) 437 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) 438 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) 439 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) 440 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) 441 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) 442 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) 443 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) 444 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) 445 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) 446 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) 447 #define MOD_SEL0_I2C6_A ((uint32_t)0U << 20U) 448 #define MOD_SEL0_I2C6_B ((uint32_t)1U << 20U) 449 #define MOD_SEL0_I2C6_C ((uint32_t)2U << 20U) 450 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 19U) 451 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 19U) 452 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 18U) 453 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 18U) 454 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 17U) 455 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 17U) 456 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 15U) 457 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 15U) 458 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 15U) 459 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 15U) 460 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 14U) 461 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 14U) 462 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 13U) 463 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 13U) 464 #define MOD_SEL0_FSO_A ((uint32_t)0U << 12U) 465 #define MOD_SEL0_FSO_B ((uint32_t)1U << 12U) 466 #define MOD_SEL0_FM_A ((uint32_t)0U << 11U) 467 #define MOD_SEL0_FM_B ((uint32_t)1U << 11U) 468 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 10U) 469 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 10U) 470 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 9U) 471 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 9U) 472 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 8U) 473 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 8U) 474 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 6U) 475 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 6U) 476 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 6U) 477 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 4U) 478 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 4U) 479 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 4U) 480 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 3U) 481 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 3U) 482 #define MOD_SEL0_ADG_A ((uint32_t)0U << 1U) 483 #define MOD_SEL0_ADG_B ((uint32_t)1U << 1U) 484 #define MOD_SEL0_ADG_C ((uint32_t)2U << 1U) 485 #define MOD_SEL0_ADG_D ((uint32_t)3U << 1U) 486 #define MOD_SEL0_5LINE_A ((uint32_t)0U << 0U) 487 #define MOD_SEL0_5LINE_B ((uint32_t)1U << 0U) 488 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) 489 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) 490 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) 491 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) 492 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) 493 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) 494 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) 495 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) 496 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) 497 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) 498 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) 499 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) 500 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) 501 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) 502 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) 503 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) 504 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) 505 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) 506 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) 507 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) 508 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) 509 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) 510 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) 511 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) 512 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) 513 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) 514 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) 515 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) 516 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) 517 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) 518 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) 519 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) 520 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) 521 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) 522 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) 523 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) 524 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) 525 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) 526 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) 527 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) 528 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) 529 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) 530 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) 531 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) 532 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) 533 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) 534 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) 535 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) 536 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) 537 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) 538 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) 539 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) 540 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) 541 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) 542 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) 543 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) 544 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) 545 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) 546 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) 547 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) 548 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) 549 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) 550 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) 551 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) 552 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) 553 554 static void pfc_reg_write(uint32_t addr, uint32_t data) 555 { 556 mmio_write_32(PFC_PMMR, ~data); 557 mmio_write_32((uintptr_t)addr, data); 558 } 559 560 void pfc_init_h3_v1(void) 561 { 562 uint32_t reg; 563 564 /* initialize module select */ 565 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A 566 | MOD_SEL0_MSIOF2_A 567 | MOD_SEL0_MSIOF1_A 568 | MOD_SEL0_LBSC_A 569 | MOD_SEL0_IEBUS_A 570 | MOD_SEL0_I2C6_A 571 | MOD_SEL0_I2C2_A 572 | MOD_SEL0_I2C1_A 573 | MOD_SEL0_HSCIF4_A 574 | MOD_SEL0_HSCIF3_A 575 | MOD_SEL0_HSCIF2_A 576 | MOD_SEL0_HSCIF1_A 577 | MOD_SEL0_FM_A 578 | MOD_SEL0_ETHERAVB_A 579 | MOD_SEL0_DRIF3_A 580 | MOD_SEL0_DRIF2_A 581 | MOD_SEL0_DRIF1_A 582 | MOD_SEL0_DRIF0_A 583 | MOD_SEL0_CANFD0_A 584 | MOD_SEL0_ADG_A 585 | MOD_SEL0_5LINE_A); 586 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A 587 | MOD_SEL1_TSIF0_A 588 | MOD_SEL1_TIMER_TMU_A 589 | MOD_SEL1_SSP1_1_A 590 | MOD_SEL1_SSP1_0_A 591 | MOD_SEL1_SSI_A 592 | MOD_SEL1_SPEED_PULSE_IF_A 593 | MOD_SEL1_SIMCARD_A 594 | MOD_SEL1_SDHI2_A 595 | MOD_SEL1_SCIF4_A 596 | MOD_SEL1_SCIF3_A 597 | MOD_SEL1_SCIF2_A 598 | MOD_SEL1_SCIF1_A 599 | MOD_SEL1_SCIF_A 600 | MOD_SEL1_REMOCON_A 601 | MOD_SEL1_RCAN0_A 602 | MOD_SEL1_PWM6_A 603 | MOD_SEL1_PWM5_A 604 | MOD_SEL1_PWM4_A 605 | MOD_SEL1_PWM3_A 606 | MOD_SEL1_PWM2_A 607 | MOD_SEL1_PWM1_A); 608 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A 609 | MOD_SEL2_I2C_3_A 610 | MOD_SEL2_I2C_0_A 611 | MOD_SEL2_VIN4_A); 612 613 /* initialize peripheral function select */ 614 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) 615 | IPSR_24_FUNC(0) 616 | IPSR_20_FUNC(0) 617 | IPSR_16_FUNC(0) 618 | IPSR_12_FUNC(0) 619 | IPSR_8_FUNC(0) 620 | IPSR_4_FUNC(0) 621 | IPSR_0_FUNC(0)); 622 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6) 623 | IPSR_24_FUNC(0) 624 | IPSR_20_FUNC(0) 625 | IPSR_16_FUNC(0) 626 | IPSR_12_FUNC(3) 627 | IPSR_8_FUNC(3) 628 | IPSR_4_FUNC(3) 629 | IPSR_0_FUNC(3)); 630 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) 631 | IPSR_24_FUNC(6) 632 | IPSR_20_FUNC(6) 633 | IPSR_16_FUNC(6) 634 | IPSR_12_FUNC(6) 635 | IPSR_8_FUNC(6) 636 | IPSR_4_FUNC(6) 637 | IPSR_0_FUNC(6)); 638 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6) 639 | IPSR_24_FUNC(6) 640 | IPSR_20_FUNC(6) 641 | IPSR_16_FUNC(6) 642 | IPSR_12_FUNC(6) 643 | IPSR_8_FUNC(0) 644 | IPSR_4_FUNC(0) 645 | IPSR_0_FUNC(0)); 646 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) 647 | IPSR_24_FUNC(0) 648 | IPSR_20_FUNC(0) 649 | IPSR_16_FUNC(0) 650 | IPSR_12_FUNC(0) 651 | IPSR_8_FUNC(6) 652 | IPSR_4_FUNC(6) 653 | IPSR_0_FUNC(6)); 654 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) 655 | IPSR_24_FUNC(0) 656 | IPSR_20_FUNC(0) 657 | IPSR_16_FUNC(0) 658 | IPSR_12_FUNC(0) 659 | IPSR_8_FUNC(6) 660 | IPSR_4_FUNC(0) 661 | IPSR_0_FUNC(0)); 662 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6) 663 | IPSR_24_FUNC(6) 664 | IPSR_20_FUNC(6) 665 | IPSR_16_FUNC(6) 666 | IPSR_12_FUNC(6) 667 | IPSR_8_FUNC(0) 668 | IPSR_4_FUNC(0) 669 | IPSR_0_FUNC(0)); 670 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) 671 | IPSR_24_FUNC(0) 672 | IPSR_20_FUNC(0) 673 | IPSR_16_FUNC(0) 674 | IPSR_8_FUNC(6) 675 | IPSR_4_FUNC(6) 676 | IPSR_0_FUNC(6)); 677 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1) 678 | IPSR_24_FUNC(1) 679 | IPSR_20_FUNC(1) 680 | IPSR_16_FUNC(1) 681 | IPSR_12_FUNC(0) 682 | IPSR_8_FUNC(0) 683 | IPSR_4_FUNC(0) 684 | IPSR_0_FUNC(0)); 685 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) 686 | IPSR_24_FUNC(0) 687 | IPSR_20_FUNC(0) 688 | IPSR_16_FUNC(0) 689 | IPSR_12_FUNC(0) 690 | IPSR_8_FUNC(0) 691 | IPSR_4_FUNC(0) 692 | IPSR_0_FUNC(0)); 693 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) 694 | IPSR_24_FUNC(4) 695 | IPSR_20_FUNC(0) 696 | IPSR_16_FUNC(0) 697 | IPSR_12_FUNC(0) 698 | IPSR_8_FUNC(0) 699 | IPSR_4_FUNC(1) 700 | IPSR_0_FUNC(1)); 701 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0) 702 | IPSR_24_FUNC(0) 703 | IPSR_20_FUNC(0) 704 | IPSR_16_FUNC(0) 705 | IPSR_12_FUNC(0) 706 | IPSR_8_FUNC(4) 707 | IPSR_4_FUNC(0) 708 | IPSR_0_FUNC(0)); 709 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8) 710 | IPSR_24_FUNC(0) 711 | IPSR_20_FUNC(0) 712 | IPSR_16_FUNC(0) 713 | IPSR_12_FUNC(0) 714 | IPSR_8_FUNC(3) 715 | IPSR_4_FUNC(0) 716 | IPSR_0_FUNC(0)); 717 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0) 718 | IPSR_24_FUNC(0) 719 | IPSR_20_FUNC(0) 720 | IPSR_16_FUNC(0) 721 | IPSR_12_FUNC(0) 722 | IPSR_8_FUNC(0) 723 | IPSR_4_FUNC(3) 724 | IPSR_0_FUNC(8)); 725 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0) 726 | IPSR_24_FUNC(0) 727 | IPSR_20_FUNC(0) 728 | IPSR_16_FUNC(0) 729 | IPSR_12_FUNC(0) 730 | IPSR_8_FUNC(0) 731 | IPSR_4_FUNC(0) 732 | IPSR_0_FUNC(0)); 733 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) 734 | IPSR_24_FUNC(0) 735 | IPSR_20_FUNC(0) 736 | IPSR_16_FUNC(0) 737 | IPSR_12_FUNC(0) 738 | IPSR_8_FUNC(0) 739 | IPSR_4_FUNC(1) 740 | IPSR_0_FUNC(1)); 741 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0) 742 | IPSR_24_FUNC(0) 743 | IPSR_20_FUNC(0) 744 | IPSR_16_FUNC(0) 745 | IPSR_12_FUNC(0) 746 | IPSR_8_FUNC(0) 747 | IPSR_4_FUNC(1) 748 | IPSR_0_FUNC(0)); 749 pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0) 750 | IPSR_0_FUNC(0)); 751 752 /* initialize GPIO/perihperal function select */ 753 pfc_reg_write(PFC_GPSR0, GPSR0_D15 754 | GPSR0_D14 755 | GPSR0_D13 756 | GPSR0_D12 757 | GPSR0_D11 758 | GPSR0_D10 759 | GPSR0_D9 760 | GPSR0_D8); 761 pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A 762 | GPSR1_A19 763 | GPSR1_A18 764 | GPSR1_A17 765 | GPSR1_A16 766 | GPSR1_A15 767 | GPSR1_A14 768 | GPSR1_A13 769 | GPSR1_A12 770 | GPSR1_A7 771 | GPSR1_A6 772 | GPSR1_A5 773 | GPSR1_A4 774 | GPSR1_A3 775 | GPSR1_A2 776 | GPSR1_A1 777 | GPSR1_A0); 778 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A 779 | GPSR2_AVB_AVTP_MATCH_A 780 | GPSR2_AVB_LINK 781 | GPSR2_AVB_PHY_INT 782 | GPSR2_AVB_MDC 783 | GPSR2_PWM2_A 784 | GPSR2_PWM1_A 785 | GPSR2_IRQ5 786 | GPSR2_IRQ4 787 | GPSR2_IRQ3 788 | GPSR2_IRQ2 789 | GPSR2_IRQ1 790 | GPSR2_IRQ0); 791 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP 792 | GPSR3_SD0_CD 793 | GPSR3_SD1_DAT3 794 | GPSR3_SD1_DAT2 795 | GPSR3_SD1_DAT1 796 | GPSR3_SD1_DAT0 797 | GPSR3_SD0_DAT3 798 | GPSR3_SD0_DAT2 799 | GPSR3_SD0_DAT1 800 | GPSR3_SD0_DAT0 801 | GPSR3_SD0_CMD 802 | GPSR3_SD0_CLK); 803 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7 804 | GPSR4_SD3_DAT6 805 | GPSR4_SD3_DAT3 806 | GPSR4_SD3_DAT2 807 | GPSR4_SD3_DAT1 808 | GPSR4_SD3_DAT0 809 | GPSR4_SD3_CMD 810 | GPSR4_SD3_CLK 811 | GPSR4_SD2_DS 812 | GPSR4_SD2_DAT3 813 | GPSR4_SD2_DAT2 814 | GPSR4_SD2_DAT1 815 | GPSR4_SD2_DAT0 816 | GPSR4_SD2_CMD 817 | GPSR4_SD2_CLK); 818 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2 819 | GPSR5_MSIOF0_SS1 820 | GPSR5_MSIOF0_SYNC 821 | GPSR5_HRTS0 822 | GPSR5_HCTS0 823 | GPSR5_HTX0 824 | GPSR5_HRX0 825 | GPSR5_HSCK0 826 | GPSR5_RX2_A 827 | GPSR5_TX2_A 828 | GPSR5_SCK2 829 | GPSR5_RTS1 830 | GPSR5_CTS1 831 | GPSR5_TX1_A 832 | GPSR5_RX1_A 833 | GPSR5_RTS0 834 | GPSR5_SCK0); 835 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC 836 | GPSR6_USB30_PWEN 837 | GPSR6_USB1_OVC 838 | GPSR6_USB1_PWEN 839 | GPSR6_USB0_OVC 840 | GPSR6_USB0_PWEN 841 | GPSR6_AUDIO_CLKB_B 842 | GPSR6_AUDIO_CLKA_A 843 | GPSR6_SSI_SDATA8 844 | GPSR6_SSI_SDATA7 845 | GPSR6_SSI_WS78 846 | GPSR6_SSI_SCK78 847 | GPSR6_SSI_WS6 848 | GPSR6_SSI_SCK6 849 | GPSR6_SSI_SDATA4 850 | GPSR6_SSI_WS4 851 | GPSR6_SSI_SCK4 852 | GPSR6_SSI_SDATA1_A 853 | GPSR6_SSI_SDATA0 854 | GPSR6_SSI_WS0129 855 | GPSR6_SSI_SCK0129); 856 pfc_reg_write(PFC_GPSR7, GPSR7_AVS2 857 | GPSR7_AVS1); 858 859 /* initialize POC control register */ 860 pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V 861 | POC_SD3_DAT7_33V 862 | POC_SD3_DAT6_33V 863 | POC_SD3_DAT5_33V 864 | POC_SD3_DAT4_33V 865 | POC_SD3_DAT3_33V 866 | POC_SD3_DAT2_33V 867 | POC_SD3_DAT1_33V 868 | POC_SD3_DAT0_33V 869 | POC_SD3_CMD_33V 870 | POC_SD3_CLK_33V 871 | POC_SD0_DAT3_33V 872 | POC_SD0_DAT2_33V 873 | POC_SD0_DAT1_33V 874 | POC_SD0_DAT0_33V 875 | POC_SD0_CMD_33V 876 | POC_SD0_CLK_33V); 877 878 /* initialize DRV control register */ 879 reg = mmio_read_32(PFC_DRVCTRL0); 880 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) 881 | DRVCTRL0_QSPI0_MOSI_IO0(3) 882 | DRVCTRL0_QSPI0_MISO_IO1(3) 883 | DRVCTRL0_QSPI0_IO2(3) 884 | DRVCTRL0_QSPI0_IO3(3) 885 | DRVCTRL0_QSPI0_SSL(3) 886 | DRVCTRL0_QSPI1_SPCLK(3) 887 | DRVCTRL0_QSPI1_MOSI_IO0(3)); 888 pfc_reg_write(PFC_DRVCTRL0, reg); 889 reg = mmio_read_32(PFC_DRVCTRL1); 890 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) 891 | DRVCTRL1_QSPI1_IO2(3) 892 | DRVCTRL1_QSPI1_IO3(3) 893 | DRVCTRL1_QSPI1_SS(3) 894 | DRVCTRL1_RPC_INT(3) 895 | DRVCTRL1_RPC_WP(3) 896 | DRVCTRL1_RPC_RESET(3) 897 | DRVCTRL1_AVB_RX_CTL(7)); 898 pfc_reg_write(PFC_DRVCTRL1, reg); 899 reg = mmio_read_32(PFC_DRVCTRL2); 900 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) 901 | DRVCTRL2_AVB_RD0(7) 902 | DRVCTRL2_AVB_RD1(7) 903 | DRVCTRL2_AVB_RD2(7) 904 | DRVCTRL2_AVB_RD3(7) 905 | DRVCTRL2_AVB_TX_CTL(3) 906 | DRVCTRL2_AVB_TXC(3) 907 | DRVCTRL2_AVB_TD0(3)); 908 pfc_reg_write(PFC_DRVCTRL2, reg); 909 reg = mmio_read_32(PFC_DRVCTRL3); 910 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3) 911 | DRVCTRL3_AVB_TD2(3) 912 | DRVCTRL3_AVB_TD3(3) 913 | DRVCTRL3_AVB_TXCREFCLK(7) 914 | DRVCTRL3_AVB_MDIO(7) 915 | DRVCTRL3_AVB_MDC(7) 916 | DRVCTRL3_AVB_MAGIC(7) 917 | DRVCTRL3_AVB_PHY_INT(7)); 918 pfc_reg_write(PFC_DRVCTRL3, reg); 919 reg = mmio_read_32(PFC_DRVCTRL4); 920 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) 921 | DRVCTRL4_AVB_AVTP_MATCH(7) 922 | DRVCTRL4_AVB_AVTP_CAPTURE(7) 923 | DRVCTRL4_IRQ0(7) 924 | DRVCTRL4_IRQ1(7) 925 | DRVCTRL4_IRQ2(7) 926 | DRVCTRL4_IRQ3(7) 927 | DRVCTRL4_IRQ4(7)); 928 pfc_reg_write(PFC_DRVCTRL4, reg); 929 reg = mmio_read_32(PFC_DRVCTRL5); 930 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) 931 | DRVCTRL5_PWM0(7) 932 | DRVCTRL5_PWM1(7) 933 | DRVCTRL5_PWM2(7) 934 | DRVCTRL5_A0(3) 935 | DRVCTRL5_A1(3) 936 | DRVCTRL5_A2(3) 937 | DRVCTRL5_A3(3)); 938 pfc_reg_write(PFC_DRVCTRL5, reg); 939 reg = mmio_read_32(PFC_DRVCTRL6); 940 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3) 941 | DRVCTRL6_A5(3) 942 | DRVCTRL6_A6(3) 943 | DRVCTRL6_A7(3) 944 | DRVCTRL6_A8(7) 945 | DRVCTRL6_A9(7) 946 | DRVCTRL6_A10(7) 947 | DRVCTRL6_A11(7)); 948 pfc_reg_write(PFC_DRVCTRL6, reg); 949 reg = mmio_read_32(PFC_DRVCTRL7); 950 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3) 951 | DRVCTRL7_A13(3) 952 | DRVCTRL7_A14(3) 953 | DRVCTRL7_A15(3) 954 | DRVCTRL7_A16(3) 955 | DRVCTRL7_A17(3) 956 | DRVCTRL7_A18(3) 957 | DRVCTRL7_A19(3)); 958 pfc_reg_write(PFC_DRVCTRL7, reg); 959 reg = mmio_read_32(PFC_DRVCTRL8); 960 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) 961 | DRVCTRL8_CS0(7) 962 | DRVCTRL8_CS1_A2(7) 963 | DRVCTRL8_BS(7) 964 | DRVCTRL8_RD(7) 965 | DRVCTRL8_RD_W(7) 966 | DRVCTRL8_WE0(7) 967 | DRVCTRL8_WE1(7)); 968 pfc_reg_write(PFC_DRVCTRL8, reg); 969 reg = mmio_read_32(PFC_DRVCTRL9); 970 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7) 971 | DRVCTRL9_PRESETOU(7) 972 | DRVCTRL9_D0(7) 973 | DRVCTRL9_D1(7) 974 | DRVCTRL9_D2(7) 975 | DRVCTRL9_D3(7) 976 | DRVCTRL9_D4(7) 977 | DRVCTRL9_D5(7)); 978 pfc_reg_write(PFC_DRVCTRL9, reg); 979 reg = mmio_read_32(PFC_DRVCTRL10); 980 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) 981 | DRVCTRL10_D7(7) 982 | DRVCTRL10_D8(3) 983 | DRVCTRL10_D9(3) 984 | DRVCTRL10_D10(3) 985 | DRVCTRL10_D11(3) 986 | DRVCTRL10_D12(3) 987 | DRVCTRL10_D13(3)); 988 pfc_reg_write(PFC_DRVCTRL10, reg); 989 reg = mmio_read_32(PFC_DRVCTRL11); 990 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3) 991 | DRVCTRL11_D15(3) 992 | DRVCTRL11_AVS1(7) 993 | DRVCTRL11_AVS2(7) 994 | DRVCTRL11_GP7_02(7) 995 | DRVCTRL11_GP7_03(7) 996 | DRVCTRL11_DU_DOTCLKIN0(3) 997 | DRVCTRL11_DU_DOTCLKIN1(3)); 998 pfc_reg_write(PFC_DRVCTRL11, reg); 999 reg = mmio_read_32(PFC_DRVCTRL12); 1000 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3) 1001 | DRVCTRL12_DU_DOTCLKIN3(3) 1002 | DRVCTRL12_DU_FSCLKST(3) 1003 | DRVCTRL12_DU_TMS(3)); 1004 pfc_reg_write(PFC_DRVCTRL12, reg); 1005 reg = mmio_read_32(PFC_DRVCTRL13); 1006 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) 1007 | DRVCTRL13_ASEBRK(3) 1008 | DRVCTRL13_SD0_CLK(2) 1009 | DRVCTRL13_SD0_CMD(2) 1010 | DRVCTRL13_SD0_DAT0(2) 1011 | DRVCTRL13_SD0_DAT1(2) 1012 | DRVCTRL13_SD0_DAT2(2) 1013 | DRVCTRL13_SD0_DAT3(2)); 1014 pfc_reg_write(PFC_DRVCTRL13, reg); 1015 reg = mmio_read_32(PFC_DRVCTRL14); 1016 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7) 1017 | DRVCTRL14_SD1_CMD(7) 1018 | DRVCTRL14_SD1_DAT0(5) 1019 | DRVCTRL14_SD1_DAT1(5) 1020 | DRVCTRL14_SD1_DAT2(5) 1021 | DRVCTRL14_SD1_DAT3(5) 1022 | DRVCTRL14_SD2_CLK(5) 1023 | DRVCTRL14_SD2_CMD(5)); 1024 pfc_reg_write(PFC_DRVCTRL14, reg); 1025 reg = mmio_read_32(PFC_DRVCTRL15); 1026 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5) 1027 | DRVCTRL15_SD2_DAT1(5) 1028 | DRVCTRL15_SD2_DAT2(5) 1029 | DRVCTRL15_SD2_DAT3(5) 1030 | DRVCTRL15_SD2_DS(5) 1031 | DRVCTRL15_SD3_CLK(2) 1032 | DRVCTRL15_SD3_CMD(2) 1033 | DRVCTRL15_SD3_DAT0(2)); 1034 pfc_reg_write(PFC_DRVCTRL15, reg); 1035 reg = mmio_read_32(PFC_DRVCTRL16); 1036 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(2) 1037 | DRVCTRL16_SD3_DAT2(2) 1038 | DRVCTRL16_SD3_DAT3(2) 1039 | DRVCTRL16_SD3_DAT4(7) 1040 | DRVCTRL16_SD3_DAT5(7) 1041 | DRVCTRL16_SD3_DAT6(7) 1042 | DRVCTRL16_SD3_DAT7(7) 1043 | DRVCTRL16_SD3_DS(7)); 1044 pfc_reg_write(PFC_DRVCTRL16, reg); 1045 reg = mmio_read_32(PFC_DRVCTRL17); 1046 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7) 1047 | DRVCTRL17_SD0_WP(7) 1048 | DRVCTRL17_SD1_CD(7) 1049 | DRVCTRL17_SD1_WP(7) 1050 | DRVCTRL17_SCK0(7) 1051 | DRVCTRL17_RX0(7) 1052 | DRVCTRL17_TX0(7) 1053 | DRVCTRL17_CTS0(7)); 1054 pfc_reg_write(PFC_DRVCTRL17, reg); 1055 reg = mmio_read_32(PFC_DRVCTRL18); 1056 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7) 1057 | DRVCTRL18_RX1(7) 1058 | DRVCTRL18_TX1(7) 1059 | DRVCTRL18_CTS1(7) 1060 | DRVCTRL18_RTS1_TANS(7) 1061 | DRVCTRL18_SCK2(7) 1062 | DRVCTRL18_TX2(7) 1063 | DRVCTRL18_RX2(7)); 1064 pfc_reg_write(PFC_DRVCTRL18, reg); 1065 reg = mmio_read_32(PFC_DRVCTRL19); 1066 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7) 1067 | DRVCTRL19_HRX0(7) 1068 | DRVCTRL19_HTX0(7) 1069 | DRVCTRL19_HCTS0(7) 1070 | DRVCTRL19_HRTS0(7) 1071 | DRVCTRL19_MSIOF0_SCK(7) 1072 | DRVCTRL19_MSIOF0_SYNC(7) 1073 | DRVCTRL19_MSIOF0_SS1(7)); 1074 pfc_reg_write(PFC_DRVCTRL19, reg); 1075 reg = mmio_read_32(PFC_DRVCTRL20); 1076 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7) 1077 | DRVCTRL20_MSIOF0_SS2(7) 1078 | DRVCTRL20_MSIOF0_RXD(7) 1079 | DRVCTRL20_MLB_CLK(7) 1080 | DRVCTRL20_MLB_SIG(7) 1081 | DRVCTRL20_MLB_DAT(7) 1082 | DRVCTRL20_MLB_REF(7) 1083 | DRVCTRL20_SSI_SCK0129(7)); 1084 pfc_reg_write(PFC_DRVCTRL20, reg); 1085 reg = mmio_read_32(PFC_DRVCTRL21); 1086 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7) 1087 | DRVCTRL21_SSI_SDATA0(7) 1088 | DRVCTRL21_SSI_SDATA1(7) 1089 | DRVCTRL21_SSI_SDATA2(7) 1090 | DRVCTRL21_SSI_SCK34(7) 1091 | DRVCTRL21_SSI_WS34(7) 1092 | DRVCTRL21_SSI_SDATA3(7) 1093 | DRVCTRL21_SSI_SCK4(7)); 1094 pfc_reg_write(PFC_DRVCTRL21, reg); 1095 reg = mmio_read_32(PFC_DRVCTRL22); 1096 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7) 1097 | DRVCTRL22_SSI_SDATA4(7) 1098 | DRVCTRL22_SSI_SCK5(7) 1099 | DRVCTRL22_SSI_WS5(7) 1100 | DRVCTRL22_SSI_SDATA5(7) 1101 | DRVCTRL22_SSI_SCK6(7) 1102 | DRVCTRL22_SSI_WS6(7) 1103 | DRVCTRL22_SSI_SDATA6(7)); 1104 pfc_reg_write(PFC_DRVCTRL22, reg); 1105 reg = mmio_read_32(PFC_DRVCTRL23); 1106 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7) 1107 | DRVCTRL23_SSI_WS78(7) 1108 | DRVCTRL23_SSI_SDATA7(7) 1109 | DRVCTRL23_SSI_SDATA8(7) 1110 | DRVCTRL23_SSI_SDATA9(7) 1111 | DRVCTRL23_AUDIO_CLKA(7) 1112 | DRVCTRL23_AUDIO_CLKB(7) 1113 | DRVCTRL23_USB0_PWEN(7)); 1114 pfc_reg_write(PFC_DRVCTRL23, reg); 1115 reg = mmio_read_32(PFC_DRVCTRL24); 1116 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7) 1117 | DRVCTRL24_USB1_PWEN(7) 1118 | DRVCTRL24_USB1_OVC(7) 1119 | DRVCTRL24_USB30_PWEN(7) 1120 | DRVCTRL24_USB30_OVC(7) 1121 | DRVCTRL24_USB31_PWEN(7) 1122 | DRVCTRL24_USB31_OVC(7)); 1123 pfc_reg_write(PFC_DRVCTRL24, reg); 1124 1125 /* initialize LSI pin pull-up/down control */ 1126 pfc_reg_write(PFC_PUD0, 0x00005FBFU); 1127 pfc_reg_write(PFC_PUD1, 0x00300FFEU); 1128 pfc_reg_write(PFC_PUD2, 0x330001E6U); 1129 pfc_reg_write(PFC_PUD3, 0x000002E0U); 1130 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U); 1131 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U); 1132 pfc_reg_write(PFC_PUD6, 0x00000055U); 1133 1134 /* initialize LSI pin pull-enable register */ 1135 pfc_reg_write(PFC_PUEN0, 0x00000FFFU); 1136 pfc_reg_write(PFC_PUEN1, 0x00100234U); 1137 pfc_reg_write(PFC_PUEN2, 0x000004C4U); 1138 pfc_reg_write(PFC_PUEN3, 0x00000200U); 1139 pfc_reg_write(PFC_PUEN4, 0x3E000000U); 1140 pfc_reg_write(PFC_PUEN5, 0x1F000805U); 1141 pfc_reg_write(PFC_PUEN6, 0x00000006U); 1142 1143 /* initialize positive/negative logic select */ 1144 mmio_write_32(GPIO_POSNEG0, 0x00000000U); 1145 mmio_write_32(GPIO_POSNEG1, 0x00000000U); 1146 mmio_write_32(GPIO_POSNEG2, 0x00000000U); 1147 mmio_write_32(GPIO_POSNEG3, 0x00000000U); 1148 mmio_write_32(GPIO_POSNEG4, 0x00000000U); 1149 mmio_write_32(GPIO_POSNEG5, 0x00000000U); 1150 mmio_write_32(GPIO_POSNEG6, 0x00000000U); 1151 mmio_write_32(GPIO_POSNEG7, 0x00000000U); 1152 1153 /* initialize general IO/interrupt switching */ 1154 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); 1155 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); 1156 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); 1157 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); 1158 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); 1159 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); 1160 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); 1161 mmio_write_32(GPIO_IOINTSEL7, 0x00000000U); 1162 1163 /* initialize general output register */ 1164 mmio_write_32(GPIO_OUTDT1, 0x00000000U); 1165 mmio_write_32(GPIO_OUTDT2, 0x00000400U); 1166 mmio_write_32(GPIO_OUTDT3, 0x0000C000U); 1167 mmio_write_32(GPIO_OUTDT5, 0x00000006U); 1168 mmio_write_32(GPIO_OUTDT6, 0x00003880U); 1169 1170 /* initialize general input/output switching */ 1171 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); 1172 mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U); 1173 mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); 1174 mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); 1175 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); 1176 #if (RCAR_GEN3_ULCB == 1) 1177 mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); 1178 #else 1179 mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); 1180 #endif 1181 mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); 1182 mmio_write_32(GPIO_INOUTSEL7, 0x00000000U); 1183 } 1184