1 /* 2 * Copyright (c) 2026, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stddef.h> 8 #include <stdint.h> 9 10 #include <drivers/console.h> 11 #include <lib/mmio.h> 12 #include <lib/utils_def.h> 13 #include "scif.h" 14 15 #include "cpg_registers.h" 16 #include "rcar_def.h" 17 #include "rcar_private.h" 18 19 /* CPG */ 20 #define CPG_MSTPSR2_SCIF0 BIT(7) 21 #define CPG_MSTPSR3_SCIF2 BIT(10) 22 23 /* SCIF */ 24 #define SCIF0_BASE 0xE6E60000UL 25 #define SCIF2_BASE 0xE6E88000UL 26 27 /* SCIF */ 28 #define SCIF_SCSMR 0x00 29 #define SCIF_SCBRR 0x04 30 #define SCIF_SCSCR 0x08 31 #define SCIF_SCFTDR 0x0C 32 #define SCIF_SCFSR 0x10 33 #define SCIF_SCFCR 0x18 34 #define SCIF_SCLSR 0x24 35 #define SCIF_DL 0x30 36 #define SCIF_CKS 0x34 37 38 /* MODE pin */ 39 #define MODEMR_MD12 BIT(12) 40 41 #define SCBRR_115200BPS 17 42 #define SCBRR_115200BPS_D3_SSCG 16 43 #define SCBRR_115200BPS_E3_SSCG 15 44 #define SCBRR_230400BPS 8 45 46 #define SCSCR_TE_EN BIT(5) 47 #define SCSCR_RE_EN BIT(4) 48 #define SCSCR_CKE_MASK 3 49 #define SCFSR_TEND_MASK BIT(6) 50 #define SCFSR_TEND_TRANS_END BIT(6) 51 #define SCSCR_CKE_INT_CLK 0 52 #define SCFCR_TFRST_EN BIT(2) 53 #define SCFCR_RFRS_EN BIT(1) 54 55 int console_renesas_init(uintptr_t base_addr, uint32_t uart_clk, 56 uint32_t baud_rate) 57 { 58 uint32_t prr = mmio_read_32(PRR); 59 uint32_t base; 60 int i; 61 62 if ((prr & PRR_PRODUCT_MASK) == PRR_PRODUCT_V3M) { /* V3M */ 63 base = SCIF0_BASE; 64 /* Enable SCIF clock */ 65 mstpcr_write(CPG_SMSTPCR2, CPG_MSTPSR2, CPG_MSTPSR2_SCIF0); 66 } else { 67 base = SCIF2_BASE; 68 /* Enable SCIF clock */ 69 mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTPSR3_SCIF2); 70 } 71 72 scif_console_set_regs(base + SCIF_SCFSR, base + SCIF_SCFTDR); 73 74 /* Clear bits TE and RE in SCSCR to 0 */ 75 mmio_write_16(base + SCIF_SCSCR, 0); 76 77 /* Set bits TFRST and RFRST in SCFCR to 1 */ 78 mmio_clrsetbits_16(base + SCIF_SCFCR, 79 SCFCR_TFRST_EN | SCFCR_RFRS_EN, 80 SCFCR_TFRST_EN | SCFCR_RFRS_EN); 81 82 /* 83 * Read flags of ER, DR, BRK, and RDF in SCFSR and those 84 * of TO and ORER in SCLSR, then clear them to 0. 85 */ 86 mmio_write_16(base + SCIF_SCFSR, 0); 87 mmio_write_16(base + SCIF_SCLSR, 0); 88 89 /* Set bits CKE[1:0] in SCSCR */ 90 mmio_clrsetbits_16(base + SCIF_SCSCR, SCSCR_CKE_MASK, 91 SCSCR_CKE_INT_CLK); 92 93 /* Set data transfer format in SCSMR */ 94 mmio_write_16(base + SCIF_SCSMR, 0); 95 96 /* Set value in SCBRR */ 97 if ((prr & (PRR_PRODUCT_MASK | PRR_CUT_MASK)) == PRR_PRODUCT_H3_CUT10) { 98 /* H3 ES 1.0 */ 99 mmio_write_8(base + SCIF_SCBRR, SCBRR_230400BPS); 100 } else if (((prr & PRR_PRODUCT_MASK) == PRR_PRODUCT_D3) && 101 (mmio_read_32(RST_MODEMR) & MODEMR_MD12)) { 102 /* D3 with SSCG(MD12) ON */ 103 mmio_write_8(base + SCIF_SCBRR, SCBRR_115200BPS_D3_SSCG); 104 } else if (((prr & PRR_PRODUCT_MASK) == PRR_PRODUCT_E3) && 105 (mmio_read_32(RST_MODEMR) & MODEMR_MD12)) { 106 /* E3 with SSCG(MD12) ON */ 107 mmio_write_8(base + SCIF_SCBRR, SCBRR_115200BPS_E3_SSCG); 108 } else { 109 /* H3/M3/M3N or when SSCG(MD12) is off in E3/D3 */ 110 mmio_write_8(base + SCIF_SCBRR, SCBRR_115200BPS); 111 } 112 113 /* 1-bit interval elapsed */ 114 for (i = 0; i < 100; i++) 115 asm volatile("nop"); 116 117 /* 118 * Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR 119 * Clear bits FRST and RFRST to 0 120 */ 121 mmio_write_16(base + SCIF_SCFCR, 0); 122 123 /* Set bits TE and RE in SCSCR to 1 */ 124 mmio_clrsetbits_16(base + SCIF_SCSCR, SCSCR_TE_EN | SCSCR_RE_EN, 125 SCSCR_TE_EN | SCSCR_RE_EN); 126 127 return 1; 128 } 129