1*f1be0792SBiju Das /* 2*f1be0792SBiju Das * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3*f1be0792SBiju Das * 4*f1be0792SBiju Das * SPDX-License-Identifier: BSD-3-Clause 5*f1be0792SBiju Das */ 6*f1be0792SBiju Das 7*f1be0792SBiju Das #include <stdint.h> 8*f1be0792SBiju Das #include <string.h> 9*f1be0792SBiju Das 10*f1be0792SBiju Das #include <common/debug.h> 11*f1be0792SBiju Das #include <lib/mmio.h> 12*f1be0792SBiju Das 13*f1be0792SBiju Das #include "cpg_registers.h" 14*f1be0792SBiju Das #include "rcar_def.h" 15*f1be0792SBiju Das #include "rcar_private.h" 16*f1be0792SBiju Das #include "rpc_registers.h" 17*f1be0792SBiju Das 18*f1be0792SBiju Das #define MSTPSR9_RPC_BIT (0x00020000U) 19*f1be0792SBiju Das #define RPC_CMNCR_MD_BIT (0x80000000U) 20*f1be0792SBiju Das #define RPC_PHYCNT_CAL BIT(31) 21*f1be0792SBiju Das #define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL) 22*f1be0792SBiju Das #define RPC_PHYCNT_STRTIM (0x7 << 15UL) 23*f1be0792SBiju Das rpc_enable(void)24*f1be0792SBiju Dasstatic void rpc_enable(void) 25*f1be0792SBiju Das { 26*f1be0792SBiju Das /* Enable clock supply to RPC. */ 27*f1be0792SBiju Das mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT); 28*f1be0792SBiju Das } 29*f1be0792SBiju Das rpc_setup(void)30*f1be0792SBiju Dasstatic void rpc_setup(void) 31*f1be0792SBiju Das { 32*f1be0792SBiju Das uint32_t product, cut, reg, phy_strtim; 33*f1be0792SBiju Das 34*f1be0792SBiju Das if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT) 35*f1be0792SBiju Das mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT); 36*f1be0792SBiju Das 37*f1be0792SBiju Das product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; 38*f1be0792SBiju Das cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; 39*f1be0792SBiju Das 40*f1be0792SBiju Das if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30)) 41*f1be0792SBiju Das phy_strtim = RPC_PHYCNT_STRTIM_M3V1; 42*f1be0792SBiju Das else 43*f1be0792SBiju Das phy_strtim = RPC_PHYCNT_STRTIM; 44*f1be0792SBiju Das 45*f1be0792SBiju Das reg = mmio_read_32(RPC_PHYCNT); 46*f1be0792SBiju Das reg &= ~RPC_PHYCNT_STRTIM; 47*f1be0792SBiju Das reg |= phy_strtim; 48*f1be0792SBiju Das mmio_write_32(RPC_PHYCNT, reg); 49*f1be0792SBiju Das reg |= RPC_PHYCNT_CAL; 50*f1be0792SBiju Das mmio_write_32(RPC_PHYCNT, reg); 51*f1be0792SBiju Das } 52*f1be0792SBiju Das rcar_rpc_init(void)53*f1be0792SBiju Dasvoid rcar_rpc_init(void) 54*f1be0792SBiju Das { 55*f1be0792SBiju Das rpc_enable(); 56*f1be0792SBiju Das rpc_setup(); 57*f1be0792SBiju Das } 58