1*662d3cc8SBiju Das /* 2*662d3cc8SBiju Das * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved. 3*662d3cc8SBiju Das * 4*662d3cc8SBiju Das * SPDX-License-Identifier: BSD-3-Clause 5*662d3cc8SBiju Das */ 6*662d3cc8SBiju Das 7*662d3cc8SBiju Das #ifndef QOS_REG_H 8*662d3cc8SBiju Das #define QOS_REG_H 9*662d3cc8SBiju Das 10*662d3cc8SBiju Das #define RCAR_QOS_NONE 3U 11*662d3cc8SBiju Das #define RCAR_QOS_TYPE_DEFAULT 0U 12*662d3cc8SBiju Das 13*662d3cc8SBiju Das #define RCAR_DRAM_SPLIT_LINEAR 0U 14*662d3cc8SBiju Das #define RCAR_DRAM_SPLIT_4CH 1U 15*662d3cc8SBiju Das #define RCAR_DRAM_SPLIT_2CH 2U 16*662d3cc8SBiju Das #define RCAR_DRAM_SPLIT_AUTO 3U 17*662d3cc8SBiju Das #define RST_BASE (0xE6160000U) 18*662d3cc8SBiju Das #define RST_MODEMR (RST_BASE + 0x0060U) 19*662d3cc8SBiju Das 20*662d3cc8SBiju Das #define DBSC_BASE 0xE6790000U 21*662d3cc8SBiju Das #define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) 22*662d3cc8SBiju Das #define DBSC_AXARB (DBSC_BASE + 0x0800U) 23*662d3cc8SBiju Das #define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) 24*662d3cc8SBiju Das #define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) 25*662d3cc8SBiju Das #define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) 26*662d3cc8SBiju Das #define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) 27*662d3cc8SBiju Das #define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) 28*662d3cc8SBiju Das #define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) 29*662d3cc8SBiju Das #define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) 30*662d3cc8SBiju Das #define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) 31*662d3cc8SBiju Das #define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U) 32*662d3cc8SBiju Das #define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U) 33*662d3cc8SBiju Das #define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U) 34*662d3cc8SBiju Das #define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU) 35*662d3cc8SBiju Das #define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U) 36*662d3cc8SBiju Das #define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U) 37*662d3cc8SBiju Das #define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U) 38*662d3cc8SBiju Das #define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU) 39*662d3cc8SBiju Das #define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U) 40*662d3cc8SBiju Das #define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U) 41*662d3cc8SBiju Das #define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U) 42*662d3cc8SBiju Das #define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU) 43*662d3cc8SBiju Das #define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U) 44*662d3cc8SBiju Das #define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U) 45*662d3cc8SBiju Das #define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U) 46*662d3cc8SBiju Das #define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU) 47*662d3cc8SBiju Das #define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U) 48*662d3cc8SBiju Das #define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U) 49*662d3cc8SBiju Das #define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U) 50*662d3cc8SBiju Das #define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU) 51*662d3cc8SBiju Das #define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U) 52*662d3cc8SBiju Das #define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U) 53*662d3cc8SBiju Das #define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U) 54*662d3cc8SBiju Das #define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU) 55*662d3cc8SBiju Das #define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U) 56*662d3cc8SBiju Das #define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U) 57*662d3cc8SBiju Das #define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U) 58*662d3cc8SBiju Das #define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU) 59*662d3cc8SBiju Das #define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) 60*662d3cc8SBiju Das #define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) 61*662d3cc8SBiju Das #define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) 62*662d3cc8SBiju Das 63*662d3cc8SBiju Das #define AXI_BASE 0xE6784000U 64*662d3cc8SBiju Das #define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) 65*662d3cc8SBiju Das #define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) 66*662d3cc8SBiju Das #define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) 67*662d3cc8SBiju Das #define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) 68*662d3cc8SBiju Das #define AXI_MMCR (AXI_BASE + 0x0300U) 69*662d3cc8SBiju Das #define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) 70*662d3cc8SBiju Das #define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) 71*662d3cc8SBiju Das #define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) 72*662d3cc8SBiju Das #define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) 73*662d3cc8SBiju Das #define ADSPLCR0_SWP 0x0CU 74*662d3cc8SBiju Das 75*662d3cc8SBiju Das #define AXI_TR3CR 0xE67D100CU 76*662d3cc8SBiju Das #define AXI_TR4CR 0xE67D1014U 77*662d3cc8SBiju Das 78*662d3cc8SBiju Das #define QOS_BASE0 0xE67E0000U 79*662d3cc8SBiju Das #define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U) 80*662d3cc8SBiju Das #define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U) 81*662d3cc8SBiju Das #define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U) 82*662d3cc8SBiju Das #define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U) 83*662d3cc8SBiju Das #define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U) 84*662d3cc8SBiju Das #define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U) 85*662d3cc8SBiju Das #define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U) 86*662d3cc8SBiju Das 87*662d3cc8SBiju Das #define QOS_BASE1 0xE67F0000U 88*662d3cc8SBiju Das #define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) 89*662d3cc8SBiju Das #define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U) 90*662d3cc8SBiju Das #define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) 91*662d3cc8SBiju Das #define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U) 92*662d3cc8SBiju Das #define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) 93*662d3cc8SBiju Das #define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) 94*662d3cc8SBiju Das #define QOSCTRL_EC (QOS_BASE1 + 0x003CU) 95*662d3cc8SBiju Das #define QOSCTRL_EMS (QOS_BASE1 + 0x0040U) 96*662d3cc8SBiju Das #define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) 97*662d3cc8SBiju Das #define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) 98*662d3cc8SBiju Das #define QOSCTRL_BERR (QOS_BASE1 + 0x0054U) 99*662d3cc8SBiju Das #define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U) 100*662d3cc8SBiju Das #define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) 101*662d3cc8SBiju Das #define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) 102*662d3cc8SBiju Das 103*662d3cc8SBiju Das #define GPU_ACT_GRD 0xFD820808U 104*662d3cc8SBiju Das #define GPU_ACT0 0xFD820800U 105*662d3cc8SBiju Das #define GPU_ACT1 0xFD821800U 106*662d3cc8SBiju Das #define GPU_ACT2 0xFD822800U 107*662d3cc8SBiju Das #define GPU_ACT3 0xFD823800U 108*662d3cc8SBiju Das #define GPU_ACT4 0xFD824800U 109*662d3cc8SBiju Das #define GPU_ACT5 0xFD825800U 110*662d3cc8SBiju Das #define GPU_ACT6 0xFD826800U 111*662d3cc8SBiju Das #define GPU_ACT7 0xFD827800U 112*662d3cc8SBiju Das 113*662d3cc8SBiju Das #define RT_ACT0 0xFFC50800U 114*662d3cc8SBiju Das #define RT_ACT1 0xFFC51800U 115*662d3cc8SBiju Das 116*662d3cc8SBiju Das #define CPU_ACT0 0xF1300800U 117*662d3cc8SBiju Das #define CPU_ACT1 0xF1340800U 118*662d3cc8SBiju Das #define CPU_ACT2 0xF1380800U 119*662d3cc8SBiju Das #define CPU_ACT3 0xF13C0800U 120*662d3cc8SBiju Das 121*662d3cc8SBiju Das #define RCAR_REWT_TRAINING_DISABLE 0U 122*662d3cc8SBiju Das #define RCAR_REWT_TRAINING_ENABLE 1U 123*662d3cc8SBiju Das 124*662d3cc8SBiju Das #define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U) 125*662d3cc8SBiju Das #define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U) 126*662d3cc8SBiju Das #define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U) 127*662d3cc8SBiju Das #define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U) 128*662d3cc8SBiju Das #define QOSWT_WTEN (QOS_BASE0 + 0x8030U) 129*662d3cc8SBiju Das #define QOSWT_WTREF (QOS_BASE0 + 0x8034U) 130*662d3cc8SBiju Das #define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U) 131*662d3cc8SBiju Das #define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU) 132*662d3cc8SBiju Das 133*662d3cc8SBiju Das #endif /* QOS_REG_H */ 134