1*c40739a6SBiju Das /* 2*c40739a6SBiju Das * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3*c40739a6SBiju Das * 4*c40739a6SBiju Das * SPDX-License-Identifier: BSD-3-Clause 5*c40739a6SBiju Das */ 6*c40739a6SBiju Das 7*c40739a6SBiju Das #ifndef PWRC_H 8*c40739a6SBiju Das #define PWRC_H 9*c40739a6SBiju Das 10*c40739a6SBiju Das #define PPOFFR_OFF 0x0 11*c40739a6SBiju Das #define PPONR_OFF 0x4 12*c40739a6SBiju Das #define PCOFFR_OFF 0x8 13*c40739a6SBiju Das #define PWKUPR_OFF 0xc 14*c40739a6SBiju Das #define PSYSR_OFF 0x10 15*c40739a6SBiju Das 16*c40739a6SBiju Das #define PWKUPR_WEN (1ull << 31) 17*c40739a6SBiju Das 18*c40739a6SBiju Das #define PSYSR_AFF_L2 (1U << 31) 19*c40739a6SBiju Das #define PSYSR_AFF_L1 (1 << 30) 20*c40739a6SBiju Das #define PSYSR_AFF_L0 (1 << 29) 21*c40739a6SBiju Das #define PSYSR_WEN (1 << 28) 22*c40739a6SBiju Das #define PSYSR_PC (1 << 27) 23*c40739a6SBiju Das #define PSYSR_PP (1 << 26) 24*c40739a6SBiju Das 25*c40739a6SBiju Das #define PSYSR_WK_SHIFT (24) 26*c40739a6SBiju Das #define PSYSR_WK_MASK (0x3) 27*c40739a6SBiju Das #define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK) 28*c40739a6SBiju Das 29*c40739a6SBiju Das #define WKUP_COLD 0x0 30*c40739a6SBiju Das #define WKUP_RESET 0x1 31*c40739a6SBiju Das #define WKUP_PPONR 0x2 32*c40739a6SBiju Das #define WKUP_GICREQ 0x3 33*c40739a6SBiju Das 34*c40739a6SBiju Das #define RCAR_INVALID (0xffffffffU) 35*c40739a6SBiju Das #define PSYSR_INVALID 0xffffffff 36*c40739a6SBiju Das 37*c40739a6SBiju Das #define RCAR_CLUSTER_A53A57 (0U) 38*c40739a6SBiju Das #define RCAR_CLUSTER_CA53 (1U) 39*c40739a6SBiju Das #define RCAR_CLUSTER_CA57 (2U) 40*c40739a6SBiju Das 41*c40739a6SBiju Das #ifndef __ASSEMBLER__ 42*c40739a6SBiju Das void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); 43*c40739a6SBiju Das void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); 44*c40739a6SBiju Das void rcar_pwrc_clusteroff(uint64_t mpidr); 45*c40739a6SBiju Das void rcar_pwrc_cpuoff(uint64_t mpidr); 46*c40739a6SBiju Das void rcar_pwrc_cpuon(uint64_t mpidr); 47*c40739a6SBiju Das int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr); 48*c40739a6SBiju Das void rcar_pwrc_setup(void); 49*c40739a6SBiju Das 50*c40739a6SBiju Das uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr); 51*c40739a6SBiju Das uint32_t rcar_pwrc_status(uint64_t mpidr); 52*c40739a6SBiju Das uint32_t rcar_pwrc_get_cluster(void); 53*c40739a6SBiju Das uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr); 54*c40739a6SBiju Das uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); 55*c40739a6SBiju Das void rcar_pwrc_restore_timer_state(void); 56*c40739a6SBiju Das void plat_secondary_reset(void); 57*c40739a6SBiju Das 58*c40739a6SBiju Das void rcar_pwrc_code_copy_to_system_ram(void); 59*c40739a6SBiju Das 60*c40739a6SBiju Das #if !PMIC_ROHM_BD9571 61*c40739a6SBiju Das void rcar_pwrc_system_reset(void); 62*c40739a6SBiju Das #endif 63*c40739a6SBiju Das 64*c40739a6SBiju Das #if RCAR_SYSTEM_SUSPEND 65*c40739a6SBiju Das void rcar_pwrc_go_suspend_to_ram(void); 66*c40739a6SBiju Das void rcar_pwrc_set_suspend_to_ram(void); 67*c40739a6SBiju Das void rcar_pwrc_init_suspend_to_ram(void); 68*c40739a6SBiju Das void rcar_pwrc_suspend_to_ram(void); 69*c40739a6SBiju Das #endif 70*c40739a6SBiju Das 71*c40739a6SBiju Das extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack, 72*c40739a6SBiju Das void *arg); 73*c40739a6SBiju Das #endif 74*c40739a6SBiju Das 75*c40739a6SBiju Das #endif /* PWRC_H */ 76