1*6f97490eSBiju Das /* 2*6f97490eSBiju Das * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3*6f97490eSBiju Das * 4*6f97490eSBiju Das * SPDX-License-Identifier: BSD-3-Clause 5*6f97490eSBiju Das */ 6*6f97490eSBiju Das 7*6f97490eSBiju Das #include <stdint.h> 8*6f97490eSBiju Das #include <string.h> 9*6f97490eSBiju Das 10*6f97490eSBiju Das #include <arch_helpers.h> 11*6f97490eSBiju Das #include <common/debug.h> 12*6f97490eSBiju Das #include <lib/mmio.h> 13*6f97490eSBiju Das 14*6f97490eSBiju Das #include "cpg_registers.h" 15*6f97490eSBiju Das #include "rcar_def.h" 16*6f97490eSBiju Das #include "rcar_private.h" 17*6f97490eSBiju Das 18*6f97490eSBiju Das /* DMA CHANNEL setting (0/16/32) */ 19*6f97490eSBiju Das #if RCAR_LSI == RCAR_V3M 20*6f97490eSBiju Das #define DMA_CH 16 21*6f97490eSBiju Das #else 22*6f97490eSBiju Das #define DMA_CH 0 23*6f97490eSBiju Das #endif 24*6f97490eSBiju Das 25*6f97490eSBiju Das #if (DMA_CH == 0) 26*6f97490eSBiju Das #define SYS_DMAC_BIT ((uint32_t)1U << 19U) 27*6f97490eSBiju Das #define DMA_BASE (0xE6700000U) 28*6f97490eSBiju Das #elif (DMA_CH == 16) 29*6f97490eSBiju Das #define SYS_DMAC_BIT ((uint32_t)1U << 18U) 30*6f97490eSBiju Das #define DMA_BASE (0xE7300000U) 31*6f97490eSBiju Das #elif (DMA_CH == 32) 32*6f97490eSBiju Das #define SYS_DMAC_BIT ((uint32_t)1U << 17U) 33*6f97490eSBiju Das #define DMA_BASE (0xE7320000U) 34*6f97490eSBiju Das #else 35*6f97490eSBiju Das #define SYS_DMAC_BIT ((uint32_t)1U << 19U) 36*6f97490eSBiju Das #define DMA_BASE (0xE6700000U) 37*6f97490eSBiju Das #endif 38*6f97490eSBiju Das 39*6f97490eSBiju Das /* DMA operation */ 40*6f97490eSBiju Das #define DMA_DMAOR (DMA_BASE + 0x0060U) 41*6f97490eSBiju Das /* DMA secure control */ 42*6f97490eSBiju Das #define DMA_DMASEC (DMA_BASE + 0x0030U) 43*6f97490eSBiju Das /* DMA channel clear */ 44*6f97490eSBiju Das #define DMA_DMACHCLR (DMA_BASE + 0x0080U) 45*6f97490eSBiju Das /* DMA source address */ 46*6f97490eSBiju Das #define DMA_DMASAR (DMA_BASE + 0x8000U) 47*6f97490eSBiju Das /* DMA destination address */ 48*6f97490eSBiju Das #define DMA_DMADAR (DMA_BASE + 0x8004U) 49*6f97490eSBiju Das /* DMA transfer count */ 50*6f97490eSBiju Das #define DMA_DMATCR (DMA_BASE + 0x8008U) 51*6f97490eSBiju Das /* DMA channel control */ 52*6f97490eSBiju Das #define DMA_DMACHCR (DMA_BASE + 0x800CU) 53*6f97490eSBiju Das /* DMA fixed destination address */ 54*6f97490eSBiju Das #define DMA_DMAFIXDAR (DMA_BASE + 0x8014U) 55*6f97490eSBiju Das 56*6f97490eSBiju Das #define DMA_USE_CHANNEL (0x00000001U) 57*6f97490eSBiju Das #define DMAOR_INITIAL (0x0301U) 58*6f97490eSBiju Das #define DMACHCLR_CH_ALL (0x0000FFFFU) 59*6f97490eSBiju Das #define DMAFIXDAR_32BIT_SHIFT (32U) 60*6f97490eSBiju Das #define DMAFIXDAR_DAR_MASK (0x000000FFU) 61*6f97490eSBiju Das #define DMADAR_BOUNDARY_ADDR (0x100000000ULL) 62*6f97490eSBiju Das #define DMATCR_CNT_SHIFT (6U) 63*6f97490eSBiju Das #define DMATCR_MAX (0x00FFFFFFU) 64*6f97490eSBiju Das #define DMACHCR_TRN_MODE (0x00105409U) 65*6f97490eSBiju Das #define DMACHCR_DE_BIT (0x00000001U) 66*6f97490eSBiju Das #define DMACHCR_TE_BIT (0x00000002U) 67*6f97490eSBiju Das #define DMACHCR_CHE_BIT (0x80000000U) 68*6f97490eSBiju Das 69*6f97490eSBiju Das #define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT 70*6f97490eSBiju Das #define DMA_FRACTION_MASK (0xFFU) 71*6f97490eSBiju Das #define DMA_DST_LIMIT (0x10000000000ULL) 72*6f97490eSBiju Das 73*6f97490eSBiju Das /* transfer length limit */ 74*6f97490eSBiju Das #define DMA_LENGTH_LIMIT ((DMATCR_MAX * (1U << DMATCR_CNT_SHIFT)) \ 75*6f97490eSBiju Das & ~DMA_FRACTION_MASK) 76*6f97490eSBiju Das 77*6f97490eSBiju Das static void dma_enable(void) 78*6f97490eSBiju Das { 79*6f97490eSBiju Das mstpcr_write(CPG_SMSTPCR2, CPG_MSTPSR2, SYS_DMAC_BIT); 80*6f97490eSBiju Das } 81*6f97490eSBiju Das 82*6f97490eSBiju Das static void dma_setup(void) 83*6f97490eSBiju Das { 84*6f97490eSBiju Das mmio_write_16(DMA_DMAOR, 0); 85*6f97490eSBiju Das mmio_write_32(DMA_DMACHCLR, DMACHCLR_CH_ALL); 86*6f97490eSBiju Das } 87*6f97490eSBiju Das 88*6f97490eSBiju Das static void dma_start(uintptr_t dst, uint32_t src, uint32_t len) 89*6f97490eSBiju Das { 90*6f97490eSBiju Das mmio_write_16(DMA_DMAOR, DMAOR_INITIAL); 91*6f97490eSBiju Das mmio_write_32(DMA_DMAFIXDAR, (dst >> DMAFIXDAR_32BIT_SHIFT) & 92*6f97490eSBiju Das DMAFIXDAR_DAR_MASK); 93*6f97490eSBiju Das mmio_write_32(DMA_DMADAR, dst & UINT32_MAX); 94*6f97490eSBiju Das mmio_write_32(DMA_DMASAR, src); 95*6f97490eSBiju Das mmio_write_32(DMA_DMATCR, len >> DMATCR_CNT_SHIFT); 96*6f97490eSBiju Das mmio_write_32(DMA_DMASEC, DMA_USE_CHANNEL); 97*6f97490eSBiju Das mmio_write_32(DMA_DMACHCR, DMACHCR_TRN_MODE); 98*6f97490eSBiju Das } 99*6f97490eSBiju Das 100*6f97490eSBiju Das static void dma_end(void) 101*6f97490eSBiju Das { 102*6f97490eSBiju Das while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_TE_BIT) == 0) { 103*6f97490eSBiju Das if ((mmio_read_32(DMA_DMACHCR) & DMACHCR_CHE_BIT) != 0U) { 104*6f97490eSBiju Das ERROR("BL2: DMA - Channel Address Error\n"); 105*6f97490eSBiju Das panic(); 106*6f97490eSBiju Das break; 107*6f97490eSBiju Das } 108*6f97490eSBiju Das } 109*6f97490eSBiju Das /* DMA transfer Disable */ 110*6f97490eSBiju Das mmio_clrbits_32(DMA_DMACHCR, DMACHCR_DE_BIT); 111*6f97490eSBiju Das while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_DE_BIT) != 0) 112*6f97490eSBiju Das ; 113*6f97490eSBiju Das 114*6f97490eSBiju Das mmio_write_32(DMA_DMASEC, 0); 115*6f97490eSBiju Das mmio_write_16(DMA_DMAOR, 0); 116*6f97490eSBiju Das mmio_write_32(DMA_DMACHCLR, DMA_USE_CHANNEL); 117*6f97490eSBiju Das } 118*6f97490eSBiju Das 119*6f97490eSBiju Das void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len) 120*6f97490eSBiju Das { 121*6f97490eSBiju Das uint32_t dma_len = len; 122*6f97490eSBiju Das 123*6f97490eSBiju Das if (len & DMA_FRACTION_MASK) 124*6f97490eSBiju Das dma_len = (len + DMA_SIZE_UNIT) & ~DMA_FRACTION_MASK; 125*6f97490eSBiju Das 126*6f97490eSBiju Das if (!dma_len || dma_len > DMA_LENGTH_LIMIT) { 127*6f97490eSBiju Das ERROR("BL2: DMA - size invalid, length (0x%x)\n", dma_len); 128*6f97490eSBiju Das panic(); 129*6f97490eSBiju Das } 130*6f97490eSBiju Das 131*6f97490eSBiju Das if (src & DMA_FRACTION_MASK) { 132*6f97490eSBiju Das ERROR("BL2: DMA - src address invalid (0x%x), len=(0x%x)\n", 133*6f97490eSBiju Das src, dma_len); 134*6f97490eSBiju Das panic(); 135*6f97490eSBiju Das } 136*6f97490eSBiju Das 137*6f97490eSBiju Das if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR || 138*6f97490eSBiju Das (dst + dma_len > DMA_DST_LIMIT) || 139*6f97490eSBiju Das (dst & DMA_FRACTION_MASK)) { 140*6f97490eSBiju Das ERROR("BL2: DMA - dest address invalid (0x%lx), len=(0x%x)\n", 141*6f97490eSBiju Das dst, dma_len); 142*6f97490eSBiju Das panic(); 143*6f97490eSBiju Das } 144*6f97490eSBiju Das 145*6f97490eSBiju Das dma_start(dst, src, dma_len); 146*6f97490eSBiju Das dma_end(); 147*6f97490eSBiju Das } 148*6f97490eSBiju Das 149*6f97490eSBiju Das void rcar_dma_init(void) 150*6f97490eSBiju Das { 151*6f97490eSBiju Das dma_enable(); 152*6f97490eSBiju Das dma_setup(); 153*6f97490eSBiju Das } 154