1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <plat_tzc380.h> 9 10 #pragma weak populate_tzc380_reg_list 11 12 #ifdef DEFAULT_TZASC_CONFIG 13 /* 14 * Typical Memory map of DRAM0 15 * |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------| 16 * | | 17 * | | 18 * | Non-SECURE REGION | 19 * | | 20 * | | 21 * | | 22 * |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------| 23 * |-----------------NXP_SECURE_DRAM_ADDR--------------------| 24 * | | 25 * | | 26 * | | 27 * | SECURE REGION (= 64MB) | 28 * | | 29 * | | 30 * | | 31 * |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----| 32 * |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------| 33 * | | 34 * | Secure EL1 Payload SHARED REGION (= 2MB) | 35 * | | 36 * |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------| 37 * 38 * 39 * 40 * Typical Memory map of DRAM1 41 * |---------------------NXP_DRAM1_ADDR----------------------| 42 * | | 43 * | | 44 * | Non-SECURE REGION | 45 * | | 46 * | | 47 * |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---| 48 * 49 * 50 * Typical Memory map of DRAM2 51 * |---------------------NXP_DRAM2_ADDR----------------------| 52 * | | 53 * | | 54 * | Non-SECURE REGION | 55 * | | 56 * | | 57 * |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---| 58 */ 59 60 /***************************************************************************** 61 * This function sets up access permissions on memory regions 62 * 63 * Input: 64 * tzc380_reg_list : TZC380 Region List 65 * dram_idx : DRAM index 66 * list_idx : TZC380 Region List Index 67 * dram_start_addr : Start address of DRAM at dram_idx. 68 * dram_size : Size of DRAM at dram_idx. 69 * secure_dram_sz : Secure DRAM Size 70 * shrd_dram_sz : Shared DRAM Size 71 * 72 * Out: 73 * list_idx : last populated index + 1 74 * 75 ****************************************************************************/ 76 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, 77 int dram_idx, int list_idx, 78 uint64_t dram_start_addr, 79 uint64_t dram_size, 80 uint32_t secure_dram_sz, 81 uint32_t shrd_dram_sz) 82 { 83 /* Region 0: Default region marked as Non-Secure */ 84 if (list_idx == 0) { 85 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW; 86 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE; 87 tzc380_reg_list[list_idx].addr = UL(0x0); 88 tzc380_reg_list[list_idx].size = 0x0; 89 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ 90 list_idx++; 91 } 92 /* Continue with list entries for index > 0 */ 93 if (dram_idx == 0) { 94 /* TZC Region 1 on DRAM0 for Secure Memory*/ 95 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW; 96 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; 97 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size; 98 tzc380_reg_list[list_idx].size = secure_dram_sz; 99 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ 100 list_idx++; 101 102 /* TZC Region 2 on DRAM0 for Shared Memory*/ 103 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW; 104 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; 105 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz; 106 tzc380_reg_list[list_idx].size = shrd_dram_sz; 107 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ 108 list_idx++; 109 110 } 111 112 return list_idx; 113 } 114 #else 115 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, 116 int dram_idx, int list_idx, 117 uint64_t dram_start_addr, 118 uint64_t dram_size, 119 uint32_t secure_dram_sz, 120 uint32_t shrd_dram_sz) 121 { 122 ERROR("tzc380_reg_list used is not a default list\n"); 123 ERROR("%s needs to be over-written.\n", __func__); 124 return 0; 125 } 126 #endif /* DEFAULT_TZASC_CONFIG */ 127 128 129 void mem_access_setup(uintptr_t base, uint32_t total_regions, 130 struct tzc380_reg *tzc380_reg_list) 131 { 132 uint32_t indx = 0; 133 unsigned int attr_value; 134 135 VERBOSE("Configuring TrustZone Controller tzc380\n"); 136 137 tzc380_init(base); 138 139 tzc380_set_action(TZC_ACTION_NONE); 140 141 for (indx = 0; indx < total_regions; indx++) { 142 attr_value = tzc380_reg_list[indx].secure | 143 TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) | 144 TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) | 145 tzc380_reg_list[indx].enabled; 146 147 tzc380_configure_region(indx, tzc380_reg_list[indx].addr, 148 attr_value); 149 } 150 151 tzc380_set_action(TZC_ACTION_ERR); 152 } 153