1*de9e57ffSJiafei Pan /* 2*de9e57ffSJiafei Pan * Copyright 2018-2021 NXP 3*de9e57ffSJiafei Pan * 4*de9e57ffSJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*de9e57ffSJiafei Pan */ 6*de9e57ffSJiafei Pan 7*de9e57ffSJiafei Pan #include <common/debug.h> 8*de9e57ffSJiafei Pan #include <plat_tzc380.h> 9*de9e57ffSJiafei Pan 10*de9e57ffSJiafei Pan #pragma weak populate_tzc380_reg_list 11*de9e57ffSJiafei Pan 12*de9e57ffSJiafei Pan #ifdef DEFAULT_TZASC_CONFIG 13*de9e57ffSJiafei Pan /* 14*de9e57ffSJiafei Pan * Typical Memory map of DRAM0 15*de9e57ffSJiafei Pan * |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------| 16*de9e57ffSJiafei Pan * | | 17*de9e57ffSJiafei Pan * | | 18*de9e57ffSJiafei Pan * | Non-SECURE REGION | 19*de9e57ffSJiafei Pan * | | 20*de9e57ffSJiafei Pan * | | 21*de9e57ffSJiafei Pan * | | 22*de9e57ffSJiafei Pan * |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------| 23*de9e57ffSJiafei Pan * |-----------------NXP_SECURE_DRAM_ADDR--------------------| 24*de9e57ffSJiafei Pan * | | 25*de9e57ffSJiafei Pan * | | 26*de9e57ffSJiafei Pan * | | 27*de9e57ffSJiafei Pan * | SECURE REGION (= 64MB) | 28*de9e57ffSJiafei Pan * | | 29*de9e57ffSJiafei Pan * | | 30*de9e57ffSJiafei Pan * | | 31*de9e57ffSJiafei Pan * |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----| 32*de9e57ffSJiafei Pan * |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------| 33*de9e57ffSJiafei Pan * | | 34*de9e57ffSJiafei Pan * | Secure EL1 Payload SHARED REGION (= 2MB) | 35*de9e57ffSJiafei Pan * | | 36*de9e57ffSJiafei Pan * |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------| 37*de9e57ffSJiafei Pan * 38*de9e57ffSJiafei Pan * 39*de9e57ffSJiafei Pan * 40*de9e57ffSJiafei Pan * Typical Memory map of DRAM1 41*de9e57ffSJiafei Pan * |---------------------NXP_DRAM1_ADDR----------------------| 42*de9e57ffSJiafei Pan * | | 43*de9e57ffSJiafei Pan * | | 44*de9e57ffSJiafei Pan * | Non-SECURE REGION | 45*de9e57ffSJiafei Pan * | | 46*de9e57ffSJiafei Pan * | | 47*de9e57ffSJiafei Pan * |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---| 48*de9e57ffSJiafei Pan * 49*de9e57ffSJiafei Pan * 50*de9e57ffSJiafei Pan * Typical Memory map of DRAM2 51*de9e57ffSJiafei Pan * |---------------------NXP_DRAM2_ADDR----------------------| 52*de9e57ffSJiafei Pan * | | 53*de9e57ffSJiafei Pan * | | 54*de9e57ffSJiafei Pan * | Non-SECURE REGION | 55*de9e57ffSJiafei Pan * | | 56*de9e57ffSJiafei Pan * | | 57*de9e57ffSJiafei Pan * |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---| 58*de9e57ffSJiafei Pan */ 59*de9e57ffSJiafei Pan 60*de9e57ffSJiafei Pan /***************************************************************************** 61*de9e57ffSJiafei Pan * This function sets up access permissions on memory regions 62*de9e57ffSJiafei Pan * 63*de9e57ffSJiafei Pan * Input: 64*de9e57ffSJiafei Pan * tzc380_reg_list : TZC380 Region List 65*de9e57ffSJiafei Pan * dram_idx : DRAM index 66*de9e57ffSJiafei Pan * list_idx : TZC380 Region List Index 67*de9e57ffSJiafei Pan * dram_start_addr : Start address of DRAM at dram_idx. 68*de9e57ffSJiafei Pan * dram_size : Size of DRAM at dram_idx. 69*de9e57ffSJiafei Pan * secure_dram_sz : Secure DRAM Size 70*de9e57ffSJiafei Pan * shrd_dram_sz : Shared DRAM Size 71*de9e57ffSJiafei Pan * 72*de9e57ffSJiafei Pan * Out: 73*de9e57ffSJiafei Pan * list_idx : last populated index + 1 74*de9e57ffSJiafei Pan * 75*de9e57ffSJiafei Pan ****************************************************************************/ 76*de9e57ffSJiafei Pan int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, 77*de9e57ffSJiafei Pan int dram_idx, int list_idx, 78*de9e57ffSJiafei Pan uint64_t dram_start_addr, 79*de9e57ffSJiafei Pan uint64_t dram_size, 80*de9e57ffSJiafei Pan uint32_t secure_dram_sz, 81*de9e57ffSJiafei Pan uint32_t shrd_dram_sz) 82*de9e57ffSJiafei Pan { 83*de9e57ffSJiafei Pan /* Region 0: Default region marked as Non-Secure */ 84*de9e57ffSJiafei Pan if (list_idx == 0) { 85*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW; 86*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE; 87*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].addr = UL(0x0); 88*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].size = 0x0; 89*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ 90*de9e57ffSJiafei Pan list_idx++; 91*de9e57ffSJiafei Pan } 92*de9e57ffSJiafei Pan /* Continue with list entries for index > 0 */ 93*de9e57ffSJiafei Pan if (dram_idx == 0) { 94*de9e57ffSJiafei Pan /* TZC Region 1 on DRAM0 for Secure Memory*/ 95*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW; 96*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; 97*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size; 98*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].size = secure_dram_sz; 99*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ 100*de9e57ffSJiafei Pan list_idx++; 101*de9e57ffSJiafei Pan 102*de9e57ffSJiafei Pan /* TZC Region 2 on DRAM0 for Shared Memory*/ 103*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW; 104*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; 105*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz; 106*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].size = shrd_dram_sz; 107*de9e57ffSJiafei Pan tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ 108*de9e57ffSJiafei Pan list_idx++; 109*de9e57ffSJiafei Pan 110*de9e57ffSJiafei Pan } 111*de9e57ffSJiafei Pan 112*de9e57ffSJiafei Pan return list_idx; 113*de9e57ffSJiafei Pan } 114*de9e57ffSJiafei Pan #else 115*de9e57ffSJiafei Pan int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, 116*de9e57ffSJiafei Pan int dram_idx, int list_idx, 117*de9e57ffSJiafei Pan uint64_t dram_start_addr, 118*de9e57ffSJiafei Pan uint64_t dram_size, 119*de9e57ffSJiafei Pan uint32_t secure_dram_sz, 120*de9e57ffSJiafei Pan uint32_t shrd_dram_sz) 121*de9e57ffSJiafei Pan { 122*de9e57ffSJiafei Pan ERROR("tzc380_reg_list used is not a default list\n"); 123*de9e57ffSJiafei Pan ERROR("%s needs to be over-written.\n", __func__); 124*de9e57ffSJiafei Pan return 0; 125*de9e57ffSJiafei Pan } 126*de9e57ffSJiafei Pan #endif /* DEFAULT_TZASC_CONFIG */ 127*de9e57ffSJiafei Pan 128*de9e57ffSJiafei Pan 129*de9e57ffSJiafei Pan void mem_access_setup(uintptr_t base, uint32_t total_regions, 130*de9e57ffSJiafei Pan struct tzc380_reg *tzc380_reg_list) 131*de9e57ffSJiafei Pan { 132*de9e57ffSJiafei Pan uint32_t indx = 0; 133*de9e57ffSJiafei Pan unsigned int attr_value; 134*de9e57ffSJiafei Pan 135*de9e57ffSJiafei Pan VERBOSE("Configuring TrustZone Controller tzc380\n"); 136*de9e57ffSJiafei Pan 137*de9e57ffSJiafei Pan tzc380_init(base); 138*de9e57ffSJiafei Pan 139*de9e57ffSJiafei Pan tzc380_set_action(TZC_ACTION_NONE); 140*de9e57ffSJiafei Pan 141*de9e57ffSJiafei Pan for (indx = 0; indx < total_regions; indx++) { 142*de9e57ffSJiafei Pan attr_value = tzc380_reg_list[indx].secure | 143*de9e57ffSJiafei Pan TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) | 144*de9e57ffSJiafei Pan TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) | 145*de9e57ffSJiafei Pan tzc380_reg_list[indx].enabled; 146*de9e57ffSJiafei Pan 147*de9e57ffSJiafei Pan tzc380_configure_region(indx, tzc380_reg_list[indx].addr, 148*de9e57ffSJiafei Pan attr_value); 149*de9e57ffSJiafei Pan } 150*de9e57ffSJiafei Pan 151*de9e57ffSJiafei Pan tzc380_set_action(TZC_ACTION_ERR); 152*de9e57ffSJiafei Pan } 153