1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * NXP FlexSpi Controller Driver. 4 * Copyright 2021 NXP 5 * 6 */ 7 #include <endian.h> 8 #include <stdint.h> 9 #include <stdio.h> 10 #include <string.h> 11 12 #include <common/debug.h> 13 #include <flash_info.h> 14 #include "fspi.h" 15 #include <fspi_api.h> 16 #include <xspi_error_codes.h> 17 18 #ifdef DEBUG_FLEXSPI 19 #define PR printf("In [%s][%d]\n", __func__, __LINE__) 20 #define PRA(a, b) printf("In [%s][%d] %s="a"\n", __func__, __LINE__, #b, b) 21 #else 22 #define PR 23 #define PRA(a, b) 24 #endif 25 26 /* 27 * This errata is valid for all NXP SoC. 28 */ 29 #define ERRATA_FLASH_A050272 1 30 31 static uintptr_t fspi_base_reg_addr; 32 static uintptr_t fspi_flash_base_addr; 33 34 static void fspi_RDSR(uint32_t *, const void *, uint32_t); 35 36 static void fspi_writel(uint32_t x_addr, uint32_t x_val) 37 { 38 fspi_out32((uint32_t *)(fspi_base_reg_addr + x_addr), 39 (uint32_t) x_val); 40 } 41 42 static uint32_t fspi_readl(uint32_t x_addr) 43 { 44 return fspi_in32((uint32_t *)(fspi_base_reg_addr + x_addr)); 45 } 46 47 static void fspi_MDIS(uint8_t x_disable) 48 { 49 uint32_t ui_reg; 50 51 ui_reg = fspi_readl(FSPI_MCR0); 52 if (x_disable != 0U) { 53 ui_reg |= FSPI_MCR0_MDIS; 54 } else { 55 ui_reg &= (uint32_t) (~FSPI_MCR0_MDIS); 56 } 57 58 fspi_writel(FSPI_MCR0, ui_reg); 59 } 60 61 static void fspi_lock_LUT(void) 62 { 63 fspi_writel(FSPI_LUTKEY, FSPI_LUTKEY_VALUE); 64 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); 65 fspi_writel(FSPI_LCKCR, FSPI_LCKER_LOCK); 66 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); 67 } 68 69 static void fspi_unlock_LUT(void) 70 { 71 fspi_writel(FSPI_LUTKEY, FSPI_LUTKEY_VALUE); 72 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); 73 fspi_writel(FSPI_LCKCR, FSPI_LCKER_UNLOCK); 74 VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR)); 75 } 76 77 static void fspi_op_setup(uint32_t fspi_op_seq_id, bool ignore_flash_sz) 78 { 79 uint32_t x_addr, x_instr0 = 0, x_instr1 = 0, x_instr2 = 0; 80 uint32_t cmd_id1, cmd_id2; 81 82 VERBOSE("In func %s\n", __func__); 83 84 switch (fspi_op_seq_id) { 85 case FSPI_READ_SEQ_ID: 86 cmd_id1 = FSPI_NOR_CMD_READ; 87 cmd_id2 = FSPI_NOR_CMD_READ_4B; 88 x_instr2 = FSPI_INSTR_OPRND0(0) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1) 89 | FSPI_INSTR_OPCODE0(FSPI_LUT_READ); 90 break; 91 case FSPI_FASTREAD_SEQ_ID: 92 cmd_id1 = FSPI_NOR_CMD_FASTREAD; 93 cmd_id2 = FSPI_NOR_CMD_FASTREAD_4B; 94 x_instr2 = FSPI_INSTR_OPRND0(8) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1) 95 | FSPI_INSTR_OPCODE0(FSPI_DUMMY_SDR) 96 | FSPI_INSTR_OPRND1(0) 97 | FSPI_INSTR_PAD1(FSPI_LUT_PAD1) 98 | FSPI_INSTR_OPCODE1(FSPI_LUT_READ); 99 break; 100 case FSPI_WRITE_SEQ_ID: 101 cmd_id1 = FSPI_NOR_CMD_PP; 102 cmd_id2 = FSPI_NOR_CMD_PP_4B; 103 x_instr2 = FSPI_INSTR_OPRND0(0) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1) 104 | FSPI_INSTR_OPCODE0(FSPI_LUT_WRITE); 105 break; 106 case FSPI_WREN_SEQ_ID: 107 cmd_id1 = FSPI_NOR_CMD_WREN; 108 cmd_id2 = FSPI_NOR_CMD_WREN; 109 break; 110 case FSPI_SE_SEQ_ID: 111 cmd_id1 = FSPI_NOR_CMD_SE_64K; 112 cmd_id2 = FSPI_NOR_CMD_SE_64K_4B; 113 break; 114 case FSPI_4K_SEQ_ID: 115 cmd_id1 = FSPI_NOR_CMD_SE_4K; 116 cmd_id2 = FSPI_NOR_CMD_SE_4K_4B; 117 break; 118 case FSPI_BE_SEQ_ID: 119 cmd_id1 = FSPI_NOR_CMD_BE; 120 cmd_id2 = FSPI_NOR_CMD_BE; 121 break; 122 case FSPI_RDSR_SEQ_ID: 123 cmd_id1 = FSPI_NOR_CMD_RDSR; 124 cmd_id2 = FSPI_NOR_CMD_RDSR; 125 break; 126 } 127 128 x_addr = FSPI_LUTREG_OFFSET + (uint32_t)(0x10 * fspi_op_seq_id); 129 if ((F_FLASH_SIZE_BYTES <= SZ_16M_BYTES) || (ignore_flash_sz)) { 130 x_instr0 = FSPI_INSTR_OPRND0(cmd_id1); 131 x_instr1 = FSPI_INSTR_OPRND1(FSPI_LUT_ADDR24BIT); 132 VERBOSE("CMD_ID = %x offset = 0x%x\n", cmd_id1, x_addr); 133 } else { 134 x_instr0 = FSPI_INSTR_OPRND0(cmd_id2); 135 x_instr1 = FSPI_INSTR_OPRND1(FSPI_LUT_ADDR32BIT); 136 VERBOSE("CMD_ID = %x offset = 0x%x\n", cmd_id2, x_addr); 137 } 138 x_instr0 |= FSPI_INSTR_PAD0(FSPI_LUT_PAD1) 139 | FSPI_INSTR_OPCODE0(FSPI_LUT_CMD); 140 141 x_instr1 |= FSPI_INSTR_PAD1(FSPI_LUT_PAD1) 142 | FSPI_INSTR_OPCODE1(FSPI_LUT_ADDR); 143 144 if (fspi_op_seq_id == FSPI_RDSR_SEQ_ID) { 145 x_instr0 |= FSPI_INSTR_OPRND1(1) | FSPI_INSTR_PAD1(FSPI_LUT_PAD1) 146 | FSPI_INSTR_OPCODE1(FSPI_LUT_READ); 147 } else if ((fspi_op_seq_id != FSPI_BE_SEQ_ID) 148 && (fspi_op_seq_id != FSPI_WREN_SEQ_ID)) { 149 x_instr0 |= x_instr1; 150 } 151 152 fspi_writel((x_addr), x_instr0); 153 fspi_writel((x_addr + U(0x4)), x_instr2); 154 fspi_writel((x_addr + U(0x8)), (uint32_t) 0x0); /* STOP command */ 155 fspi_writel((x_addr + U(0xc)), (uint32_t) 0x0); /* STOP command */ 156 } 157 158 static void fspi_setup_LUT(void) 159 { 160 VERBOSE("In func %s\n", __func__); 161 fspi_unlock_LUT(); 162 163 /* LUT Setup for READ Command 3-Byte low Frequency */ 164 fspi_op_setup(FSPI_READ_SEQ_ID, false); 165 166 /* LUT Setup for FAST READ Command 3-Byte/4-Byte high Frequency */ 167 fspi_op_setup(FSPI_FASTREAD_SEQ_ID, false); 168 169 /* LUT Setup for Page Program */ 170 fspi_op_setup(FSPI_WRITE_SEQ_ID, false); 171 172 /* LUT Setup for WREN */ 173 fspi_op_setup(FSPI_WREN_SEQ_ID, true); 174 175 /* LUT Setup for Sector_Erase */ 176 fspi_op_setup(FSPI_SE_SEQ_ID, false); 177 178 /* LUT Setup for Sub Sector 4K Erase */ 179 fspi_op_setup(FSPI_4K_SEQ_ID, false); 180 181 /* LUT Setup for Bulk_Erase */ 182 fspi_op_setup(FSPI_BE_SEQ_ID, true); 183 184 /* Read Status */ 185 fspi_op_setup(FSPI_RDSR_SEQ_ID, true); 186 187 fspi_lock_LUT(); 188 } 189 190 static inline void fspi_ahb_invalidate(void) 191 { 192 uint32_t reg; 193 194 VERBOSE("In func %s %d\n", __func__, __LINE__); 195 reg = fspi_readl(FSPI_MCR0); 196 reg |= FSPI_MCR0_SWRST; 197 fspi_writel(FSPI_MCR0, reg); 198 while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST) != 0) 199 ; /* FSPI_MCR0_SWRESET_MASK */ 200 VERBOSE("In func %s %d\n", __func__, __LINE__); 201 } 202 203 #if defined(CONFIG_FSPI_AHB) 204 static void fspi_init_ahb(void) 205 { 206 uint32_t i, x_flash_cr2, seq_id; 207 208 x_flash_cr2 = 0; 209 /* Reset AHB RX buffer CR configuration */ 210 for (i = 0; i < 8; i++) { 211 fspi_writel((FSPI_AHBRX_BUF0CR0 + 4 * i), 0U); 212 } 213 214 /* Set ADATSZ with the maximum AHB buffer size */ 215 fspi_writel(FSPI_AHBRX_BUF7CR0, 216 ((uint32_t) ((FSPI_RX_MAX_AHBBUF_SIZE / 8U) | 217 FSPI_AHBRXBUF0CR7_PREF))); 218 219 /* Known limitation handling: prefetch and 220 * no start address alignment.*/ 221 fspi_writel(FSPI_AHBCR, FSPI_AHBCR_PREF_EN); 222 INFO("xAhbcr=0x%x\n", fspi_readl(FSPI_AHBCR)); 223 224 // Setup AHB READ sequenceID for all flashes. 225 x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2); 226 INFO("x_flash_cr2=0x%x\n", x_flash_cr2); 227 228 seq_id = CONFIG_FSPI_FASTREAD ? 229 FSPI_FASTREAD_SEQ_ID : FSPI_READ_SEQ_ID; 230 x_flash_cr2 |= ((seq_id << FSPI_FLSHXCR2_ARDSEQI_SHIFT) & 0x1f); 231 232 INFO("x_flash_cr2=0x%x\n", x_flash_cr2); 233 234 fspi_writel(FSPI_FLSHA1CR2, x_flash_cr2); 235 x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2); 236 INFO("x_flash_cr2=0x%x\n", x_flash_cr2); 237 } 238 #endif 239 240 int xspi_read(uint32_t pc_rx_addr, uint32_t *pc_rx_buf, uint32_t x_size_bytes) 241 { 242 if (x_size_bytes == 0) { 243 ERROR("Zero length reads are not allowed\n"); 244 return XSPI_READ_FAIL; 245 } 246 247 #if defined(CONFIG_FSPI_AHB) 248 return xspi_ahb_read(pc_rx_addr, pc_rx_buf, x_size_bytes); 249 #else 250 return xspi_ip_read(pc_rx_addr, pc_rx_buf, x_size_bytes); 251 #endif 252 } 253 #if defined(CONFIG_FSPI_AHB) 254 int xspi_ahb_read(uint32_t pc_rx_addr, uint32_t *pc_rx_buf, uint32_t x_size_bytes) 255 { 256 VERBOSE("In func %s 0x%x\n", __func__, (pc_rx_addr)); 257 258 if (F_FLASH_SIZE_BYTES <= SZ_16M_BYTES) { 259 pc_rx_addr = ((uint32_t)(pcRxAddr & MASK_24BIT_ADDRESS)); 260 } else { 261 pc_rx_addr = ((uint32_t)(pcRxAddr & MASK_32BIT_ADDRESS)); 262 } 263 264 pc_rx_addr = ((uint32_t)(pcRxAddr + fspi_flash_base_addr)); 265 266 if (((pc_rx_addr % 4) != 0) || (((uintptr_t)pc_rx_buf % 4) != 0)) { 267 WARN("%s: unaligned Start Address src=%ld dst=0x%p\n", 268 __func__, (pc_rx_addr - fspi_flash_base_addr), pc_rx_buf); 269 } 270 271 /* Directly copy from AHB Buffer */ 272 memcpy(pc_rx_buf, (void *)(uintptr_t)pc_rx_addr, x_size_bytes); 273 274 fspi_ahb_invalidate(); 275 return XSPI_SUCCESS; 276 } 277 #endif 278 279 int xspi_ip_read(uint32_t pc_rx_addr, uint32_t *pv_rx_buf, uint32_t ui_len) 280 { 281 282 uint32_t i = 0U, j = 0U, x_rem = 0U; 283 uint32_t x_iteration = 0U, x_size_rx = 0U, x_size_wm, temp_size; 284 uint32_t data = 0U; 285 uint32_t x_len_bytes; 286 uint32_t x_addr, sts0, intr, seq_id; 287 288 x_addr = (uint32_t) pc_rx_addr; 289 x_len_bytes = ui_len; 290 291 /* Watermark level : 8 bytes. (BY DEFAULT) */ 292 x_size_wm = 8U; 293 294 /* Clear RX Watermark interrupt in INT register, if any existing. */ 295 fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA); 296 PRA("0x%x", fspi_readl(FSPI_INTR)); 297 /* Invalid the RXFIFO, to run next IP Command */ 298 /* Clears data entries in IP Rx FIFOs, Also reset R/W pointers */ 299 fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR); 300 fspi_writel(FSPI_INTR, FSPI_INTEN_IPCMDDONE); 301 302 while (x_len_bytes) { 303 304 /* FlexSPI can store no more than FSPI_RX_IPBUF_SIZE */ 305 x_size_rx = (x_len_bytes > FSPI_RX_IPBUF_SIZE) ? 306 FSPI_RX_IPBUF_SIZE : x_len_bytes; 307 308 /* IP Control Register0 - SF Address to be read */ 309 fspi_writel(FSPI_IPCR0, x_addr); 310 PRA("0x%x", fspi_readl(FSPI_IPCR0)); 311 /* IP Control Register1 - SEQID_READ operation, Size */ 312 313 seq_id = CONFIG_FSPI_FASTREAD ? 314 FSPI_FASTREAD_SEQ_ID : FSPI_READ_SEQ_ID; 315 316 fspi_writel(FSPI_IPCR1, 317 (uint32_t)(seq_id << FSPI_IPCR1_ISEQID_SHIFT) | 318 (uint16_t) x_size_rx); 319 320 PRA("0x%x", fspi_readl(FSPI_IPCR1)); 321 322 do { 323 sts0 = fspi_readl(FSPI_STS0); 324 } while (((sts0 & FSPI_STS0_ARB_IDLE) == 0) && 325 ((sts0 & FSPI_STS0_SEQ_IDLE) == 0)); 326 327 /* Trigger IP Read Command */ 328 fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK); 329 PRA("0x%x", fspi_readl(FSPI_IPCMD)); 330 331 intr = fspi_readl(FSPI_INTR); 332 if (((intr & FSPI_INTR_IPCMDGE) != 0) || 333 ((intr & FSPI_INTR_IPCMDERR) != 0)) { 334 ERROR("Error in IP READ INTR=0x%x\n", intr); 335 return -XSPI_IP_READ_FAIL; 336 } 337 /* Will read in n iterations of each 8 FIFO's(WM level) */ 338 x_iteration = x_size_rx / x_size_wm; 339 for (i = 0U; i < x_iteration; i++) { 340 if ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK) == 0) { 341 PRA("0x%x", fspi_readl(FSPI_INTR)); 342 } 343 /* Wait for IP Rx Watermark Fill event */ 344 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK)) { 345 PRA("0x%x", fspi_readl(FSPI_INTR)); 346 } 347 348 /* Read RX FIFO's(upto WM level) & copy to rxbuffer */ 349 for (j = 0U; j < x_size_wm; j += 4U) { 350 /* Read FIFO Data Register */ 351 data = fspi_readl(FSPI_RFDR + j); 352 #if FSPI_IPDATA_SWAP /* Just In case you want swap */ 353 data = bswap32(data); 354 #endif 355 memcpy(pv_rx_buf++, &data, 4); 356 } 357 358 /* Clear IP_RX_WATERMARK Event in INTR register */ 359 /* Reset FIFO Read pointer for next iteration.*/ 360 fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA); 361 } 362 363 x_rem = x_size_rx % x_size_wm; 364 365 if (x_rem != 0U) { 366 /* Wait for data filled */ 367 while (!(fspi_readl(FSPI_IPRXFSTS) & FSPI_IPRXFSTS_FILL_MASK)) { 368 PRA("0x%x", fspi_readl(FSPI_IPRXFSTS)); 369 } 370 371 temp_size = 0; 372 j = 0U; 373 while (x_rem > 0U) { 374 data = 0U; 375 data = fspi_readl(FSPI_RFDR + j); 376 #if FSPI_IPDATA_SWAP /* Just In case you want swap */ 377 data = bswap32(data); 378 #endif 379 temp_size = (x_rem < 4) ? x_rem : 4; 380 memcpy(pv_rx_buf++, &data, temp_size); 381 x_rem -= temp_size; 382 } 383 } 384 385 386 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) { 387 PRA("0x%x", fspi_readl(FSPI_INTR)); 388 } 389 390 /* Invalid the RX FIFO, to run next IP Command */ 391 fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR); 392 /* Clear IP Command Done flag in interrupt register*/ 393 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 394 395 /* Update remaining len, Increment x_addr read pointer. */ 396 x_len_bytes -= x_size_rx; 397 x_addr += x_size_rx; 398 } 399 PR; 400 return XSPI_SUCCESS; 401 } 402 403 void xspi_ip_write(uint32_t pc_wr_addr, uint32_t *pv_wr_buf, uint32_t ui_len) 404 { 405 406 uint32_t x_iteration = 0U, x_rem = 0U; 407 uint32_t x_size_tx = 0U, x_size_wm, temp_size; 408 uint32_t i = 0U, j = 0U; 409 uint32_t ui_data = 0U; 410 uint32_t x_addr, x_len_bytes; 411 412 413 x_size_wm = 8U; /* Default TX WaterMark level: 8 Bytes. */ 414 x_addr = (uint32_t)pc_wr_addr; 415 x_len_bytes = ui_len; 416 VERBOSE("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n", 417 __func__, __LINE__, x_addr, x_len_bytes); 418 419 while (x_len_bytes != 0U) { 420 421 x_size_tx = (x_len_bytes > FSPI_TX_IPBUF_SIZE) ? 422 FSPI_TX_IPBUF_SIZE : x_len_bytes; 423 424 /* IP Control Register0 - SF Address to be read */ 425 fspi_writel(FSPI_IPCR0, x_addr); 426 INFO("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n", 427 __func__, __LINE__, x_addr, x_len_bytes); 428 429 /* 430 * Fill TX FIFO's.. 431 * 432 */ 433 434 x_iteration = x_size_tx / x_size_wm; 435 for (i = 0U; i < x_iteration; i++) { 436 437 /* Ensure TX FIFO Watermark Available */ 438 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE_MASK) == 0) 439 ; 440 441 442 /* Fill TxFIFO's ( upto watermark level) */ 443 for (j = 0U; j < x_size_wm; j += 4U) { 444 memcpy(&ui_data, pv_wr_buf++, 4); 445 /* Write TX FIFO Data Register */ 446 fspi_writel((FSPI_TFDR + j), ui_data); 447 448 } 449 450 /* Clear IP_TX_WATERMARK Event in INTR register */ 451 /* Reset the FIFO Write pointer for next iteration */ 452 fspi_writel(FSPI_INTR, FSPI_INTR_IPTXWE); 453 } 454 455 x_rem = x_size_tx % x_size_wm; 456 457 if (x_rem != 0U) { 458 /* Wait for TXFIFO empty */ 459 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE)) 460 ; 461 462 temp_size = 0U; 463 j = 0U; 464 while (x_rem > 0U) { 465 ui_data = 0U; 466 temp_size = (x_rem < 4U) ? x_rem : 4U; 467 memcpy(&ui_data, pv_wr_buf++, temp_size); 468 INFO("%d ---> pv_wr_buf=0x%p\n", __LINE__, pv_wr_buf); 469 fspi_writel((FSPI_TFDR + j), ui_data); 470 x_rem -= temp_size; 471 j += 4U ; /* TODO: May not be needed*/ 472 } 473 /* Clear IP_TX_WATERMARK Event in INTR register */ 474 /* Reset FIFO's Write pointer for next iteration.*/ 475 fspi_writel(FSPI_INTR, FSPI_INTR_IPTXWE); 476 } 477 478 /* IP Control Register1 - SEQID_WRITE operation, Size */ 479 fspi_writel(FSPI_IPCR1, (uint32_t)(FSPI_WRITE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | (uint16_t) x_size_tx); 480 /* Trigger IP Write Command */ 481 fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK); 482 483 /* Wait for IP Write command done */ 484 while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) 485 ; 486 487 /* Invalidate TX FIFOs & acknowledge IP_CMD_DONE event */ 488 fspi_writel(FSPI_IPTXFCR, FSPI_IPTXFCR_CLR); 489 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 490 491 /* for next iteration */ 492 x_len_bytes -= x_size_tx; 493 x_addr += x_size_tx; 494 } 495 496 } 497 498 int xspi_write(uint32_t pc_wr_addr, void *pv_wr_buf, uint32_t ui_len) 499 { 500 501 uint32_t x_addr; 502 uint32_t x_page1_len = 0U, x_page_l_len = 0U; 503 uint32_t i, j = 0U; 504 void *buf = pv_wr_buf; 505 506 VERBOSE("\nIn func %s\n", __func__); 507 508 x_addr = (uint32_t)(pc_wr_addr); 509 if ((ui_len <= F_PAGE_256) && ((x_addr % F_PAGE_256) == 0)) { 510 x_page1_len = ui_len; 511 INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j); 512 } else if ((ui_len <= F_PAGE_256) && ((x_addr % F_PAGE_256) != 0)) { 513 x_page1_len = (F_PAGE_256 - (x_addr % F_PAGE_256)); 514 if (ui_len > x_page1_len) { 515 x_page_l_len = (ui_len - x_page1_len) % F_PAGE_256; 516 } else { 517 x_page1_len = ui_len; 518 x_page_l_len = 0; 519 } 520 j = 0U; 521 INFO("%d 0x%x 0x%x\n", x_addr % F_PAGE_256, x_addr % F_PAGE_256, F_PAGE_256); 522 INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j); 523 } else if ((ui_len > F_PAGE_256) && ((x_addr % F_PAGE_256) == 0)) { 524 j = ui_len / F_PAGE_256; 525 x_page_l_len = ui_len % F_PAGE_256; 526 INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j); 527 } else if ((ui_len > F_PAGE_256) && ((x_addr % F_PAGE_256) != 0)) { 528 x_page1_len = (F_PAGE_256 - (x_addr % F_PAGE_256)); 529 j = (ui_len - x_page1_len) / F_PAGE_256; 530 x_page_l_len = (ui_len - x_page1_len) % F_PAGE_256; 531 INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j); 532 } 533 534 if (x_page1_len != 0U) { 535 xspi_wren(x_addr); 536 xspi_ip_write(x_addr, (uint32_t *)buf, x_page1_len); 537 while (is_flash_busy()) 538 ; 539 INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n", 540 __LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr)); 541 INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf); 542 x_addr += x_page1_len; 543 /* TODO What is buf start is not 4 aligned */ 544 buf = buf + x_page1_len; 545 } 546 547 for (i = 0U; i < j; i++) { 548 INFO("In for loop Buf pv_wr_buf=%p, final Buf=%p x_addr=0x%x offset_buf %d.\n", 549 pv_wr_buf, buf, x_addr, x_page1_len/4); 550 xspi_wren(x_addr); 551 xspi_ip_write(x_addr, (uint32_t *)buf, F_PAGE_256); 552 while (is_flash_busy()) 553 ; 554 INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n", 555 __LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr)); 556 x_addr += F_PAGE_256; 557 /* TODO What is buf start is not 4 aligned */ 558 buf = buf + F_PAGE_256; 559 INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf); 560 } 561 562 if (x_page_l_len != 0U) { 563 INFO("%d Initial Buf pv_wr_buf=%p, final Buf=%p x_page_l_len=0x%x\n", __LINE__, pv_wr_buf, buf, x_page_l_len); 564 xspi_wren(x_addr); 565 xspi_ip_write(x_addr, (uint32_t *)buf, x_page_l_len); 566 while (is_flash_busy()) 567 ; 568 INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n", 569 __LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr)); 570 } 571 572 VERBOSE("Now calling func call Invalidate%s\n", __func__); 573 fspi_ahb_invalidate(); 574 return XSPI_SUCCESS; 575 } 576 577 int xspi_wren(uint32_t pc_wr_addr) 578 { 579 VERBOSE("In func %s Addr=0x%x\n", __func__, pc_wr_addr); 580 581 fspi_writel(FSPI_IPTXFCR, FSPI_IPTXFCR_CLR); 582 583 fspi_writel(FSPI_IPCR0, (uint32_t)pc_wr_addr); 584 fspi_writel(FSPI_IPCR1, ((FSPI_WREN_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0)); 585 fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK); 586 587 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) 588 ; 589 590 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 591 return XSPI_SUCCESS; 592 } 593 594 static void fspi_bbluk_er(void) 595 { 596 VERBOSE("In func %s\n", __func__); 597 fspi_writel(FSPI_IPCR0, 0x0); 598 fspi_writel(FSPI_IPCR1, ((FSPI_BE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 20)); 599 fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK); 600 601 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) 602 ; 603 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 604 605 } 606 607 static void fspi_RDSR(uint32_t *rxbuf, const void *p_addr, uint32_t size) 608 { 609 uint32_t iprxfcr = 0U; 610 uint32_t data = 0U; 611 612 iprxfcr = fspi_readl(FSPI_IPRXFCR); 613 /* IP RX FIFO would be read by processor */ 614 iprxfcr = iprxfcr & (uint32_t)~FSPI_IPRXFCR_CLR; 615 /* Invalid data entries in IP RX FIFO */ 616 iprxfcr = iprxfcr | FSPI_IPRXFCR_CLR; 617 fspi_writel(FSPI_IPRXFCR, iprxfcr); 618 619 fspi_writel(FSPI_IPCR0, (uintptr_t) p_addr); 620 fspi_writel(FSPI_IPCR1, 621 (uint32_t) ((FSPI_RDSR_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) 622 | (uint16_t) size)); 623 /* Trigger the command */ 624 fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK); 625 /* Wait for command done */ 626 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) 627 ; 628 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 629 630 data = fspi_readl(FSPI_RFDR); 631 memcpy(rxbuf, &data, size); 632 633 /* Rx FIFO invalidation needs to be done prior w1c of INTR.IPRXWA bit */ 634 fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR); 635 fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA_MASK); 636 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 637 638 } 639 640 bool is_flash_busy(void) 641 { 642 #define FSPI_ONE_BYTE 1 643 uint8_t data[4]; 644 645 VERBOSE("In func %s\n\n", __func__); 646 fspi_RDSR((uint32_t *) data, 0, FSPI_ONE_BYTE); 647 648 return !!((uint32_t) data[0] & FSPI_NOR_SR_WIP_MASK); 649 } 650 651 int xspi_bulk_erase(void) 652 { 653 VERBOSE("In func %s\n", __func__); 654 xspi_wren((uint32_t) 0x0); 655 fspi_bbluk_er(); 656 while (is_flash_busy()) 657 ; 658 fspi_ahb_invalidate(); 659 return XSPI_SUCCESS; 660 } 661 662 static void fspi_sec_er(uint32_t pc_wr_addr) 663 { 664 uint32_t x_addr; 665 666 VERBOSE("In func %s\n", __func__); 667 x_addr = (uint32_t)(pc_wr_addr); 668 669 fspi_writel(FSPI_IPCR0, x_addr); 670 INFO("In [%s][%d] Erase address 0x%x\n", __func__, __LINE__, (x_addr)); 671 #if CONFIG_FSPI_ERASE_4K 672 fspi_writel(FSPI_IPCR1, ((FSPI_4K_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0)); 673 #else 674 fspi_writel(FSPI_IPCR1, ((FSPI_SE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0)); 675 #endif 676 fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK); 677 678 while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) { 679 PRA("0x%x", fspi_readl(FSPI_INTR)); 680 } 681 fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK); 682 } 683 684 int xspi_sector_erase(uint32_t pc_wr_addr, uint32_t ui_len) 685 { 686 uint32_t x_addr, x_len_bytes, i, num_sector = 0U; 687 688 VERBOSE("In func %s\n", __func__); 689 x_addr = (uint32_t)(pc_wr_addr); 690 if ((x_addr % F_SECTOR_ERASE_SZ) != 0) { 691 ERROR("!!! In func %s, unalinged start address can only be in multiples of 0x%x\n", 692 __func__, F_SECTOR_ERASE_SZ); 693 return -XSPI_ERASE_FAIL; 694 } 695 696 x_len_bytes = ui_len * 1; 697 if (x_len_bytes < F_SECTOR_ERASE_SZ) { 698 ERROR("!!! In func %s, Less than 1 sector can only be in multiples of 0x%x\n", 699 __func__, F_SECTOR_ERASE_SZ); 700 return -XSPI_ERASE_FAIL; 701 } 702 703 num_sector = x_len_bytes/F_SECTOR_ERASE_SZ; 704 num_sector += x_len_bytes % F_SECTOR_ERASE_SZ ? 1U : 0U; 705 INFO("F_SECTOR_ERASE_SZ: 0x%08x, num_sector: %d\n", F_SECTOR_ERASE_SZ, num_sector); 706 707 for (i = 0U; i < num_sector ; i++) { 708 xspi_wren(x_addr + (F_SECTOR_ERASE_SZ * i)); 709 fspi_sec_er(x_addr + (F_SECTOR_ERASE_SZ * i)); 710 while (is_flash_busy()) 711 ; 712 } 713 fspi_ahb_invalidate(); 714 return XSPI_SUCCESS; 715 } 716 717 718 __attribute__((unused)) static void fspi_delay_ms(uint32_t x) 719 { 720 volatile unsigned long ul_count; 721 722 for (ul_count = 0U; ul_count < (30U * x); ul_count++) 723 ; 724 725 } 726 727 728 #if defined(DEBUG_FLEXSPI) 729 static void fspi_dump_regs(void) 730 { 731 uint32_t i; 732 733 VERBOSE("\nRegisters Dump:\n"); 734 VERBOSE("Flexspi: Register FSPI_MCR0(0x%x) = 0x%08x\n", FSPI_MCR0, fspi_readl(FSPI_MCR0)); 735 VERBOSE("Flexspi: Register FSPI_MCR2(0x%x) = 0x%08x\n", FSPI_MCR2, fspi_readl(FSPI_MCR2)); 736 VERBOSE("Flexspi: Register FSPI_DLL_A_CR(0x%x) = 0x%08x\n", FSPI_DLLACR, fspi_readl(FSPI_DLLACR)); 737 VERBOSE("\n"); 738 739 for (i = 0U; i < 8U; i++) { 740 VERBOSE("Flexspi: Register FSPI_AHBRX_BUF0CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF0CR0 + i * 4, fspi_readl((FSPI_AHBRX_BUF0CR0 + i * 4))); 741 } 742 VERBOSE("\n"); 743 744 VERBOSE("Flexspi: Register FSPI_AHBRX_BUF7CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF7CR0, fspi_readl(FSPI_AHBRX_BUF7CR0)); 745 VERBOSE("Flexspi: Register FSPI_AHB_CR(0x%x) \t = 0x%08x\n", FSPI_AHBCR, fspi_readl(FSPI_AHBCR)); 746 VERBOSE("\n"); 747 748 for (i = 0U; i < 4U; i++) { 749 VERBOSE("Flexspi: Register FSPI_FLSH_A1_CR2,(0x%x) = 0x%08x\n", FSPI_FLSHA1CR2 + i * 4, fspi_readl(FSPI_FLSHA1CR2 + i * 4)); 750 } 751 } 752 #endif 753 754 int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr) 755 { 756 uint32_t mcrx; 757 uint32_t flash_size; 758 759 if (fspi_base_reg_addr != 0U) { 760 INFO("FSPI is already initialized.\n"); 761 return XSPI_SUCCESS; 762 } 763 764 fspi_base_reg_addr = base_reg_addr; 765 fspi_flash_base_addr = flash_start_addr; 766 767 INFO("Flexspi driver: Version v1.0\n"); 768 INFO("Flexspi: Default MCR0 = 0x%08x, before reset\n", fspi_readl(FSPI_MCR0)); 769 VERBOSE("Flexspi: Resetting controller...\n"); 770 771 /* Reset FlexSpi Controller */ 772 fspi_writel(FSPI_MCR0, FSPI_MCR0_SWRST); 773 while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST)) 774 ; /* FSPI_MCR0_SWRESET_MASK */ 775 776 777 /* Disable Controller Module before programming its registersi, especially MCR0 (Master Control Register0) */ 778 fspi_MDIS(1); 779 /* 780 * Program MCR0 with default values, AHB Timeout(0xff), IP Timeout(0xff). {FSPI_MCR0- 0xFFFF0000} 781 */ 782 783 /* Timeout wait cycle for AHB command grant */ 784 mcrx = fspi_readl(FSPI_MCR0); 785 mcrx |= (uint32_t)((FSPI_MAX_TIMEOUT_AHBCMD << FSPI_MCR0_AHBGRANTWAIT_SHIFT) & (FSPI_MCR0_AHBGRANTWAIT_MASK)); 786 787 /* Time out wait cycle for IP command grant*/ 788 mcrx |= (uint32_t) (FSPI_MAX_TIMEOUT_IPCMD << FSPI_MCR0_IPGRANTWAIT_SHIFT) & (FSPI_MCR0_IPGRANTWAIT_MASK); 789 790 /* TODO why BE64 set BE32*/ 791 mcrx |= (uint32_t) (FSPI_ENDCFG_LE64 << FSPI_MCR0_ENDCFG_SHIFT) & FSPI_MCR0_ENDCFG_MASK; 792 793 fspi_writel(FSPI_MCR0, mcrx); 794 795 /* Reset the DLL register to default value */ 796 fspi_writel(FSPI_DLLACR, FSPI_DLLACR_OVRDEN); 797 fspi_writel(FSPI_DLLBCR, FSPI_DLLBCR_OVRDEN); 798 799 #if ERRATA_FLASH_A050272 /* ERRATA DLL */ 800 for (uint8_t delay = 100U; delay > 0U; delay--) { 801 __asm__ volatile ("nop"); 802 } 803 #endif 804 805 /* Configure flash control registers for different chip select */ 806 flash_size = (F_FLASH_SIZE_BYTES * FLASH_NUM) / FSPI_BYTES_PER_KBYTES; 807 fspi_writel(FSPI_FLSHA1CR0, flash_size); 808 fspi_writel(FSPI_FLSHA2CR0, 0U); 809 fspi_writel(FSPI_FLSHB1CR0, 0U); 810 fspi_writel(FSPI_FLSHB2CR0, 0U); 811 812 #if defined(CONFIG_FSPI_AHB) 813 fspi_init_ahb(); 814 #endif 815 /* RE-Enable Controller Module */ 816 fspi_MDIS(0); 817 INFO("Flexspi: After MCR0 = 0x%08x,\n", fspi_readl(FSPI_MCR0)); 818 fspi_setup_LUT(); 819 820 /* Dump of all registers, ensure controller not disabled anymore*/ 821 #if defined(DEBUG_FLEXSPI) 822 fspi_dump_regs(); 823 #endif 824 825 INFO("Flexspi: Init done!!\n"); 826 827 #if DEBUG_FLEXSPI 828 829 uint32_t xspi_addr = SZ_57M; 830 831 /* 832 * Second argument of fspi_test is the size of buffer(s) passed 833 * to the function. 834 * SIZE_BUFFER defined in test_fspi.c is kept large enough to 835 * accommodate variety of sizes for regressive tests. 836 */ 837 fspi_test(xspi_addr, 0x40, 0); 838 fspi_test(xspi_addr, 0x15, 2); 839 fspi_test(xspi_addr, 0x80, 0); 840 fspi_test(xspi_addr, 0x81, 0); 841 fspi_test(xspi_addr, 0x79, 3); 842 843 fspi_test(xspi_addr + 0x11, 0x15, 0); 844 fspi_test(xspi_addr + 0x11, 0x40, 0); 845 fspi_test(xspi_addr + 0xff, 0x40, 1); 846 fspi_test(xspi_addr + 0x25, 0x81, 2); 847 fspi_test(xspi_addr + 0xef, 0x6f, 3); 848 849 fspi_test((xspi_addr - F_SECTOR_ERASE_SZ), 0x229, 0); 850 #endif 851 852 return XSPI_SUCCESS; 853 } 854