1*b525a8f0SKuldeep Singh /* 2*b525a8f0SKuldeep Singh * Copyright 2020 NXP 3*b525a8f0SKuldeep Singh * 4*b525a8f0SKuldeep Singh * SPDX-License-Identifier: BSD-3-Clause 5*b525a8f0SKuldeep Singh * 6*b525a8f0SKuldeep Singh */ 7*b525a8f0SKuldeep Singh 8*b525a8f0SKuldeep Singh #ifndef FLEXSPI_NOR_H 9*b525a8f0SKuldeep Singh #define FLEXSPI_NOR_H 10*b525a8f0SKuldeep Singh 11*b525a8f0SKuldeep Singh int flexspi_nor_io_setup(uintptr_t nxp_flexspi_flash_addr, 12*b525a8f0SKuldeep Singh size_t nxp_flexspi_flash_size, 13*b525a8f0SKuldeep Singh uint32_t fspi_base_reg_addr); 14*b525a8f0SKuldeep Singh 15*b525a8f0SKuldeep Singh #endif /* FLEXSPI_NOR_H */ 16