1 /* 2 * Copyright 2020-2023, 2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <ddr_init.h> 8 9 /* Ensure optimal phy pll settings for selected frequency. */ 10 void set_optimal_pll(uint16_t frequency) 11 { 12 /* Configure phy pll registers */ 13 mmio_write_32(MASTER_PLLCTRL1, PLLCTRL1_VALUE); 14 mmio_write_32(MASTER_PLLTESTMODE, PLLTESTMODE_VALUE); 15 mmio_write_32(MASTER_PLLCTRL4, PLLCTRL4_VALUE); 16 mmio_write_32(MASTER_PLLCTRL2, pllctrl2_value(frequency)); 17 18 mmio_setbits_32(MASTER_CALMISC2, (CALMISC2 << CALMISC2_OFFSET)); 19 20 mmio_clrsetbits_32(MASTER_CALOFFSET, 21 CALDRV_MASK, ((CALDRV << CALDRV_OFFSET) | (CALDRV << CALDRV2_OFFSET))); 22 } 23