1 /* 2 * Copyright 2020 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <common/debug.h> 9 #include "dcfg.h" 10 #include <lib/mmio.h> 11 #ifdef NXP_SFP_ENABLED 12 #include <sfp.h> 13 #endif 14 15 static soc_info_t soc_info = {0}; 16 static devdisr5_info_t devdisr5_info = {0}; 17 static dcfg_init_info_t *dcfg_init_info; 18 19 /* Read the PORSR1 register */ 20 uint32_t read_reg_porsr1(void) 21 { 22 unsigned int *porsr1_addr = NULL; 23 24 if (dcfg_init_info->porsr1 != 0U) { 25 return dcfg_init_info->porsr1; 26 } 27 28 porsr1_addr = (void *) 29 (dcfg_init_info->g_nxp_dcfg_addr + DCFG_PORSR1_OFFSET); 30 dcfg_init_info->porsr1 = gur_in32(porsr1_addr); 31 32 return dcfg_init_info->porsr1; 33 } 34 35 36 const soc_info_t *get_soc_info(void) 37 { 38 uint32_t reg; 39 40 if (soc_info.is_populated == true) { 41 return (const soc_info_t *) &soc_info; 42 } 43 44 reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET); 45 46 soc_info.mfr_id = (reg & SVR_MFR_ID_MASK) >> SVR_MFR_ID_SHIFT; 47 #if defined(CONFIG_CHASSIS_3_2) 48 soc_info.family = (reg & SVR_FAMILY_MASK) >> SVR_FAMILY_SHIFT; 49 soc_info.dev_id = (reg & SVR_DEV_ID_MASK) >> SVR_DEV_ID_SHIFT; 50 #endif 51 /* zero means SEC enabled. */ 52 soc_info.sec_enabled = 53 (((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false; 54 55 soc_info.personality = (reg & SVR_PERSONALITY_MASK) 56 >> SVR_PERSONALITY_SHIFT; 57 soc_info.maj_ver = (reg & SVR_MAJ_VER_MASK) >> SVR_MAJ_VER_SHIFT; 58 soc_info.min_ver = reg & SVR_MIN_VER_MASK; 59 60 soc_info.is_populated = true; 61 return (const soc_info_t *) &soc_info; 62 } 63 64 void dcfg_init(dcfg_init_info_t *dcfg_init_data) 65 { 66 dcfg_init_info = dcfg_init_data; 67 read_reg_porsr1(); 68 get_soc_info(); 69 } 70 71 bool is_sec_enabled(void) 72 { 73 return soc_info.sec_enabled; 74 } 75 76 const devdisr5_info_t *get_devdisr5_info(void) 77 { 78 uint32_t reg; 79 80 if (devdisr5_info.is_populated == true) 81 return (const devdisr5_info_t *) &devdisr5_info; 82 83 reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET); 84 85 #if defined(CONFIG_CHASSIS_3_2) 86 devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1; 87 devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1; 88 devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1; 89 #elif defined(CONFIG_CHASSIS_2) 90 devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1; 91 devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1; 92 #endif 93 devdisr5_info.is_populated = true; 94 95 return (const devdisr5_info_t *) &devdisr5_info; 96 } 97 98 int get_clocks(struct sysinfo *sys) 99 { 100 unsigned int *rcwsr0 = NULL; 101 const unsigned long sysclk = dcfg_init_info->nxp_sysclk_freq; 102 const unsigned long ddrclk = dcfg_init_info->nxp_ddrclk_freq; 103 104 rcwsr0 = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR0_OFFSET); 105 sys->freq_platform = sysclk; 106 sys->freq_ddr_pll0 = ddrclk; 107 sys->freq_ddr_pll1 = ddrclk; 108 109 sys->freq_platform *= (gur_in32(rcwsr0) >> 110 RCWSR0_SYS_PLL_RAT_SHIFT) & 111 RCWSR0_SYS_PLL_RAT_MASK; 112 113 sys->freq_platform /= dcfg_init_info->nxp_plat_clk_divider; 114 115 sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >> 116 RCWSR0_MEM_PLL_RAT_SHIFT) & 117 RCWSR0_MEM_PLL_RAT_MASK; 118 sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >> 119 RCWSR0_MEM2_PLL_RAT_SHIFT) & 120 RCWSR0_MEM2_PLL_RAT_MASK; 121 if (sys->freq_platform == 0) { 122 return 1; 123 } else { 124 return 0; 125 } 126 } 127 128 #ifdef NXP_SFP_ENABLED 129 /******************************************************************************* 130 * Returns true if secur eboot is enabled on board 131 * mode = 0 (development mode - sb_en = 1) 132 * mode = 1 (production mode - ITS = 1) 133 ******************************************************************************/ 134 bool check_boot_mode_secure(uint32_t *mode) 135 { 136 uint32_t val = 0U; 137 uint32_t *rcwsr = NULL; 138 *mode = 0U; 139 140 if (sfp_check_its() == 1) { 141 /* ITS =1 , Production mode */ 142 *mode = 1U; 143 return true; 144 } 145 146 rcwsr = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR_SB_EN_OFFSET); 147 148 val = (gur_in32(rcwsr) >> RCWSR_SBEN_SHIFT) & 149 RCWSR_SBEN_MASK; 150 151 if (val == RCWSR_SBEN_MASK) { 152 *mode = 0U; 153 return true; 154 } 155 156 return false; 157 } 158 #endif 159 160 void error_handler(int error_code) 161 { 162 /* Dump error code in SCRATCH4 register */ 163 INFO("Error in Fuse Provisioning: %x\n", error_code); 164 gur_out32((void *) 165 (dcfg_init_info->g_nxp_dcfg_addr + DCFG_SCRATCH4_OFFSET), 166 error_code); 167 } 168