xref: /rk3399_ARM-atf/drivers/nxp/clk/s32cc/s32cc_early_clks.c (revision 83af45042debcaf76f2f898984f1b74dedc477e1)
166af5425SGhennadi Procopciuc /*
266af5425SGhennadi Procopciuc  * Copyright 2024 NXP
366af5425SGhennadi Procopciuc  *
466af5425SGhennadi Procopciuc  * SPDX-License-Identifier: BSD-3-Clause
566af5425SGhennadi Procopciuc  */
666af5425SGhennadi Procopciuc #include <drivers/clk.h>
766af5425SGhennadi Procopciuc #include <s32cc-clk-drv.h>
866af5425SGhennadi Procopciuc #include <s32cc-clk-ids.h>
966af5425SGhennadi Procopciuc #include <s32cc-clk-utils.h>
1066af5425SGhennadi Procopciuc 
1166af5425SGhennadi Procopciuc #define S32CC_FXOSC_FREQ	(40U * MHZ)
1266af5425SGhennadi Procopciuc 
1366af5425SGhennadi Procopciuc int s32cc_init_early_clks(void)
1466af5425SGhennadi Procopciuc {
1566af5425SGhennadi Procopciuc 	int ret;
1666af5425SGhennadi Procopciuc 
1766af5425SGhennadi Procopciuc 	s32cc_clk_register_drv();
1866af5425SGhennadi Procopciuc 
19*83af4504SGhennadi Procopciuc 	ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
20*83af4504SGhennadi Procopciuc 	if (ret != 0) {
21*83af4504SGhennadi Procopciuc 		return ret;
22*83af4504SGhennadi Procopciuc 	}
23*83af4504SGhennadi Procopciuc 
24*83af4504SGhennadi Procopciuc 	ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
25*83af4504SGhennadi Procopciuc 	if (ret != 0) {
26*83af4504SGhennadi Procopciuc 		return ret;
27*83af4504SGhennadi Procopciuc 	}
28*83af4504SGhennadi Procopciuc 
2966af5425SGhennadi Procopciuc 	ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
3066af5425SGhennadi Procopciuc 	if (ret != 0) {
3166af5425SGhennadi Procopciuc 		return ret;
3266af5425SGhennadi Procopciuc 	}
3366af5425SGhennadi Procopciuc 
348ab34357SGhennadi Procopciuc 	ret = clk_enable(S32CC_CLK_FXOSC);
358ab34357SGhennadi Procopciuc 	if (ret != 0) {
368ab34357SGhennadi Procopciuc 		return ret;
378ab34357SGhennadi Procopciuc 	}
388ab34357SGhennadi Procopciuc 
3966af5425SGhennadi Procopciuc 	return ret;
4066af5425SGhennadi Procopciuc }
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